imx8mm-evk.dtsi 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494
  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright 2020 NXP
  4. */
  5. /dts-v1/;
  6. #include <dt-bindings/usb/pd.h>
  7. #include "imx8mm.dtsi"
  8. / {
  9. chosen {
  10. stdout-path = &uart2;
  11. };
  12. memory@40000000 {
  13. device_type = "memory";
  14. reg = <0x0 0x40000000 0 0x80000000>;
  15. };
  16. leds {
  17. compatible = "gpio-leds";
  18. pinctrl-names = "default";
  19. pinctrl-0 = <&pinctrl_gpio_led>;
  20. status {
  21. label = "status";
  22. gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  23. default-state = "on";
  24. };
  25. };
  26. reg_usdhc2_vmmc: regulator-usdhc2 {
  27. compatible = "regulator-fixed";
  28. pinctrl-names = "default";
  29. pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  30. regulator-name = "VSD_3V3";
  31. regulator-min-microvolt = <3300000>;
  32. regulator-max-microvolt = <3300000>;
  33. gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  34. enable-active-high;
  35. };
  36. ir-receiver {
  37. compatible = "gpio-ir-receiver";
  38. gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
  39. pinctrl-names = "default";
  40. pinctrl-0 = <&pinctrl_ir>;
  41. linux,autosuspend-period = <125>;
  42. };
  43. wm8524: audio-codec {
  44. #sound-dai-cells = <0>;
  45. compatible = "wlf,wm8524";
  46. pinctrl-names = "default";
  47. pinctrl-0 = <&pinctrl_gpio_wlf>;
  48. wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
  49. };
  50. sound-wm8524 {
  51. compatible = "simple-audio-card";
  52. simple-audio-card,name = "wm8524-audio";
  53. simple-audio-card,format = "i2s";
  54. simple-audio-card,frame-master = <&cpudai>;
  55. simple-audio-card,bitclock-master = <&cpudai>;
  56. simple-audio-card,widgets =
  57. "Line", "Left Line Out Jack",
  58. "Line", "Right Line Out Jack";
  59. simple-audio-card,routing =
  60. "Left Line Out Jack", "LINEVOUTL",
  61. "Right Line Out Jack", "LINEVOUTR";
  62. cpudai: simple-audio-card,cpu {
  63. sound-dai = <&sai3>;
  64. dai-tdm-slot-num = <2>;
  65. dai-tdm-slot-width = <32>;
  66. };
  67. simple-audio-card,codec {
  68. sound-dai = <&wm8524>;
  69. clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
  70. };
  71. };
  72. };
  73. &A53_0 {
  74. cpu-supply = <&buck2_reg>;
  75. };
  76. &A53_1 {
  77. cpu-supply = <&buck2_reg>;
  78. };
  79. &A53_2 {
  80. cpu-supply = <&buck2_reg>;
  81. };
  82. &A53_3 {
  83. cpu-supply = <&buck2_reg>;
  84. };
  85. &fec1 {
  86. pinctrl-names = "default";
  87. pinctrl-0 = <&pinctrl_fec1>;
  88. phy-mode = "rgmii-id";
  89. phy-handle = <&ethphy0>;
  90. fsl,magic-packet;
  91. status = "okay";
  92. mdio {
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. ethphy0: ethernet-phy@0 {
  96. compatible = "ethernet-phy-ieee802.3-c22";
  97. reg = <0>;
  98. reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  99. reset-assert-us = <10000>;
  100. };
  101. };
  102. };
  103. &i2c1 {
  104. clock-frequency = <400000>;
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&pinctrl_i2c1>;
  107. status = "okay";
  108. pmic: pca9450@25 {
  109. reg = <0x25>;
  110. compatible = "nxp,pca9450a";
  111. /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
  112. pinctrl-0 = <&pinctrl_pmic>;
  113. gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
  114. regulators {
  115. #address-cells = <1>;
  116. #size-cells = <0>;
  117. pca9450,pmic-buck2-uses-i2c-dvs;
  118. /* Run/Standby voltage */
  119. pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
  120. buck1_reg: regulator@0 {
  121. reg = <0>;
  122. regulator-compatible = "buck1";
  123. regulator-min-microvolt = <600000>;
  124. regulator-max-microvolt = <2187500>;
  125. regulator-boot-on;
  126. regulator-always-on;
  127. regulator-ramp-delay = <3125>;
  128. };
  129. buck2_reg: regulator@1 {
  130. reg = <1>;
  131. regulator-compatible = "buck2";
  132. regulator-min-microvolt = <600000>;
  133. regulator-max-microvolt = <2187500>;
  134. regulator-boot-on;
  135. regulator-always-on;
  136. regulator-ramp-delay = <3125>;
  137. };
  138. buck3_reg: regulator@2 {
  139. reg = <2>;
  140. regulator-compatible = "buck3";
  141. regulator-min-microvolt = <600000>;
  142. regulator-max-microvolt = <2187500>;
  143. regulator-boot-on;
  144. regulator-always-on;
  145. };
  146. buck4_reg: regulator@3 {
  147. reg = <3>;
  148. regulator-compatible = "buck4";
  149. regulator-min-microvolt = <600000>;
  150. regulator-max-microvolt = <3400000>;
  151. regulator-boot-on;
  152. regulator-always-on;
  153. };
  154. buck5_reg: regulator@4 {
  155. reg = <4>;
  156. regulator-compatible = "buck5";
  157. regulator-min-microvolt = <600000>;
  158. regulator-max-microvolt = <3400000>;
  159. regulator-boot-on;
  160. regulator-always-on;
  161. };
  162. buck6_reg: regulator@5 {
  163. reg = <5>;
  164. regulator-compatible = "buck6";
  165. regulator-min-microvolt = <600000>;
  166. regulator-max-microvolt = <3400000>;
  167. regulator-boot-on;
  168. regulator-always-on;
  169. };
  170. ldo1_reg: regulator@6 {
  171. reg = <6>;
  172. regulator-compatible = "ldo1";
  173. regulator-min-microvolt = <1600000>;
  174. regulator-max-microvolt = <3300000>;
  175. regulator-boot-on;
  176. regulator-always-on;
  177. };
  178. ldo2_reg: regulator@7 {
  179. reg = <7>;
  180. regulator-compatible = "ldo2";
  181. regulator-min-microvolt = <800000>;
  182. regulator-max-microvolt = <1150000>;
  183. regulator-boot-on;
  184. regulator-always-on;
  185. };
  186. ldo3_reg: regulator@8 {
  187. reg = <8>;
  188. regulator-compatible = "ldo3";
  189. regulator-min-microvolt = <800000>;
  190. regulator-max-microvolt = <3300000>;
  191. regulator-boot-on;
  192. regulator-always-on;
  193. };
  194. ldo4_reg: regulator@9 {
  195. reg = <9>;
  196. regulator-compatible = "ldo4";
  197. regulator-min-microvolt = <800000>;
  198. regulator-max-microvolt = <3300000>;
  199. regulator-boot-on;
  200. regulator-always-on;
  201. };
  202. ldo5_reg: regulator@10 {
  203. reg = <10>;
  204. regulator-compatible = "ldo5";
  205. regulator-min-microvolt = <1800000>;
  206. regulator-max-microvolt = <3300000>;
  207. };
  208. };
  209. };
  210. };
  211. &i2c2 {
  212. clock-frequency = <400000>;
  213. pinctrl-names = "default";
  214. pinctrl-0 = <&pinctrl_i2c2>;
  215. status = "okay";
  216. ptn5110: tcpc@50 {
  217. compatible = "nxp,ptn5110";
  218. pinctrl-names = "default";
  219. pinctrl-0 = <&pinctrl_typec1>;
  220. reg = <0x50>;
  221. interrupt-parent = <&gpio2>;
  222. interrupts = <11 8>;
  223. status = "okay";
  224. port {
  225. typec1_dr_sw: endpoint {
  226. remote-endpoint = <&usb1_drd_sw>;
  227. };
  228. };
  229. typec1_con: connector {
  230. compatible = "usb-c-connector";
  231. label = "USB-C";
  232. power-role = "dual";
  233. data-role = "dual";
  234. try-power-role = "sink";
  235. source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
  236. sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
  237. PDO_VAR(5000, 20000, 3000)>;
  238. op-sink-microwatt = <15000000>;
  239. self-powered;
  240. };
  241. };
  242. };
  243. &i2c3 {
  244. clock-frequency = <400000>;
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&pinctrl_i2c3>;
  247. status = "okay";
  248. pca6416: gpio@20 {
  249. compatible = "ti,tca6416";
  250. reg = <0x20>;
  251. gpio-controller;
  252. #gpio-cells = <2>;
  253. };
  254. };
  255. &sai3 {
  256. pinctrl-names = "default";
  257. pinctrl-0 = <&pinctrl_sai3>;
  258. assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
  259. assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  260. assigned-clock-rates = <24576000>;
  261. status = "okay";
  262. };
  263. &snvs_pwrkey {
  264. status = "okay";
  265. };
  266. &uart2 { /* console */
  267. pinctrl-names = "default";
  268. pinctrl-0 = <&pinctrl_uart2>;
  269. status = "okay";
  270. };
  271. &usbotg1 {
  272. dr_mode = "otg";
  273. hnp-disable;
  274. srp-disable;
  275. adp-disable;
  276. usb-role-switch;
  277. samsung,picophy-pre-emp-curr-control = <3>;
  278. samsung,picophy-dc-vol-level-adjust = <7>;
  279. status = "okay";
  280. port {
  281. usb1_drd_sw: endpoint {
  282. remote-endpoint = <&typec1_dr_sw>;
  283. };
  284. };
  285. };
  286. &usdhc2 {
  287. assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
  288. assigned-clock-rates = <200000000>;
  289. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  290. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  291. pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  292. pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  293. cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  294. bus-width = <4>;
  295. vmmc-supply = <&reg_usdhc2_vmmc>;
  296. status = "okay";
  297. };
  298. &wdog1 {
  299. pinctrl-names = "default";
  300. pinctrl-0 = <&pinctrl_wdog>;
  301. fsl,ext-reset-output;
  302. status = "okay";
  303. };
  304. &iomuxc {
  305. pinctrl_fec1: fec1grp {
  306. fsl,pins = <
  307. MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  308. MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
  309. MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  310. MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  311. MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  312. MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  313. MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  314. MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  315. MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  316. MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  317. MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  318. MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  319. MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  320. MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  321. MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
  322. >;
  323. };
  324. pinctrl_gpio_led: gpioledgrp {
  325. fsl,pins = <
  326. MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
  327. >;
  328. };
  329. pinctrl_ir: irgrp {
  330. fsl,pins = <
  331. MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
  332. >;
  333. };
  334. pinctrl_gpio_wlf: gpiowlfgrp {
  335. fsl,pins = <
  336. MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
  337. >;
  338. };
  339. pinctrl_i2c1: i2c1grp {
  340. fsl,pins = <
  341. MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
  342. MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
  343. >;
  344. };
  345. pinctrl_i2c2: i2c2grp {
  346. fsl,pins = <
  347. MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
  348. MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
  349. >;
  350. };
  351. pinctrl_i2c3: i2c3grp {
  352. fsl,pins = <
  353. MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
  354. MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
  355. >;
  356. };
  357. pinctrl_pmic: pmicirqgrp {
  358. fsl,pins = <
  359. MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
  360. >;
  361. };
  362. pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
  363. fsl,pins = <
  364. MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
  365. >;
  366. };
  367. pinctrl_sai3: sai3grp {
  368. fsl,pins = <
  369. MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
  370. MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
  371. MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
  372. MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
  373. >;
  374. };
  375. pinctrl_typec1: typec1grp {
  376. fsl,pins = <
  377. MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
  378. >;
  379. };
  380. pinctrl_uart2: uart2grp {
  381. fsl,pins = <
  382. MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
  383. MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
  384. >;
  385. };
  386. pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
  387. fsl,pins = <
  388. MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
  389. >;
  390. };
  391. pinctrl_usdhc2: usdhc2grp {
  392. fsl,pins = <
  393. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
  394. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
  395. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
  396. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
  397. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
  398. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
  399. MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  400. >;
  401. };
  402. pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
  403. fsl,pins = <
  404. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
  405. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
  406. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
  407. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
  408. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
  409. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
  410. MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  411. >;
  412. };
  413. pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
  414. fsl,pins = <
  415. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
  416. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
  417. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
  418. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
  419. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
  420. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
  421. MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  422. >;
  423. };
  424. pinctrl_wdog: wdoggrp {
  425. fsl,pins = <
  426. MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
  427. >;
  428. };
  429. };