imx6qdl-gw5912.dtsi 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. led2 = &led2;
  14. mmc0 = &usdhc3;
  15. nand = &gpmi;
  16. usb0 = &usbh1;
  17. usb1 = &usbotg;
  18. };
  19. chosen {
  20. stdout-path = &uart2;
  21. };
  22. gpio-keys {
  23. compatible = "gpio-keys";
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. user-pb {
  27. label = "user_pb";
  28. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  29. linux,code = <BTN_0>;
  30. };
  31. user-pb1x {
  32. label = "user_pb1x";
  33. linux,code = <BTN_1>;
  34. interrupt-parent = <&gsc>;
  35. interrupts = <0>;
  36. };
  37. key-erased {
  38. label = "key-erased";
  39. linux,code = <BTN_2>;
  40. interrupt-parent = <&gsc>;
  41. interrupts = <1>;
  42. };
  43. eeprom-wp {
  44. label = "eeprom_wp";
  45. linux,code = <BTN_3>;
  46. interrupt-parent = <&gsc>;
  47. interrupts = <2>;
  48. };
  49. tamper {
  50. label = "tamper";
  51. linux,code = <BTN_4>;
  52. interrupt-parent = <&gsc>;
  53. interrupts = <5>;
  54. };
  55. switch-hold {
  56. label = "switch_hold";
  57. linux,code = <BTN_5>;
  58. interrupt-parent = <&gsc>;
  59. interrupts = <7>;
  60. };
  61. };
  62. leds {
  63. compatible = "gpio-leds";
  64. pinctrl-names = "default";
  65. pinctrl-0 = <&pinctrl_gpio_leds>;
  66. led0: user1 {
  67. label = "user1";
  68. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  69. default-state = "on";
  70. linux,default-trigger = "heartbeat";
  71. };
  72. led1: user2 {
  73. label = "user2";
  74. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  75. default-state = "off";
  76. };
  77. led2: user3 {
  78. label = "user3";
  79. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  80. default-state = "off";
  81. };
  82. };
  83. memory@10000000 {
  84. device_type = "memory";
  85. reg = <0x10000000 0x40000000>;
  86. };
  87. pps {
  88. compatible = "pps-gpio";
  89. pinctrl-names = "default";
  90. pinctrl-0 = <&pinctrl_pps>;
  91. gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  92. };
  93. reg_3p3v: regulator-3p3v {
  94. compatible = "regulator-fixed";
  95. regulator-name = "3P3V";
  96. regulator-min-microvolt = <3300000>;
  97. regulator-max-microvolt = <3300000>;
  98. regulator-always-on;
  99. };
  100. reg_usb_vbus: regulator-5p0v {
  101. compatible = "regulator-fixed";
  102. regulator-name = "usb_vbus";
  103. regulator-min-microvolt = <5000000>;
  104. regulator-max-microvolt = <5000000>;
  105. regulator-always-on;
  106. };
  107. };
  108. &can1 {
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_flexcan1>;
  111. status = "okay";
  112. };
  113. &ecspi2 {
  114. cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
  115. pinctrl-names = "default";
  116. pinctrl-0 = <&pinctrl_ecspi2>;
  117. status = "okay";
  118. };
  119. &fec {
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&pinctrl_enet>;
  122. phy-mode = "rgmii-id";
  123. status = "okay";
  124. };
  125. &gpmi {
  126. pinctrl-names = "default";
  127. pinctrl-0 = <&pinctrl_gpmi_nand>;
  128. status = "okay";
  129. };
  130. &i2c1 {
  131. clock-frequency = <100000>;
  132. pinctrl-names = "default";
  133. pinctrl-0 = <&pinctrl_i2c1>;
  134. status = "okay";
  135. gsc: gsc@20 {
  136. compatible = "gw,gsc";
  137. reg = <0x20>;
  138. interrupt-parent = <&gpio1>;
  139. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  140. interrupt-controller;
  141. #interrupt-cells = <1>;
  142. #address-cells = <1>;
  143. #size-cells = <0>;
  144. adc {
  145. compatible = "gw,gsc-adc";
  146. #address-cells = <1>;
  147. #size-cells = <0>;
  148. channel@0 {
  149. gw,mode = <0>;
  150. reg = <0x00>;
  151. label = "temp";
  152. };
  153. channel@2 {
  154. gw,mode = <1>;
  155. reg = <0x02>;
  156. label = "vdd_vin";
  157. };
  158. channel@5 {
  159. gw,mode = <1>;
  160. reg = <0x05>;
  161. label = "vdd_3p3";
  162. };
  163. channel@8 {
  164. gw,mode = <1>;
  165. reg = <0x08>;
  166. label = "vdd_bat";
  167. };
  168. channel@b {
  169. gw,mode = <1>;
  170. reg = <0x0b>;
  171. label = "vdd_5p0";
  172. };
  173. channel@e {
  174. gw,mode = <1>;
  175. reg = <0xe>;
  176. label = "vdd_arm";
  177. };
  178. channel@11 {
  179. gw,mode = <1>;
  180. reg = <0x11>;
  181. label = "vdd_soc";
  182. };
  183. channel@14 {
  184. gw,mode = <1>;
  185. reg = <0x14>;
  186. label = "vdd_3p0";
  187. };
  188. channel@17 {
  189. gw,mode = <1>;
  190. reg = <0x17>;
  191. label = "vdd_1p5";
  192. };
  193. channel@1d {
  194. gw,mode = <1>;
  195. reg = <0x1d>;
  196. label = "vdd_1p8";
  197. };
  198. channel@20 {
  199. gw,mode = <1>;
  200. reg = <0x20>;
  201. label = "vdd_1p0";
  202. };
  203. channel@23 {
  204. gw,mode = <1>;
  205. reg = <0x23>;
  206. label = "vdd_2p5";
  207. };
  208. };
  209. fan-controller@a {
  210. compatible = "gw,gsc-fan";
  211. #address-cells = <1>;
  212. #size-cells = <0>;
  213. reg = <0x0a>;
  214. };
  215. };
  216. gsc_gpio: gpio@23 {
  217. compatible = "nxp,pca9555";
  218. reg = <0x23>;
  219. gpio-controller;
  220. #gpio-cells = <2>;
  221. interrupt-parent = <&gsc>;
  222. interrupts = <4>;
  223. };
  224. eeprom@50 {
  225. compatible = "atmel,24c02";
  226. reg = <0x50>;
  227. pagesize = <16>;
  228. };
  229. eeprom@51 {
  230. compatible = "atmel,24c02";
  231. reg = <0x51>;
  232. pagesize = <16>;
  233. };
  234. eeprom@52 {
  235. compatible = "atmel,24c02";
  236. reg = <0x52>;
  237. pagesize = <16>;
  238. };
  239. eeprom@53 {
  240. compatible = "atmel,24c02";
  241. reg = <0x53>;
  242. pagesize = <16>;
  243. };
  244. rtc@68 {
  245. compatible = "dallas,ds1672";
  246. reg = <0x68>;
  247. };
  248. };
  249. &i2c2 {
  250. clock-frequency = <100000>;
  251. pinctrl-names = "default";
  252. pinctrl-0 = <&pinctrl_i2c2>;
  253. status = "okay";
  254. };
  255. &i2c3 {
  256. clock-frequency = <100000>;
  257. pinctrl-names = "default";
  258. pinctrl-0 = <&pinctrl_i2c3>;
  259. status = "okay";
  260. accel@19 {
  261. pinctrl-names = "default";
  262. pinctrl-0 = <&pinctrl_accel>;
  263. compatible = "st,lis2de12";
  264. reg = <0x19>;
  265. st,drdy-int-pin = <1>;
  266. interrupt-parent = <&gpio7>;
  267. interrupts = <13 0>;
  268. interrupt-names = "INT1";
  269. };
  270. };
  271. &pcie {
  272. pinctrl-names = "default";
  273. pinctrl-0 = <&pinctrl_pcie>;
  274. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  275. status = "okay";
  276. };
  277. &pwm1 {
  278. pinctrl-names = "default";
  279. pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
  280. status = "disabled";
  281. };
  282. &pwm2 {
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  285. status = "disabled";
  286. };
  287. &pwm3 {
  288. pinctrl-names = "default";
  289. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  290. status = "disabled";
  291. };
  292. &pwm4 {
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
  295. status = "disabled";
  296. };
  297. &uart1 {
  298. pinctrl-names = "default";
  299. pinctrl-0 = <&pinctrl_uart1>;
  300. rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
  301. status = "okay";
  302. };
  303. &uart2 {
  304. pinctrl-names = "default";
  305. pinctrl-0 = <&pinctrl_uart2>;
  306. status = "okay";
  307. };
  308. &uart5 {
  309. pinctrl-names = "default";
  310. pinctrl-0 = <&pinctrl_uart5>;
  311. status = "okay";
  312. };
  313. &usbotg {
  314. vbus-supply = <&reg_usb_vbus>;
  315. pinctrl-names = "default";
  316. pinctrl-0 = <&pinctrl_usbotg>;
  317. disable-over-current;
  318. dr_mode = "host";
  319. status = "okay";
  320. };
  321. &usbh1 {
  322. vbus-supply = <&reg_usb_vbus>;
  323. status = "okay";
  324. };
  325. &usdhc3 {
  326. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  327. pinctrl-0 = <&pinctrl_usdhc3>;
  328. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  329. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  330. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  331. vmmc-supply = <&reg_3p3v>;
  332. no-1-8-v; /* firmware will remove if board revision supports */
  333. status = "okay";
  334. };
  335. &wdog1 {
  336. status = "disabled";
  337. };
  338. &wdog2 {
  339. pinctrl-names = "default";
  340. pinctrl-0 = <&pinctrl_wdog>;
  341. fsl,ext-reset-output;
  342. status = "okay";
  343. };
  344. &iomuxc {
  345. pinctrl_accel: accelmuxgrp {
  346. fsl,pins = <
  347. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
  348. >;
  349. };
  350. pinctrl_enet: enetgrp {
  351. fsl,pins = <
  352. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  353. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  354. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  355. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  356. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  357. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  358. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  359. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  360. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  361. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  362. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  363. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  364. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  365. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  366. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  367. >;
  368. };
  369. pinctrl_ecspi2: escpi2grp {
  370. fsl,pins = <
  371. MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
  372. MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
  373. MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
  374. MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
  375. >;
  376. };
  377. pinctrl_flexcan1: flexcan1grp {
  378. fsl,pins = <
  379. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  380. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  381. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
  382. >;
  383. };
  384. pinctrl_gpio_leds: gpioledsgrp {
  385. fsl,pins = <
  386. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  387. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  388. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  389. >;
  390. };
  391. pinctrl_gpmi_nand: gpminandgrp {
  392. fsl,pins = <
  393. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  394. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  395. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  396. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  397. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  398. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  399. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  400. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  401. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  402. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  403. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  404. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  405. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  406. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  407. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  408. >;
  409. };
  410. pinctrl_i2c1: i2c1grp {
  411. fsl,pins = <
  412. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  413. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  414. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
  415. >;
  416. };
  417. pinctrl_i2c2: i2c2grp {
  418. fsl,pins = <
  419. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  420. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  421. >;
  422. };
  423. pinctrl_i2c3: i2c3grp {
  424. fsl,pins = <
  425. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  426. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  427. >;
  428. };
  429. pinctrl_pcie: pciegrp {
  430. fsl,pins = <
  431. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
  432. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
  433. >;
  434. };
  435. pinctrl_pps: ppsgrp {
  436. fsl,pins = <
  437. MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
  438. >;
  439. };
  440. pinctrl_pwm1: pwm1grp {
  441. fsl,pins = <
  442. MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
  443. >;
  444. };
  445. pinctrl_pwm2: pwm2grp {
  446. fsl,pins = <
  447. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  448. >;
  449. };
  450. pinctrl_pwm3: pwm3grp {
  451. fsl,pins = <
  452. MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  453. >;
  454. };
  455. pinctrl_pwm4: pwm4grp {
  456. fsl,pins = <
  457. MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
  458. >;
  459. };
  460. pinctrl_uart1: uart1grp {
  461. fsl,pins = <
  462. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  463. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  464. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
  465. >;
  466. };
  467. pinctrl_uart2: uart2grp {
  468. fsl,pins = <
  469. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  470. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  471. MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
  472. >;
  473. };
  474. pinctrl_uart5: uart5grp {
  475. fsl,pins = <
  476. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  477. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  478. >;
  479. };
  480. pinctrl_usbotg: usbotggrp {
  481. fsl,pins = <
  482. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
  483. >;
  484. };
  485. pinctrl_usdhc3: usdhc3grp {
  486. fsl,pins = <
  487. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  488. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  489. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  490. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  491. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  492. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  493. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  494. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  495. >;
  496. };
  497. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  498. fsl,pins = <
  499. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  500. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  501. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  502. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  503. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  504. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  505. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  506. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  507. >;
  508. };
  509. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  510. fsl,pins = <
  511. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  512. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  513. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  514. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  515. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  516. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  517. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  518. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  519. >;
  520. };
  521. pinctrl_wdog: wdoggrp {
  522. fsl,pins = <
  523. MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
  524. >;
  525. };
  526. };