imx6qdl-gw5907.dtsi 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. nand = &gpmi;
  14. usb0 = &usbh1;
  15. usb1 = &usbotg;
  16. };
  17. chosen {
  18. stdout-path = &uart2;
  19. };
  20. gpio-keys {
  21. compatible = "gpio-keys";
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. user-pb {
  25. label = "user_pb";
  26. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  27. linux,code = <BTN_0>;
  28. };
  29. user-pb1x {
  30. label = "user_pb1x";
  31. linux,code = <BTN_1>;
  32. interrupt-parent = <&gsc>;
  33. interrupts = <0>;
  34. };
  35. key-erased {
  36. label = "key-erased";
  37. linux,code = <BTN_2>;
  38. interrupt-parent = <&gsc>;
  39. interrupts = <1>;
  40. };
  41. eeprom-wp {
  42. label = "eeprom_wp";
  43. linux,code = <BTN_3>;
  44. interrupt-parent = <&gsc>;
  45. interrupts = <2>;
  46. };
  47. tamper {
  48. label = "tamper";
  49. linux,code = <BTN_4>;
  50. interrupt-parent = <&gsc>;
  51. interrupts = <5>;
  52. };
  53. switch-hold {
  54. label = "switch_hold";
  55. linux,code = <BTN_5>;
  56. interrupt-parent = <&gsc>;
  57. interrupts = <7>;
  58. };
  59. };
  60. leds {
  61. compatible = "gpio-leds";
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_gpio_leds>;
  64. led0: user1 {
  65. label = "user1";
  66. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  67. default-state = "on";
  68. linux,default-trigger = "heartbeat";
  69. };
  70. led1: user2 {
  71. label = "user2";
  72. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  73. default-state = "off";
  74. };
  75. };
  76. memory@10000000 {
  77. device_type = "memory";
  78. reg = <0x10000000 0x20000000>;
  79. };
  80. pps {
  81. compatible = "pps-gpio";
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&pinctrl_pps>;
  84. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  85. status = "okay";
  86. };
  87. reg_3p3v: regulator-3p3v {
  88. compatible = "regulator-fixed";
  89. regulator-name = "3P3V";
  90. regulator-min-microvolt = <3300000>;
  91. regulator-max-microvolt = <3300000>;
  92. regulator-always-on;
  93. };
  94. reg_5p0v: regulator-5p0v {
  95. compatible = "regulator-fixed";
  96. regulator-name = "5P0V";
  97. regulator-min-microvolt = <5000000>;
  98. regulator-max-microvolt = <5000000>;
  99. regulator-always-on;
  100. };
  101. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  102. compatible = "regulator-fixed";
  103. regulator-name = "usb_otg_vbus";
  104. regulator-min-microvolt = <5000000>;
  105. regulator-max-microvolt = <5000000>;
  106. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  107. enable-active-high;
  108. };
  109. };
  110. &fec {
  111. pinctrl-names = "default";
  112. pinctrl-0 = <&pinctrl_enet>;
  113. phy-mode = "rgmii-id";
  114. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  115. status = "okay";
  116. };
  117. &gpmi {
  118. pinctrl-names = "default";
  119. pinctrl-0 = <&pinctrl_gpmi_nand>;
  120. status = "okay";
  121. };
  122. &hdmi {
  123. ddc-i2c-bus = <&i2c3>;
  124. status = "okay";
  125. };
  126. &i2c1 {
  127. clock-frequency = <100000>;
  128. pinctrl-names = "default";
  129. pinctrl-0 = <&pinctrl_i2c1>;
  130. status = "okay";
  131. gsc: gsc@20 {
  132. compatible = "gw,gsc";
  133. reg = <0x20>;
  134. interrupt-parent = <&gpio1>;
  135. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  136. interrupt-controller;
  137. #interrupt-cells = <1>;
  138. #size-cells = <0>;
  139. adc {
  140. compatible = "gw,gsc-adc";
  141. #address-cells = <1>;
  142. #size-cells = <0>;
  143. channel@0 {
  144. gw,mode = <0>;
  145. reg = <0x00>;
  146. label = "temp";
  147. };
  148. channel@2 {
  149. gw,mode = <1>;
  150. reg = <0x02>;
  151. label = "vdd_vin";
  152. };
  153. channel@5 {
  154. gw,mode = <1>;
  155. reg = <0x05>;
  156. label = "vdd_3p3";
  157. };
  158. channel@8 {
  159. gw,mode = <1>;
  160. reg = <0x08>;
  161. label = "vdd_bat";
  162. };
  163. channel@b {
  164. gw,mode = <1>;
  165. reg = <0x0b>;
  166. label = "vdd_5p0";
  167. };
  168. channel@e {
  169. gw,mode = <1>;
  170. reg = <0xe>;
  171. label = "vdd_arm";
  172. };
  173. channel@11 {
  174. gw,mode = <1>;
  175. reg = <0x11>;
  176. label = "vdd_soc";
  177. };
  178. channel@14 {
  179. gw,mode = <1>;
  180. reg = <0x14>;
  181. label = "vdd_3p0";
  182. };
  183. channel@17 {
  184. gw,mode = <1>;
  185. reg = <0x17>;
  186. label = "vdd_1p5";
  187. };
  188. channel@1d {
  189. gw,mode = <1>;
  190. reg = <0x1d>;
  191. label = "vdd_1p8";
  192. };
  193. channel@20 {
  194. gw,mode = <1>;
  195. reg = <0x20>;
  196. label = "vdd_an1";
  197. };
  198. channel@23 {
  199. gw,mode = <1>;
  200. reg = <0x23>;
  201. label = "vdd_2p5";
  202. };
  203. };
  204. };
  205. gsc_gpio: gpio@23 {
  206. compatible = "nxp,pca9555";
  207. reg = <0x23>;
  208. gpio-controller;
  209. #gpio-cells = <2>;
  210. interrupt-parent = <&gsc>;
  211. interrupts = <4>;
  212. };
  213. eeprom@50 {
  214. compatible = "atmel,24c02";
  215. reg = <0x50>;
  216. pagesize = <16>;
  217. };
  218. eeprom@51 {
  219. compatible = "atmel,24c02";
  220. reg = <0x51>;
  221. pagesize = <16>;
  222. };
  223. eeprom@52 {
  224. compatible = "atmel,24c02";
  225. reg = <0x52>;
  226. pagesize = <16>;
  227. };
  228. eeprom@53 {
  229. compatible = "atmel,24c02";
  230. reg = <0x53>;
  231. pagesize = <16>;
  232. };
  233. ds1672@68 {
  234. compatible = "dallas,ds1672";
  235. reg = <0x68>;
  236. };
  237. };
  238. &i2c2 {
  239. clock-frequency = <100000>;
  240. pinctrl-names = "default";
  241. pinctrl-0 = <&pinctrl_i2c2>;
  242. status = "okay";
  243. };
  244. &i2c3 {
  245. clock-frequency = <100000>;
  246. pinctrl-names = "default";
  247. pinctrl-0 = <&pinctrl_i2c3>;
  248. status = "okay";
  249. gpio@20 {
  250. compatible = "nxp,pca9555";
  251. reg = <0x20>;
  252. gpio-controller;
  253. #gpio-cells = <2>;
  254. };
  255. adc@48 {
  256. compatible = "ti,ads1015";
  257. reg = <0x48>;
  258. #address-cells = <1>;
  259. #size-cells = <0>;
  260. channel@4 {
  261. reg = <4>;
  262. ti,gain = <0>;
  263. ti,datarate = <5>;
  264. };
  265. channel@5 {
  266. reg = <5>;
  267. ti,gain = <0>;
  268. ti,datarate = <5>;
  269. };
  270. channel@6 {
  271. reg = <6>;
  272. ti,gain = <0>;
  273. ti,datarate = <5>;
  274. };
  275. };
  276. };
  277. &pcie {
  278. pinctrl-names = "default";
  279. pinctrl-0 = <&pinctrl_pcie>;
  280. reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
  281. status = "okay";
  282. };
  283. &pwm2 {
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  286. status = "disabled";
  287. };
  288. &pwm3 {
  289. pinctrl-names = "default";
  290. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  291. status = "disabled";
  292. };
  293. &pwm4 {
  294. pinctrl-names = "default";
  295. pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
  296. status = "disabled";
  297. };
  298. &uart1 {
  299. pinctrl-names = "default";
  300. pinctrl-0 = <&pinctrl_uart1>;
  301. status = "okay";
  302. };
  303. &uart2 {
  304. pinctrl-names = "default";
  305. pinctrl-0 = <&pinctrl_uart2>;
  306. status = "okay";
  307. };
  308. &uart3 {
  309. pinctrl-names = "default";
  310. pinctrl-0 = <&pinctrl_uart3>;
  311. status = "okay";
  312. };
  313. &uart5 {
  314. pinctrl-names = "default";
  315. pinctrl-0 = <&pinctrl_uart5>;
  316. status = "okay";
  317. };
  318. &usbotg {
  319. vbus-supply = <&reg_usb_otg_vbus>;
  320. pinctrl-names = "default";
  321. pinctrl-0 = <&pinctrl_usbotg>;
  322. disable-over-current;
  323. dr_mode = "otg";
  324. status = "okay";
  325. };
  326. &usbh1 {
  327. status = "okay";
  328. };
  329. &wdog1 {
  330. pinctrl-names = "default";
  331. pinctrl-0 = <&pinctrl_wdog>;
  332. fsl,ext-reset-output;
  333. };
  334. &iomuxc {
  335. pinctrl_enet: enetgrp {
  336. fsl,pins = <
  337. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  338. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  339. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  340. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  341. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  342. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  343. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  344. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  345. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  346. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  347. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  348. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  349. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  350. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  351. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  352. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  353. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  354. >;
  355. };
  356. pinctrl_gpio_leds: gpioledsgrp {
  357. fsl,pins = <
  358. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  359. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  360. >;
  361. };
  362. pinctrl_gpmi_nand: gpminandgrp {
  363. fsl,pins = <
  364. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  365. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  366. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  367. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  368. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  369. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  370. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  371. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  372. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  373. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  374. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  375. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  376. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  377. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  378. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  379. >;
  380. };
  381. pinctrl_i2c1: i2c1grp {
  382. fsl,pins = <
  383. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  384. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  385. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
  386. >;
  387. };
  388. pinctrl_i2c2: i2c2grp {
  389. fsl,pins = <
  390. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  391. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  392. >;
  393. };
  394. pinctrl_i2c3: i2c3grp {
  395. fsl,pins = <
  396. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  397. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  398. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  399. MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
  400. >;
  401. };
  402. pinctrl_pcie: pciegrp {
  403. fsl,pins = <
  404. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
  405. >;
  406. };
  407. pinctrl_pps: ppsgrp {
  408. fsl,pins = <
  409. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  410. >;
  411. };
  412. pinctrl_pwm2: pwm2grp {
  413. fsl,pins = <
  414. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  415. >;
  416. };
  417. pinctrl_pwm3: pwm3grp {
  418. fsl,pins = <
  419. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  420. >;
  421. };
  422. pinctrl_pwm4: pwm4grp {
  423. fsl,pins = <
  424. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  425. >;
  426. };
  427. pinctrl_uart1: uart1grp {
  428. fsl,pins = <
  429. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  430. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  431. >;
  432. };
  433. pinctrl_uart2: uart2grp {
  434. fsl,pins = <
  435. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  436. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  437. >;
  438. };
  439. pinctrl_uart3: uart3grp {
  440. fsl,pins = <
  441. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  442. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  443. >;
  444. };
  445. pinctrl_uart5: uart5grp {
  446. fsl,pins = <
  447. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  448. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  449. >;
  450. };
  451. pinctrl_usbotg: usbotggrp {
  452. fsl,pins = <
  453. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  454. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
  455. >;
  456. };
  457. pinctrl_wdog: wdoggrp {
  458. fsl,pins = <
  459. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  460. >;
  461. };
  462. };