imx6qdl-gw5904.dtsi 17 KB

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  1. /*
  2. * Copyright 2017 Gateworks Corporation
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public
  20. * License along with this file; if not, write to the Free
  21. * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22. * MA 02110-1301 USA
  23. *
  24. * Or, alternatively,
  25. *
  26. * b) Permission is hereby granted, free of charge, to any person
  27. * obtaining a copy of this software and associated documentation
  28. * files (the "Software"), to deal in the Software without
  29. * restriction, including without limitation the rights to use,
  30. * copy, modify, merge, publish, distribute, sublicense, and/or
  31. * sell copies of the Software, and to permit persons to whom the
  32. * Software is furnished to do so, subject to the following
  33. * conditions:
  34. *
  35. * The above copyright notice and this permission notice shall be
  36. * included in all copies or substantial portions of the Software.
  37. *
  38. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45. * OTHER DEALINGS IN THE SOFTWARE.
  46. */
  47. #include <dt-bindings/gpio/gpio.h>
  48. #include <dt-bindings/input/linux-event-codes.h>
  49. #include <dt-bindings/interrupt-controller/irq.h>
  50. / {
  51. /* these are used by bootloader for disabling nodes */
  52. aliases {
  53. led0 = &led0;
  54. led1 = &led1;
  55. led2 = &led2;
  56. mmc0 = &usdhc3;
  57. usb0 = &usbh1;
  58. usb1 = &usbotg;
  59. };
  60. chosen {
  61. stdout-path = &uart2;
  62. };
  63. backlight {
  64. compatible = "pwm-backlight";
  65. pwms = <&pwm4 0 5000000>;
  66. brightness-levels = <0 4 8 16 32 64 128 255>;
  67. default-brightness-level = <7>;
  68. };
  69. gpio-keys {
  70. compatible = "gpio-keys";
  71. #address-cells = <1>;
  72. #size-cells = <0>;
  73. user-pb {
  74. label = "user_pb";
  75. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  76. linux,code = <BTN_0>;
  77. };
  78. user-pb1x {
  79. label = "user_pb1x";
  80. linux,code = <BTN_1>;
  81. interrupt-parent = <&gsc>;
  82. interrupts = <0>;
  83. };
  84. key-erased {
  85. label = "key-erased";
  86. linux,code = <BTN_2>;
  87. interrupt-parent = <&gsc>;
  88. interrupts = <1>;
  89. };
  90. eeprom-wp {
  91. label = "eeprom_wp";
  92. linux,code = <BTN_3>;
  93. interrupt-parent = <&gsc>;
  94. interrupts = <2>;
  95. };
  96. tamper {
  97. label = "tamper";
  98. linux,code = <BTN_4>;
  99. interrupt-parent = <&gsc>;
  100. interrupts = <5>;
  101. };
  102. switch-hold {
  103. label = "switch_hold";
  104. linux,code = <BTN_5>;
  105. interrupt-parent = <&gsc>;
  106. interrupts = <7>;
  107. };
  108. };
  109. leds {
  110. compatible = "gpio-leds";
  111. pinctrl-names = "default";
  112. pinctrl-0 = <&pinctrl_gpio_leds>;
  113. led0: user1 {
  114. label = "user1";
  115. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  116. default-state = "on";
  117. linux,default-trigger = "heartbeat";
  118. };
  119. led1: user2 {
  120. label = "user2";
  121. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  122. default-state = "off";
  123. };
  124. led2: user3 {
  125. label = "user3";
  126. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  127. default-state = "off";
  128. };
  129. };
  130. memory@10000000 {
  131. device_type = "memory";
  132. reg = <0x10000000 0x40000000>;
  133. };
  134. pps {
  135. compatible = "pps-gpio";
  136. pinctrl-names = "default";
  137. pinctrl-0 = <&pinctrl_pps>;
  138. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  139. };
  140. reg_1p0v: regulator-1p0v {
  141. compatible = "regulator-fixed";
  142. regulator-name = "1P0V";
  143. regulator-min-microvolt = <1000000>;
  144. regulator-max-microvolt = <1000000>;
  145. regulator-always-on;
  146. };
  147. reg_3p3v: regulator-3p3v {
  148. compatible = "regulator-fixed";
  149. regulator-name = "3P3V";
  150. regulator-min-microvolt = <3300000>;
  151. regulator-max-microvolt = <3300000>;
  152. regulator-always-on;
  153. };
  154. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  155. compatible = "regulator-fixed";
  156. regulator-name = "usb_h1_vbus";
  157. regulator-min-microvolt = <5000000>;
  158. regulator-max-microvolt = <5000000>;
  159. regulator-always-on;
  160. };
  161. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  162. compatible = "regulator-fixed";
  163. regulator-name = "usb_otg_vbus";
  164. regulator-min-microvolt = <5000000>;
  165. regulator-max-microvolt = <5000000>;
  166. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  167. enable-active-high;
  168. };
  169. };
  170. &clks {
  171. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  172. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  173. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  174. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  175. };
  176. &fec {
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&pinctrl_enet>;
  179. phy-mode = "rgmii-id";
  180. status = "okay";
  181. fixed-link {
  182. speed = <1000>;
  183. full-duplex;
  184. };
  185. mdio {
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. switch@0 {
  189. compatible = "marvell,mv88e6085";
  190. reg = <0>;
  191. ports {
  192. #address-cells = <1>;
  193. #size-cells = <0>;
  194. port@0 {
  195. reg = <0>;
  196. label = "lan4";
  197. };
  198. port@1 {
  199. reg = <1>;
  200. label = "lan3";
  201. };
  202. port@2 {
  203. reg = <2>;
  204. label = "lan2";
  205. };
  206. port@3 {
  207. reg = <3>;
  208. label = "lan1";
  209. };
  210. port@5 {
  211. reg = <5>;
  212. label = "cpu";
  213. ethernet = <&fec>;
  214. };
  215. };
  216. };
  217. };
  218. };
  219. &i2c1 {
  220. clock-frequency = <100000>;
  221. pinctrl-names = "default";
  222. pinctrl-0 = <&pinctrl_i2c1>;
  223. status = "okay";
  224. gsc: gsc@20 {
  225. compatible = "gw,gsc";
  226. reg = <0x20>;
  227. interrupt-parent = <&gpio1>;
  228. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  229. interrupt-controller;
  230. #interrupt-cells = <1>;
  231. #size-cells = <0>;
  232. adc {
  233. compatible = "gw,gsc-adc";
  234. #address-cells = <1>;
  235. #size-cells = <0>;
  236. channel@0 {
  237. gw,mode = <0>;
  238. reg = <0x00>;
  239. label = "temp";
  240. };
  241. channel@2 {
  242. gw,mode = <1>;
  243. reg = <0x02>;
  244. label = "vdd_vin";
  245. };
  246. channel@5 {
  247. gw,mode = <1>;
  248. reg = <0x05>;
  249. label = "vdd_3p3";
  250. };
  251. channel@8 {
  252. gw,mode = <1>;
  253. reg = <0x08>;
  254. label = "vdd_bat";
  255. };
  256. channel@b {
  257. gw,mode = <1>;
  258. reg = <0x0b>;
  259. label = "vdd_5p0";
  260. };
  261. channel@e {
  262. gw,mode = <1>;
  263. reg = <0xe>;
  264. label = "vdd_arm";
  265. };
  266. channel@11 {
  267. gw,mode = <1>;
  268. reg = <0x11>;
  269. label = "vdd_soc";
  270. };
  271. channel@14 {
  272. gw,mode = <1>;
  273. reg = <0x14>;
  274. label = "vdd_3p0";
  275. };
  276. channel@17 {
  277. gw,mode = <1>;
  278. reg = <0x17>;
  279. label = "vdd_1p5";
  280. };
  281. channel@1d {
  282. gw,mode = <1>;
  283. reg = <0x1d>;
  284. label = "vdd_1p8";
  285. };
  286. channel@20 {
  287. gw,mode = <1>;
  288. reg = <0x20>;
  289. label = "vdd_an1";
  290. };
  291. channel@23 {
  292. gw,mode = <1>;
  293. reg = <0x23>;
  294. label = "vdd_2p5";
  295. };
  296. };
  297. };
  298. gsc_gpio: gpio@23 {
  299. compatible = "nxp,pca9555";
  300. reg = <0x23>;
  301. gpio-controller;
  302. #gpio-cells = <2>;
  303. interrupt-parent = <&gsc>;
  304. interrupts = <4>;
  305. };
  306. eeprom1: eeprom@50 {
  307. compatible = "atmel,24c02";
  308. reg = <0x50>;
  309. pagesize = <16>;
  310. };
  311. eeprom2: eeprom@51 {
  312. compatible = "atmel,24c02";
  313. reg = <0x51>;
  314. pagesize = <16>;
  315. };
  316. eeprom3: eeprom@52 {
  317. compatible = "atmel,24c02";
  318. reg = <0x52>;
  319. pagesize = <16>;
  320. };
  321. eeprom4: eeprom@53 {
  322. compatible = "atmel,24c02";
  323. reg = <0x53>;
  324. pagesize = <16>;
  325. };
  326. dts1672: rtc@68 {
  327. compatible = "dallas,ds1672";
  328. reg = <0x68>;
  329. };
  330. };
  331. &i2c2 {
  332. clock-frequency = <100000>;
  333. pinctrl-names = "default";
  334. pinctrl-0 = <&pinctrl_i2c2>;
  335. status = "okay";
  336. magn@1c {
  337. compatible = "st,lsm9ds1-magn";
  338. reg = <0x1c>;
  339. pinctrl-names = "default";
  340. pinctrl-0 = <&pinctrl_mag>;
  341. interrupt-parent = <&gpio5>;
  342. interrupts = <17 IRQ_TYPE_EDGE_RISING>;
  343. };
  344. ltc3676: pmic@3c {
  345. compatible = "lltc,ltc3676";
  346. reg = <0x3c>;
  347. interrupt-parent = <&gpio1>;
  348. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  349. regulators {
  350. /* VDD_SOC (1+R1/R2 = 1.635) */
  351. reg_vdd_soc: sw1 {
  352. regulator-name = "vddsoc";
  353. regulator-min-microvolt = <674400>;
  354. regulator-max-microvolt = <1308000>;
  355. lltc,fb-voltage-divider = <127000 200000>;
  356. regulator-ramp-delay = <7000>;
  357. regulator-boot-on;
  358. regulator-always-on;
  359. };
  360. /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
  361. reg_1p8v: sw2 {
  362. regulator-name = "vdd1p8";
  363. regulator-min-microvolt = <1033310>;
  364. regulator-max-microvolt = <2004000>;
  365. lltc,fb-voltage-divider = <301000 200000>;
  366. regulator-ramp-delay = <7000>;
  367. regulator-boot-on;
  368. regulator-always-on;
  369. };
  370. /* VDD_ARM (1+R1/R2 = 1.635) */
  371. reg_vdd_arm: sw3 {
  372. regulator-name = "vddarm";
  373. regulator-min-microvolt = <674400>;
  374. regulator-max-microvolt = <1308000>;
  375. lltc,fb-voltage-divider = <127000 200000>;
  376. regulator-ramp-delay = <7000>;
  377. regulator-boot-on;
  378. regulator-always-on;
  379. };
  380. /* VDD_DDR (1+R1/R2 = 2.105) */
  381. reg_vdd_ddr: sw4 {
  382. regulator-name = "vddddr";
  383. regulator-min-microvolt = <868310>;
  384. regulator-max-microvolt = <1684000>;
  385. lltc,fb-voltage-divider = <221000 200000>;
  386. regulator-ramp-delay = <7000>;
  387. regulator-boot-on;
  388. regulator-always-on;
  389. };
  390. /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
  391. reg_2p5v: ldo2 {
  392. regulator-name = "vdd2p5";
  393. regulator-min-microvolt = <2490375>;
  394. regulator-max-microvolt = <2490375>;
  395. lltc,fb-voltage-divider = <487000 200000>;
  396. regulator-boot-on;
  397. regulator-always-on;
  398. };
  399. /* VDD_HIGH (1+R1/R2 = 4.17) */
  400. reg_3p0v: ldo4 {
  401. regulator-name = "vdd3p0";
  402. regulator-min-microvolt = <3023250>;
  403. regulator-max-microvolt = <3023250>;
  404. lltc,fb-voltage-divider = <634000 200000>;
  405. regulator-boot-on;
  406. regulator-always-on;
  407. };
  408. };
  409. };
  410. imu@6a {
  411. compatible = "st,lsm9ds1-imu";
  412. reg = <0x6a>;
  413. st,drdy-int-pin = <1>;
  414. pinctrl-names = "default";
  415. pinctrl-0 = <&pinctrl_imu>;
  416. interrupt-parent = <&gpio4>;
  417. interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
  418. };
  419. };
  420. &i2c3 {
  421. clock-frequency = <100000>;
  422. pinctrl-names = "default";
  423. pinctrl-0 = <&pinctrl_i2c3>;
  424. status = "okay";
  425. egalax_ts: touchscreen@4 {
  426. compatible = "eeti,egalax_ts";
  427. reg = <0x04>;
  428. interrupt-parent = <&gpio1>;
  429. interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
  430. wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
  431. };
  432. };
  433. &ldb {
  434. status = "okay";
  435. lvds-channel@0 {
  436. fsl,data-mapping = "spwg";
  437. fsl,data-width = <18>;
  438. status = "okay";
  439. display-timings {
  440. native-mode = <&timing0>;
  441. timing0: hsd100pxn1 {
  442. clock-frequency = <65000000>;
  443. hactive = <1024>;
  444. vactive = <768>;
  445. hback-porch = <220>;
  446. hfront-porch = <40>;
  447. vback-porch = <21>;
  448. vfront-porch = <7>;
  449. hsync-len = <60>;
  450. vsync-len = <10>;
  451. };
  452. };
  453. };
  454. };
  455. &pcie {
  456. pinctrl-names = "default";
  457. pinctrl-0 = <&pinctrl_pcie>;
  458. reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
  459. status = "okay";
  460. };
  461. &pwm2 {
  462. pinctrl-names = "default";
  463. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  464. status = "disabled";
  465. };
  466. &pwm3 {
  467. pinctrl-names = "default";
  468. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  469. status = "disabled";
  470. };
  471. &pwm4 {
  472. #pwm-cells = <2>;
  473. pinctrl-names = "default";
  474. pinctrl-0 = <&pinctrl_pwm4>;
  475. status = "okay";
  476. };
  477. &uart1 {
  478. pinctrl-names = "default";
  479. pinctrl-0 = <&pinctrl_uart1>;
  480. status = "okay";
  481. };
  482. &uart2 {
  483. pinctrl-names = "default";
  484. pinctrl-0 = <&pinctrl_uart2>;
  485. status = "okay";
  486. };
  487. &uart3 {
  488. pinctrl-names = "default";
  489. pinctrl-0 = <&pinctrl_uart3>;
  490. uart-has-rtscts;
  491. status = "okay";
  492. };
  493. &uart4 {
  494. pinctrl-names = "default";
  495. pinctrl-0 = <&pinctrl_uart4>;
  496. uart-has-rtscts;
  497. status = "okay";
  498. };
  499. &uart5 {
  500. pinctrl-names = "default";
  501. pinctrl-0 = <&pinctrl_uart5>;
  502. status = "okay";
  503. };
  504. &usbotg {
  505. vbus-supply = <&reg_usb_otg_vbus>;
  506. pinctrl-names = "default";
  507. pinctrl-0 = <&pinctrl_usbotg>;
  508. disable-over-current;
  509. dr_mode = "otg";
  510. status = "okay";
  511. };
  512. &usbh1 {
  513. vbus-supply = <&reg_usb_h1_vbus>;
  514. status = "okay";
  515. };
  516. &usdhc3 {
  517. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  518. pinctrl-0 = <&pinctrl_usdhc3>;
  519. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  520. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  521. non-removable;
  522. vmmc-supply = <&reg_3p3v>;
  523. keep-power-in-suspend;
  524. status = "okay";
  525. };
  526. &wdog1 {
  527. pinctrl-names = "default";
  528. pinctrl-0 = <&pinctrl_wdog>;
  529. fsl,ext-reset-output;
  530. };
  531. &iomuxc {
  532. pinctrl_enet: enetgrp {
  533. fsl,pins = <
  534. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  535. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  536. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  537. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  538. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  539. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  540. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  541. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  542. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  543. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  544. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  545. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  546. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  547. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  548. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  549. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  550. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
  551. >;
  552. };
  553. pinctrl_gpio_leds: gpioledsgrp {
  554. fsl,pins = <
  555. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  556. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  557. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  558. >;
  559. };
  560. pinctrl_i2c1: i2c1grp {
  561. fsl,pins = <
  562. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  563. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  564. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
  565. >;
  566. };
  567. pinctrl_i2c2: i2c2grp {
  568. fsl,pins = <
  569. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  570. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  571. >;
  572. };
  573. pinctrl_i2c3: i2c3grp {
  574. fsl,pins = <
  575. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  576. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  577. >;
  578. };
  579. pinctrl_imu: imugrp {
  580. fsl,pins = <
  581. MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
  582. >;
  583. };
  584. pinctrl_mag: maggrp {
  585. fsl,pins = <
  586. MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
  587. >;
  588. };
  589. pinctrl_pcie: pciegrp {
  590. fsl,pins = <
  591. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
  592. >;
  593. };
  594. pinctrl_pmic: pmicgrp {
  595. fsl,pins = <
  596. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */
  597. >;
  598. };
  599. pinctrl_pps: ppsgrp {
  600. fsl,pins = <
  601. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  602. >;
  603. };
  604. pinctrl_pwm2: pwm2grp {
  605. fsl,pins = <
  606. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  607. >;
  608. };
  609. pinctrl_pwm3: pwm3grp {
  610. fsl,pins = <
  611. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  612. >;
  613. };
  614. pinctrl_pwm4: pwm4grp {
  615. fsl,pins = <
  616. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  617. >;
  618. };
  619. pinctrl_uart1: uart1grp {
  620. fsl,pins = <
  621. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  622. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  623. >;
  624. };
  625. pinctrl_uart2: uart2grp {
  626. fsl,pins = <
  627. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  628. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  629. >;
  630. };
  631. pinctrl_uart3: uart3grp {
  632. fsl,pins = <
  633. MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
  634. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  635. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  636. MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
  637. >;
  638. };
  639. pinctrl_uart4: uart4grp {
  640. fsl,pins = <
  641. MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
  642. MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
  643. MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
  644. MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
  645. >;
  646. };
  647. pinctrl_uart5: uart5grp {
  648. fsl,pins = <
  649. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  650. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  651. >;
  652. };
  653. pinctrl_usbotg: usbotggrp {
  654. fsl,pins = <
  655. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  656. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
  657. MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
  658. >;
  659. };
  660. pinctrl_usdhc3: usdhc3grp {
  661. fsl,pins = <
  662. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  663. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  664. MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059
  665. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  666. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  667. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  668. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  669. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  670. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  671. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  672. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  673. >;
  674. };
  675. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  676. fsl,pins = <
  677. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  678. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  679. MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9
  680. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  681. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  682. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  683. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  684. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
  685. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
  686. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
  687. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
  688. >;
  689. };
  690. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  691. fsl,pins = <
  692. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  693. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  694. MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9
  695. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  696. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  697. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  698. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  699. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
  700. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
  701. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
  702. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
  703. >;
  704. };
  705. pinctrl_wdog: wdoggrp {
  706. fsl,pins = <
  707. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  708. >;
  709. };
  710. };