imx6qdl-gw553x.dtsi 16 KB

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  1. /*
  2. * Copyright 2016 Gateworks Corporation
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public
  20. * License along with this file; if not, write to the Free
  21. * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22. * MA 02110-1301 USA
  23. *
  24. * Or, alternatively,
  25. *
  26. * b) Permission is hereby granted, free of charge, to any person
  27. * obtaining a copy of this software and associated documentation
  28. * files (the "Software"), to deal in the Software without
  29. * restriction, including without limitation the rights to use,
  30. * copy, modify, merge, publish, distribute, sublicense, and/or
  31. * sell copies of the Software, and to permit persons to whom the
  32. * Software is furnished to do so, subject to the following
  33. * conditions:
  34. *
  35. * The above copyright notice and this permission notice shall be
  36. * included in all copies or substantial portions of the Software.
  37. *
  38. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45. * OTHER DEALINGS IN THE SOFTWARE.
  46. */
  47. #include <dt-bindings/gpio/gpio.h>
  48. #include <dt-bindings/input/linux-event-codes.h>
  49. #include <dt-bindings/interrupt-controller/irq.h>
  50. / {
  51. /* these are used by bootloader for disabling nodes */
  52. aliases {
  53. led0 = &led0;
  54. led1 = &led1;
  55. nand = &gpmi;
  56. usb0 = &usbh1;
  57. usb1 = &usbotg;
  58. };
  59. chosen {
  60. stdout-path = &uart2;
  61. };
  62. gpio-keys {
  63. compatible = "gpio-keys";
  64. user-pb {
  65. label = "user_pb";
  66. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  67. linux,code = <BTN_0>;
  68. };
  69. user-pb1x {
  70. label = "user_pb1x";
  71. linux,code = <BTN_1>;
  72. interrupt-parent = <&gsc>;
  73. interrupts = <0>;
  74. };
  75. key-erased {
  76. label = "key-erased";
  77. linux,code = <BTN_2>;
  78. interrupt-parent = <&gsc>;
  79. interrupts = <1>;
  80. };
  81. eeprom-wp {
  82. label = "eeprom_wp";
  83. linux,code = <BTN_3>;
  84. interrupt-parent = <&gsc>;
  85. interrupts = <2>;
  86. };
  87. tamper {
  88. label = "tamper";
  89. linux,code = <BTN_4>;
  90. interrupt-parent = <&gsc>;
  91. interrupts = <5>;
  92. };
  93. switch-hold {
  94. label = "switch_hold";
  95. linux,code = <BTN_5>;
  96. interrupt-parent = <&gsc>;
  97. interrupts = <7>;
  98. };
  99. };
  100. leds {
  101. compatible = "gpio-leds";
  102. pinctrl-names = "default";
  103. pinctrl-0 = <&pinctrl_gpio_leds>;
  104. led0: user1 {
  105. label = "user1";
  106. gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  107. default-state = "on";
  108. linux,default-trigger = "heartbeat";
  109. };
  110. led1: user2 {
  111. label = "user2";
  112. gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  113. default-state = "off";
  114. };
  115. };
  116. memory@10000000 {
  117. device_type = "memory";
  118. reg = <0x10000000 0x20000000>;
  119. };
  120. pps {
  121. compatible = "pps-gpio";
  122. pinctrl-names = "default";
  123. pinctrl-0 = <&pinctrl_pps>;
  124. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  125. status = "okay";
  126. };
  127. reg_5p0v: regulator-5p0v {
  128. compatible = "regulator-fixed";
  129. regulator-name = "5P0V";
  130. regulator-min-microvolt = <5000000>;
  131. regulator-max-microvolt = <5000000>;
  132. regulator-always-on;
  133. };
  134. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  135. compatible = "regulator-fixed";
  136. regulator-name = "usb_otg_vbus";
  137. regulator-min-microvolt = <5000000>;
  138. regulator-max-microvolt = <5000000>;
  139. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  140. enable-active-high;
  141. };
  142. };
  143. &gpmi {
  144. pinctrl-names = "default";
  145. pinctrl-0 = <&pinctrl_gpmi_nand>;
  146. status = "okay";
  147. };
  148. &hdmi {
  149. pinctrl-names = "default";
  150. pinctrl-0 = <&pinctrl_hdmi>;
  151. ddc-i2c-bus = <&i2c3>;
  152. status = "okay";
  153. };
  154. &i2c1 {
  155. clock-frequency = <100000>;
  156. pinctrl-names = "default";
  157. pinctrl-0 = <&pinctrl_i2c1>;
  158. status = "okay";
  159. gsc: gsc@20 {
  160. compatible = "gw,gsc";
  161. reg = <0x20>;
  162. interrupt-parent = <&gpio1>;
  163. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  164. interrupt-controller;
  165. #interrupt-cells = <1>;
  166. #size-cells = <0>;
  167. adc {
  168. compatible = "gw,gsc-adc";
  169. #address-cells = <1>;
  170. #size-cells = <0>;
  171. channel@0 {
  172. gw,mode = <0>;
  173. reg = <0x00>;
  174. label = "temp";
  175. };
  176. channel@2 {
  177. gw,mode = <1>;
  178. reg = <0x02>;
  179. label = "vdd_vin";
  180. };
  181. channel@5 {
  182. gw,mode = <1>;
  183. reg = <0x05>;
  184. label = "vdd_3p3";
  185. };
  186. channel@8 {
  187. gw,mode = <1>;
  188. reg = <0x08>;
  189. label = "vdd_bat";
  190. };
  191. channel@b {
  192. gw,mode = <1>;
  193. reg = <0x0b>;
  194. label = "vdd_5p0";
  195. };
  196. channel@e {
  197. gw,mode = <1>;
  198. reg = <0xe>;
  199. label = "vdd_arm";
  200. };
  201. channel@11 {
  202. gw,mode = <1>;
  203. reg = <0x11>;
  204. label = "vdd_soc";
  205. };
  206. channel@14 {
  207. gw,mode = <1>;
  208. reg = <0x14>;
  209. label = "vdd_3p0";
  210. };
  211. channel@17 {
  212. gw,mode = <1>;
  213. reg = <0x17>;
  214. label = "vdd_1p5";
  215. };
  216. channel@1d {
  217. gw,mode = <1>;
  218. reg = <0x1d>;
  219. label = "vdd_1p8a";
  220. };
  221. channel@20 {
  222. gw,mode = <1>;
  223. reg = <0x20>;
  224. label = "vdd_1p0b";
  225. };
  226. channel@26 {
  227. gw,mode = <1>;
  228. reg = <0x26>;
  229. label = "vdd_an1";
  230. };
  231. };
  232. };
  233. gsc_gpio: gpio@23 {
  234. compatible = "nxp,pca9555";
  235. reg = <0x23>;
  236. gpio-controller;
  237. #gpio-cells = <2>;
  238. interrupt-parent = <&gsc>;
  239. interrupts = <4>;
  240. };
  241. eeprom1: eeprom@50 {
  242. compatible = "atmel,24c02";
  243. reg = <0x50>;
  244. pagesize = <16>;
  245. };
  246. eeprom2: eeprom@51 {
  247. compatible = "atmel,24c02";
  248. reg = <0x51>;
  249. pagesize = <16>;
  250. };
  251. eeprom3: eeprom@52 {
  252. compatible = "atmel,24c02";
  253. reg = <0x52>;
  254. pagesize = <16>;
  255. };
  256. eeprom4: eeprom@53 {
  257. compatible = "atmel,24c02";
  258. reg = <0x53>;
  259. pagesize = <16>;
  260. };
  261. rtc: ds1672@68 {
  262. compatible = "dallas,ds1672";
  263. reg = <0x68>;
  264. };
  265. };
  266. &i2c2 {
  267. clock-frequency = <100000>;
  268. pinctrl-names = "default";
  269. pinctrl-0 = <&pinctrl_i2c2>;
  270. status = "okay";
  271. magn@1c {
  272. compatible = "st,lsm9ds1-magn";
  273. reg = <0x1c>;
  274. pinctrl-names = "default";
  275. pinctrl-0 = <&pinctrl_mag>;
  276. interrupt-parent = <&gpio1>;
  277. interrupts = <2 IRQ_TYPE_EDGE_RISING>;
  278. };
  279. imu@6a {
  280. compatible = "st,lsm9ds1-imu";
  281. reg = <0x6a>;
  282. st,drdy-int-pin = <1>;
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&pinctrl_imu>;
  285. interrupt-parent = <&gpio7>;
  286. interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
  287. };
  288. ltc3676: pmic@3c {
  289. compatible = "lltc,ltc3676";
  290. reg = <0x3c>;
  291. pinctrl-names = "default";
  292. pinctrl-0 = <&pinctrl_pmic>;
  293. interrupt-parent = <&gpio1>;
  294. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  295. regulators {
  296. /* VDD_SOC (1+R1/R2 = 1.635) */
  297. reg_vdd_soc: sw1 {
  298. regulator-name = "vddsoc";
  299. regulator-min-microvolt = <674400>;
  300. regulator-max-microvolt = <1308000>;
  301. lltc,fb-voltage-divider = <127000 200000>;
  302. regulator-ramp-delay = <7000>;
  303. regulator-boot-on;
  304. regulator-always-on;
  305. };
  306. /* VDD_DDR (1+R1/R2 = 2.105) */
  307. reg_vdd_ddr: sw2 {
  308. regulator-name = "vddddr";
  309. regulator-min-microvolt = <868310>;
  310. regulator-max-microvolt = <1684000>;
  311. lltc,fb-voltage-divider = <221000 200000>;
  312. regulator-ramp-delay = <7000>;
  313. regulator-boot-on;
  314. regulator-always-on;
  315. };
  316. /* VDD_ARM (1+R1/R2 = 1.635) */
  317. reg_vdd_arm: sw3 {
  318. regulator-name = "vddarm";
  319. regulator-min-microvolt = <674400>;
  320. regulator-max-microvolt = <1308000>;
  321. lltc,fb-voltage-divider = <127000 200000>;
  322. regulator-ramp-delay = <7000>;
  323. regulator-boot-on;
  324. regulator-always-on;
  325. };
  326. /* VDD_3P3 (1+R1/R2 = 1.281) */
  327. reg_3p3v: sw4 {
  328. regulator-name = "vdd3p3";
  329. regulator-min-microvolt = <1880000>;
  330. regulator-max-microvolt = <3647000>;
  331. lltc,fb-voltage-divider = <200000 56200>;
  332. regulator-ramp-delay = <7000>;
  333. regulator-boot-on;
  334. regulator-always-on;
  335. };
  336. /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */
  337. reg_1p8a: ldo2 {
  338. regulator-name = "vdd1p8a";
  339. regulator-min-microvolt = <1816125>;
  340. regulator-max-microvolt = <1816125>;
  341. lltc,fb-voltage-divider = <301000 200000>;
  342. regulator-boot-on;
  343. regulator-always-on;
  344. };
  345. /* VDD_1P8b: microSD VDD_1P8 */
  346. reg_1p8b: ldo3 {
  347. regulator-name = "vdd1p8b";
  348. regulator-min-microvolt = <1800000>;
  349. regulator-max-microvolt = <1800000>;
  350. regulator-boot-on;
  351. };
  352. /* VDD_HIGH (1+R1/R2 = 4.17) */
  353. reg_3p0v: ldo4 {
  354. regulator-name = "vdd3p0";
  355. regulator-min-microvolt = <3023250>;
  356. regulator-max-microvolt = <3023250>;
  357. lltc,fb-voltage-divider = <634000 200000>;
  358. regulator-boot-on;
  359. regulator-always-on;
  360. };
  361. };
  362. };
  363. };
  364. &i2c3 {
  365. clock-frequency = <100000>;
  366. pinctrl-names = "default";
  367. pinctrl-0 = <&pinctrl_i2c3>;
  368. status = "okay";
  369. adv7180: camera@20 {
  370. compatible = "adi,adv7180";
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&pinctrl_adv7180>;
  373. reg = <0x20>;
  374. powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
  375. interrupt-parent = <&gpio5>;
  376. interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
  377. port {
  378. adv7180_to_ipu1_csi0_mux: endpoint {
  379. remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  380. bus-width = <8>;
  381. };
  382. };
  383. };
  384. };
  385. &ipu1_csi0_from_ipu1_csi0_mux {
  386. bus-width = <8>;
  387. };
  388. &ipu1_csi0_mux_from_parallel_sensor {
  389. remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
  390. bus-width = <8>;
  391. };
  392. &ipu1_csi0 {
  393. pinctrl-names = "default";
  394. pinctrl-0 = <&pinctrl_ipu1_csi0>;
  395. };
  396. &pcie {
  397. pinctrl-names = "default";
  398. pinctrl-0 = <&pinctrl_pcie>;
  399. reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
  400. status = "okay";
  401. };
  402. &pwm2 {
  403. pinctrl-names = "default";
  404. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  405. status = "disabled";
  406. };
  407. &pwm3 {
  408. pinctrl-names = "default";
  409. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  410. status = "disabled";
  411. };
  412. &pwm4 {
  413. pinctrl-names = "default";
  414. pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
  415. status = "disabled";
  416. };
  417. &uart2 {
  418. pinctrl-names = "default";
  419. pinctrl-0 = <&pinctrl_uart2>;
  420. status = "okay";
  421. };
  422. &uart3 {
  423. pinctrl-names = "default";
  424. pinctrl-0 = <&pinctrl_uart3>;
  425. status = "okay";
  426. };
  427. &uart4 {
  428. pinctrl-names = "default";
  429. pinctrl-0 = <&pinctrl_uart4>;
  430. status = "okay";
  431. };
  432. &uart5 {
  433. pinctrl-names = "default";
  434. pinctrl-0 = <&pinctrl_uart5>;
  435. status = "okay";
  436. };
  437. &usbh1 {
  438. status = "okay";
  439. };
  440. &usbotg {
  441. vbus-supply = <&reg_usb_otg_vbus>;
  442. pinctrl-names = "default";
  443. pinctrl-0 = <&pinctrl_usbotg>;
  444. disable-over-current;
  445. dr_mode = "otg";
  446. status = "okay";
  447. };
  448. &usdhc3 {
  449. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  450. pinctrl-0 = <&pinctrl_usdhc3>;
  451. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  452. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  453. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  454. status = "okay";
  455. };
  456. &wdog1 {
  457. pinctrl-names = "default";
  458. pinctrl-0 = <&pinctrl_wdog>;
  459. fsl,ext-reset-output;
  460. };
  461. &iomuxc {
  462. pinctrl_adv7180: adv7180grp {
  463. fsl,pins = <
  464. MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
  465. MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
  466. >;
  467. };
  468. pinctrl_gpmi_nand: gpminandgrp {
  469. fsl,pins = <
  470. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  471. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  472. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  473. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  474. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  475. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  476. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  477. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  478. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  479. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  480. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  481. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  482. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  483. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  484. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  485. >;
  486. };
  487. pinctrl_hdmi: hdmigrp {
  488. fsl,pins = <
  489. MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
  490. >;
  491. };
  492. pinctrl_i2c1: i2c1grp {
  493. fsl,pins = <
  494. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  495. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  496. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  497. >;
  498. };
  499. pinctrl_i2c2: i2c2grp {
  500. fsl,pins = <
  501. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  502. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  503. >;
  504. };
  505. pinctrl_i2c3: i2c3grp {
  506. fsl,pins = <
  507. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  508. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  509. >;
  510. };
  511. pinctrl_imu: imugrp {
  512. fsl,pins = <
  513. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
  514. >;
  515. };
  516. pinctrl_ipu1_csi0: ipu1csi0grp {
  517. fsl,pins = <
  518. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
  519. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
  520. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
  521. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
  522. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
  523. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
  524. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
  525. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
  526. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
  527. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
  528. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
  529. >;
  530. };
  531. pinctrl_gpio_leds: gpioledsgrp {
  532. fsl,pins = <
  533. MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
  534. MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
  535. >;
  536. };
  537. pinctrl_mag: maggrp {
  538. fsl,pins = <
  539. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  540. >;
  541. };
  542. pinctrl_pcie: pciegrp {
  543. fsl,pins = <
  544. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
  545. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
  546. >;
  547. };
  548. pinctrl_pmic: pmicgrp {
  549. fsl,pins = <
  550. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  551. >;
  552. };
  553. pinctrl_pps: ppsgrp {
  554. fsl,pins = <
  555. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  556. >;
  557. };
  558. pinctrl_pwm2: pwm2grp {
  559. fsl,pins = <
  560. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  561. >;
  562. };
  563. pinctrl_pwm3: pwm3grp {
  564. fsl,pins = <
  565. MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  566. >;
  567. };
  568. pinctrl_pwm4: pwm4grp {
  569. fsl,pins = <
  570. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  571. >;
  572. };
  573. pinctrl_uart2: uart2grp {
  574. fsl,pins = <
  575. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  576. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  577. >;
  578. };
  579. pinctrl_uart3: uart3grp {
  580. fsl,pins = <
  581. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  582. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  583. >;
  584. };
  585. pinctrl_uart4: uart4grp {
  586. fsl,pins = <
  587. MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  588. MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  589. >;
  590. };
  591. pinctrl_uart5: uart5grp {
  592. fsl,pins = <
  593. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  594. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  595. >;
  596. };
  597. pinctrl_usbotg: usbotggrp {
  598. fsl,pins = <
  599. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  600. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
  601. >;
  602. };
  603. pinctrl_usdhc3: usdhc3grp {
  604. fsl,pins = <
  605. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  606. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  607. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  608. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  609. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  610. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  611. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  612. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  613. >;
  614. };
  615. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  616. fsl,pins = <
  617. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  618. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  619. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  620. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  621. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  622. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  623. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  624. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  625. >;
  626. };
  627. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  628. fsl,pins = <
  629. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  630. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  631. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  632. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  633. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  634. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  635. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  636. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  637. >;
  638. };
  639. pinctrl_wdog: wdoggrp {
  640. fsl,pins = <
  641. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  642. >;
  643. };
  644. };