imx6qdl-gw552x.dtsi 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2014 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. led2 = &led2;
  14. nand = &gpmi;
  15. usb0 = &usbh1;
  16. usb1 = &usbotg;
  17. };
  18. chosen {
  19. bootargs = "console=ttymxc1,115200";
  20. };
  21. gpio-keys {
  22. compatible = "gpio-keys";
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. user-pb {
  26. label = "user_pb";
  27. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  28. linux,code = <BTN_0>;
  29. };
  30. user-pb1x {
  31. label = "user_pb1x";
  32. linux,code = <BTN_1>;
  33. interrupt-parent = <&gsc>;
  34. interrupts = <0>;
  35. };
  36. key-erased {
  37. label = "key-erased";
  38. linux,code = <BTN_2>;
  39. interrupt-parent = <&gsc>;
  40. interrupts = <1>;
  41. };
  42. eeprom-wp {
  43. label = "eeprom_wp";
  44. linux,code = <BTN_3>;
  45. interrupt-parent = <&gsc>;
  46. interrupts = <2>;
  47. };
  48. tamper {
  49. label = "tamper";
  50. linux,code = <BTN_4>;
  51. interrupt-parent = <&gsc>;
  52. interrupts = <5>;
  53. };
  54. switch-hold {
  55. label = "switch_hold";
  56. linux,code = <BTN_5>;
  57. interrupt-parent = <&gsc>;
  58. interrupts = <7>;
  59. };
  60. };
  61. leds {
  62. compatible = "gpio-leds";
  63. pinctrl-names = "default";
  64. pinctrl-0 = <&pinctrl_gpio_leds>;
  65. led0: user1 {
  66. label = "user1";
  67. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  68. default-state = "on";
  69. linux,default-trigger = "heartbeat";
  70. };
  71. led1: user2 {
  72. label = "user2";
  73. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  74. default-state = "off";
  75. };
  76. led2: user3 {
  77. label = "user3";
  78. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  79. default-state = "off";
  80. };
  81. };
  82. memory@10000000 {
  83. device_type = "memory";
  84. reg = <0x10000000 0x20000000>;
  85. };
  86. reg_1p0v: regulator-1p0v {
  87. compatible = "regulator-fixed";
  88. regulator-name = "1P0V";
  89. regulator-min-microvolt = <1000000>;
  90. regulator-max-microvolt = <1000000>;
  91. regulator-always-on;
  92. };
  93. reg_3p3v: regulator-3p3v {
  94. compatible = "regulator-fixed";
  95. regulator-name = "3P3V";
  96. regulator-min-microvolt = <3300000>;
  97. regulator-max-microvolt = <3300000>;
  98. regulator-always-on;
  99. };
  100. reg_5p0v: regulator-5p0v {
  101. compatible = "regulator-fixed";
  102. regulator-name = "5P0V";
  103. regulator-min-microvolt = <5000000>;
  104. regulator-max-microvolt = <5000000>;
  105. regulator-always-on;
  106. };
  107. };
  108. &gpmi {
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_gpmi_nand>;
  111. status = "okay";
  112. };
  113. &hdmi {
  114. ddc-i2c-bus = <&i2c3>;
  115. status = "okay";
  116. };
  117. &i2c1 {
  118. clock-frequency = <100000>;
  119. pinctrl-names = "default";
  120. pinctrl-0 = <&pinctrl_i2c1>;
  121. status = "okay";
  122. gsc: gsc@20 {
  123. compatible = "gw,gsc";
  124. reg = <0x20>;
  125. interrupt-parent = <&gpio1>;
  126. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  127. interrupt-controller;
  128. #interrupt-cells = <1>;
  129. #size-cells = <0>;
  130. adc {
  131. compatible = "gw,gsc-adc";
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. channel@0 {
  135. gw,mode = <0>;
  136. reg = <0x00>;
  137. label = "temp";
  138. };
  139. channel@2 {
  140. gw,mode = <1>;
  141. reg = <0x02>;
  142. label = "vdd_vin";
  143. };
  144. channel@5 {
  145. gw,mode = <1>;
  146. reg = <0x05>;
  147. label = "vdd_3p3";
  148. };
  149. channel@8 {
  150. gw,mode = <1>;
  151. reg = <0x08>;
  152. label = "vdd_bat";
  153. };
  154. channel@b {
  155. gw,mode = <1>;
  156. reg = <0x0b>;
  157. label = "vdd_5p0";
  158. };
  159. channel@e {
  160. gw,mode = <1>;
  161. reg = <0xe>;
  162. label = "vdd_arm";
  163. };
  164. channel@11 {
  165. gw,mode = <1>;
  166. reg = <0x11>;
  167. label = "vdd_soc";
  168. };
  169. channel@14 {
  170. gw,mode = <1>;
  171. reg = <0x14>;
  172. label = "vdd_3p0";
  173. };
  174. channel@17 {
  175. gw,mode = <1>;
  176. reg = <0x17>;
  177. label = "vdd_1p5";
  178. };
  179. channel@1d {
  180. gw,mode = <1>;
  181. reg = <0x1d>;
  182. label = "vdd_1p8";
  183. };
  184. channel@20 {
  185. gw,mode = <1>;
  186. reg = <0x20>;
  187. label = "vdd_1p0";
  188. };
  189. channel@23 {
  190. gw,mode = <1>;
  191. reg = <0x23>;
  192. label = "vdd_2p5";
  193. };
  194. };
  195. };
  196. gsc_gpio: gpio@23 {
  197. compatible = "nxp,pca9555";
  198. reg = <0x23>;
  199. gpio-controller;
  200. #gpio-cells = <2>;
  201. interrupt-parent = <&gsc>;
  202. interrupts = <4>;
  203. };
  204. eeprom1: eeprom@50 {
  205. compatible = "atmel,24c02";
  206. reg = <0x50>;
  207. pagesize = <16>;
  208. };
  209. eeprom2: eeprom@51 {
  210. compatible = "atmel,24c02";
  211. reg = <0x51>;
  212. pagesize = <16>;
  213. };
  214. eeprom3: eeprom@52 {
  215. compatible = "atmel,24c02";
  216. reg = <0x52>;
  217. pagesize = <16>;
  218. };
  219. eeprom4: eeprom@53 {
  220. compatible = "atmel,24c02";
  221. reg = <0x53>;
  222. pagesize = <16>;
  223. };
  224. rtc: ds1672@68 {
  225. compatible = "dallas,ds1672";
  226. reg = <0x68>;
  227. };
  228. };
  229. &i2c2 {
  230. clock-frequency = <100000>;
  231. pinctrl-names = "default";
  232. pinctrl-0 = <&pinctrl_i2c2>;
  233. status = "okay";
  234. ltc3676: pmic@3c {
  235. compatible = "lltc,ltc3676";
  236. reg = <0x3c>;
  237. pinctrl-names = "default";
  238. pinctrl-0 = <&pinctrl_pmic>;
  239. interrupt-parent = <&gpio1>;
  240. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  241. regulators {
  242. /* VDD_SOC (1+R1/R2 = 1.635) */
  243. reg_vdd_soc: sw1 {
  244. regulator-name = "vddsoc";
  245. regulator-min-microvolt = <674400>;
  246. regulator-max-microvolt = <1308000>;
  247. lltc,fb-voltage-divider = <127000 200000>;
  248. regulator-ramp-delay = <7000>;
  249. regulator-boot-on;
  250. regulator-always-on;
  251. };
  252. /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */
  253. reg_1p8v: sw2 {
  254. regulator-name = "vdd1p8";
  255. regulator-min-microvolt = <1033310>;
  256. regulator-max-microvolt = <2004000>;
  257. lltc,fb-voltage-divider = <301000 200000>;
  258. regulator-ramp-delay = <7000>;
  259. regulator-boot-on;
  260. regulator-always-on;
  261. };
  262. /* VDD_ARM (1+R1/R2 = 1.635) */
  263. reg_vdd_arm: sw3 {
  264. regulator-name = "vddarm";
  265. regulator-min-microvolt = <674400>;
  266. regulator-max-microvolt = <1308000>;
  267. lltc,fb-voltage-divider = <127000 200000>;
  268. regulator-ramp-delay = <7000>;
  269. regulator-boot-on;
  270. regulator-always-on;
  271. };
  272. /* VDD_DDR (1+R1/R2 = 2.105) */
  273. reg_vdd_ddr: sw4 {
  274. regulator-name = "vddddr";
  275. regulator-min-microvolt = <868310>;
  276. regulator-max-microvolt = <1684000>;
  277. lltc,fb-voltage-divider = <221000 200000>;
  278. regulator-ramp-delay = <7000>;
  279. regulator-boot-on;
  280. regulator-always-on;
  281. };
  282. /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
  283. reg_2p5v: ldo2 {
  284. regulator-name = "vdd2p5";
  285. regulator-min-microvolt = <2490375>;
  286. regulator-max-microvolt = <2490375>;
  287. lltc,fb-voltage-divider = <487000 200000>;
  288. regulator-boot-on;
  289. regulator-always-on;
  290. };
  291. /* VDD_HIGH (1+R1/R2 = 4.17) */
  292. reg_3p0v: ldo4 {
  293. regulator-name = "vdd3p0";
  294. regulator-min-microvolt = <3023250>;
  295. regulator-max-microvolt = <3023250>;
  296. lltc,fb-voltage-divider = <634000 200000>;
  297. regulator-boot-on;
  298. regulator-always-on;
  299. };
  300. };
  301. };
  302. };
  303. &i2c3 {
  304. clock-frequency = <100000>;
  305. pinctrl-names = "default";
  306. pinctrl-0 = <&pinctrl_i2c3>;
  307. status = "okay";
  308. };
  309. &pcie {
  310. pinctrl-names = "default";
  311. pinctrl-0 = <&pinctrl_pcie>;
  312. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  313. status = "okay";
  314. };
  315. &pwm2 {
  316. pinctrl-names = "default";
  317. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  318. status = "disabled";
  319. };
  320. &pwm3 {
  321. pinctrl-names = "default";
  322. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  323. status = "disabled";
  324. };
  325. &uart2 {
  326. pinctrl-names = "default";
  327. pinctrl-0 = <&pinctrl_uart2>;
  328. status = "okay";
  329. };
  330. &uart3 {
  331. pinctrl-names = "default";
  332. pinctrl-0 = <&pinctrl_uart3>;
  333. status = "okay";
  334. };
  335. &uart5 {
  336. pinctrl-names = "default";
  337. pinctrl-0 = <&pinctrl_uart5>;
  338. status = "okay"; };
  339. &usbh1 {
  340. status = "okay";
  341. };
  342. &usbotg {
  343. vbus-supply = <&reg_5p0v>;
  344. pinctrl-names = "default";
  345. pinctrl-0 = <&pinctrl_usbotg>;
  346. disable-over-current;
  347. dr_mode = "otg";
  348. status = "okay";
  349. };
  350. &wdog1 {
  351. pinctrl-names = "default";
  352. pinctrl-0 = <&pinctrl_wdog>;
  353. fsl,ext-reset-output;
  354. };
  355. &iomuxc {
  356. pinctrl_gpio_leds: gpioledsgrp {
  357. fsl,pins = <
  358. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  359. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  360. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  361. >;
  362. };
  363. pinctrl_gpmi_nand: gpminandgrp {
  364. fsl,pins = <
  365. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  366. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  367. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  368. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  369. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  370. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  371. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  372. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  373. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  374. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  375. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  376. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  377. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  378. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  379. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  380. >;
  381. };
  382. pinctrl_i2c1: i2c1grp {
  383. fsl,pins = <
  384. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  385. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  386. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  387. >;
  388. };
  389. pinctrl_i2c2: i2c2grp {
  390. fsl,pins = <
  391. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  392. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  393. >;
  394. };
  395. pinctrl_i2c3: i2c3grp {
  396. fsl,pins = <
  397. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  398. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  399. >;
  400. };
  401. pinctrl_pcie: pciegrp {
  402. fsl,pins = <
  403. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
  404. >;
  405. };
  406. pinctrl_pmic: pmicgrp {
  407. fsl,pins = <
  408. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  409. >;
  410. };
  411. pinctrl_pwm2: pwm2grp {
  412. fsl,pins = <
  413. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  414. >;
  415. };
  416. pinctrl_pwm3: pwm3grp {
  417. fsl,pins = <
  418. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  419. >;
  420. };
  421. pinctrl_uart2: uart2grp {
  422. fsl,pins = <
  423. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  424. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  425. >;
  426. };
  427. pinctrl_uart3: uart3grp {
  428. fsl,pins = <
  429. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  430. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  431. >;
  432. };
  433. pinctrl_uart5: uart5grp {
  434. fsl,pins = <
  435. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  436. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  437. >;
  438. };
  439. pinctrl_usbotg: usbotggrp {
  440. fsl,pins = <
  441. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059
  442. >;
  443. };
  444. pinctrl_wdog: wdoggrp {
  445. fsl,pins = <
  446. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  447. >;
  448. };
  449. };