imx6qdl-gw551x.dtsi 16 KB

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  1. /*
  2. * Copyright 2014 Gateworks Corporation
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public
  20. * License along with this file; if not, write to the Free
  21. * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22. * MA 02110-1301 USA
  23. *
  24. * Or, alternatively,
  25. *
  26. * b) Permission is hereby granted, free of charge, to any person
  27. * obtaining a copy of this software and associated documentation
  28. * files (the "Software"), to deal in the Software without
  29. * restriction, including without limitation the rights to use,
  30. * copy, modify, merge, publish, distribute, sublicense, and/or
  31. * sell copies of the Software, and to permit persons to whom the
  32. * Software is furnished to do so, subject to the following
  33. * conditions:
  34. *
  35. * The above copyright notice and this permission notice shall be
  36. * included in all copies or substantial portions of the Software.
  37. *
  38. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45. * OTHER DEALINGS IN THE SOFTWARE.
  46. */
  47. #include <dt-bindings/gpio/gpio.h>
  48. #include <dt-bindings/media/tda1997x.h>
  49. #include <dt-bindings/input/linux-event-codes.h>
  50. #include <dt-bindings/interrupt-controller/irq.h>
  51. #include <dt-bindings/sound/fsl-imx-audmux.h>
  52. / {
  53. /* these are used by bootloader for disabling nodes */
  54. aliases {
  55. led0 = &led0;
  56. nand = &gpmi;
  57. ssi0 = &ssi1;
  58. usb0 = &usbh1;
  59. usb1 = &usbotg;
  60. };
  61. chosen {
  62. bootargs = "console=ttymxc1,115200";
  63. };
  64. gpio-keys {
  65. compatible = "gpio-keys";
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. user-pb {
  69. label = "user_pb";
  70. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  71. linux,code = <BTN_0>;
  72. };
  73. user-pb1x {
  74. label = "user_pb1x";
  75. linux,code = <BTN_1>;
  76. interrupt-parent = <&gsc>;
  77. interrupts = <0>;
  78. };
  79. key-erased {
  80. label = "key-erased";
  81. linux,code = <BTN_2>;
  82. interrupt-parent = <&gsc>;
  83. interrupts = <1>;
  84. };
  85. eeprom-wp {
  86. label = "eeprom_wp";
  87. linux,code = <BTN_3>;
  88. interrupt-parent = <&gsc>;
  89. interrupts = <2>;
  90. };
  91. tamper {
  92. label = "tamper";
  93. linux,code = <BTN_4>;
  94. interrupt-parent = <&gsc>;
  95. interrupts = <5>;
  96. };
  97. switch-hold {
  98. label = "switch_hold";
  99. linux,code = <BTN_5>;
  100. interrupt-parent = <&gsc>;
  101. interrupts = <7>;
  102. };
  103. };
  104. leds {
  105. compatible = "gpio-leds";
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&pinctrl_gpio_leds>;
  108. led0: user1 {
  109. label = "user1";
  110. gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
  111. default-state = "on";
  112. linux,default-trigger = "heartbeat";
  113. };
  114. };
  115. memory@10000000 {
  116. device_type = "memory";
  117. reg = <0x10000000 0x20000000>;
  118. };
  119. reg_5p0v: regulator-5p0v {
  120. compatible = "regulator-fixed";
  121. regulator-name = "5P0V";
  122. regulator-min-microvolt = <5000000>;
  123. regulator-max-microvolt = <5000000>;
  124. };
  125. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  126. compatible = "regulator-fixed";
  127. regulator-name = "usb_h1_vbus";
  128. regulator-min-microvolt = <5000000>;
  129. regulator-max-microvolt = <5000000>;
  130. };
  131. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  132. compatible = "regulator-fixed";
  133. regulator-name = "usb_otg_vbus";
  134. regulator-min-microvolt = <5000000>;
  135. regulator-max-microvolt = <5000000>;
  136. };
  137. sound-digital {
  138. compatible = "simple-audio-card";
  139. simple-audio-card,name = "tda1997x-audio";
  140. simple-audio-card,format = "i2s";
  141. simple-audio-card,bitclock-master = <&sound_codec>;
  142. simple-audio-card,frame-master = <&sound_codec>;
  143. sound_cpu: simple-audio-card,cpu {
  144. sound-dai = <&ssi1>;
  145. };
  146. sound_codec: simple-audio-card,codec {
  147. sound-dai = <&hdmi_receiver>;
  148. };
  149. };
  150. };
  151. &audmux {
  152. pinctrl-names = "default";
  153. pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */
  154. status = "okay";
  155. ssi1 {
  156. fsl,audmux-port = <0>;
  157. fsl,port-config = <
  158. (IMX_AUDMUX_V2_PTCR_TFSDIR |
  159. IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
  160. IMX_AUDMUX_V2_PTCR_TCLKDIR |
  161. IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
  162. IMX_AUDMUX_V2_PTCR_SYN)
  163. IMX_AUDMUX_V2_PDCR_RXDSEL(4)
  164. >;
  165. };
  166. aud5 {
  167. fsl,audmux-port = <4>;
  168. fsl,port-config = <
  169. IMX_AUDMUX_V2_PTCR_SYN
  170. IMX_AUDMUX_V2_PDCR_RXDSEL(0)>;
  171. };
  172. };
  173. &can1 {
  174. pinctrl-names = "default";
  175. pinctrl-0 = <&pinctrl_flexcan1>;
  176. status = "okay";
  177. };
  178. &gpmi {
  179. pinctrl-names = "default";
  180. pinctrl-0 = <&pinctrl_gpmi_nand>;
  181. status = "okay";
  182. };
  183. &hdmi {
  184. ddc-i2c-bus = <&i2c3>;
  185. status = "okay";
  186. };
  187. &i2c1 {
  188. clock-frequency = <100000>;
  189. pinctrl-names = "default";
  190. pinctrl-0 = <&pinctrl_i2c1>;
  191. status = "okay";
  192. gsc: gsc@20 {
  193. compatible = "gw,gsc";
  194. reg = <0x20>;
  195. interrupt-parent = <&gpio1>;
  196. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  197. interrupt-controller;
  198. #interrupt-cells = <1>;
  199. #size-cells = <0>;
  200. adc {
  201. compatible = "gw,gsc-adc";
  202. #address-cells = <1>;
  203. #size-cells = <0>;
  204. channel@0 {
  205. gw,mode = <0>;
  206. reg = <0x00>;
  207. label = "temp";
  208. };
  209. channel@2 {
  210. gw,mode = <1>;
  211. reg = <0x02>;
  212. label = "vdd_vin";
  213. };
  214. channel@5 {
  215. gw,mode = <1>;
  216. reg = <0x05>;
  217. label = "vdd_3p3";
  218. };
  219. channel@8 {
  220. gw,mode = <1>;
  221. reg = <0x08>;
  222. label = "vdd_bat";
  223. };
  224. channel@b {
  225. gw,mode = <1>;
  226. reg = <0x0b>;
  227. label = "vdd_5p0";
  228. };
  229. channel@e {
  230. gw,mode = <1>;
  231. reg = <0xe>;
  232. label = "vdd_arm";
  233. };
  234. channel@11 {
  235. gw,mode = <1>;
  236. reg = <0x11>;
  237. label = "vdd_soc";
  238. };
  239. channel@14 {
  240. gw,mode = <1>;
  241. reg = <0x14>;
  242. label = "vdd_3p0";
  243. };
  244. channel@17 {
  245. gw,mode = <1>;
  246. reg = <0x17>;
  247. label = "vdd_1p5";
  248. };
  249. channel@1d {
  250. gw,mode = <1>;
  251. reg = <0x1d>;
  252. label = "vdd_1p8a";
  253. };
  254. channel@20 {
  255. gw,mode = <1>;
  256. reg = <0x20>;
  257. label = "vdd_1p0b";
  258. };
  259. };
  260. };
  261. gsc_gpio: gpio@23 {
  262. compatible = "nxp,pca9555";
  263. reg = <0x23>;
  264. gpio-controller;
  265. #gpio-cells = <2>;
  266. interrupt-parent = <&gsc>;
  267. interrupts = <4>;
  268. };
  269. eeprom1: eeprom@50 {
  270. compatible = "atmel,24c02";
  271. reg = <0x50>;
  272. pagesize = <16>;
  273. };
  274. eeprom2: eeprom@51 {
  275. compatible = "atmel,24c02";
  276. reg = <0x51>;
  277. pagesize = <16>;
  278. };
  279. eeprom3: eeprom@52 {
  280. compatible = "atmel,24c02";
  281. reg = <0x52>;
  282. pagesize = <16>;
  283. };
  284. eeprom4: eeprom@53 {
  285. compatible = "atmel,24c02";
  286. reg = <0x53>;
  287. pagesize = <16>;
  288. };
  289. rtc: ds1672@68 {
  290. compatible = "dallas,ds1672";
  291. reg = <0x68>;
  292. };
  293. };
  294. &i2c2 {
  295. clock-frequency = <100000>;
  296. pinctrl-names = "default";
  297. pinctrl-0 = <&pinctrl_i2c2>;
  298. status = "okay";
  299. ltc3676: pmic@3c {
  300. compatible = "lltc,ltc3676";
  301. reg = <0x3c>;
  302. pinctrl-names = "default";
  303. pinctrl-0 = <&pinctrl_pmic>;
  304. interrupt-parent = <&gpio1>;
  305. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  306. regulators {
  307. /* VDD_SOC (1+R1/R2 = 1.635) */
  308. reg_vdd_soc: sw1 {
  309. regulator-name = "vddsoc";
  310. regulator-min-microvolt = <674400>;
  311. regulator-max-microvolt = <1308000>;
  312. lltc,fb-voltage-divider = <127000 200000>;
  313. regulator-ramp-delay = <7000>;
  314. regulator-boot-on;
  315. regulator-always-on;
  316. };
  317. /* VDD_DDR (1+R1/R2 = 2.105) */
  318. reg_vdd_ddr: sw2 {
  319. regulator-name = "vddddr";
  320. regulator-min-microvolt = <868310>;
  321. regulator-max-microvolt = <1684000>;
  322. lltc,fb-voltage-divider = <221000 200000>;
  323. regulator-ramp-delay = <7000>;
  324. regulator-boot-on;
  325. regulator-always-on;
  326. };
  327. /* VDD_ARM (1+R1/R2 = 1.635) */
  328. reg_vdd_arm: sw3 {
  329. regulator-name = "vddarm";
  330. regulator-min-microvolt = <674400>;
  331. regulator-max-microvolt = <1308000>;
  332. lltc,fb-voltage-divider = <127000 200000>;
  333. regulator-ramp-delay = <7000>;
  334. regulator-boot-on;
  335. regulator-always-on;
  336. };
  337. /* VDD_3P3 (1+R1/R2 = 1.281) */
  338. reg_3p3: sw4 {
  339. regulator-name = "vdd3p3";
  340. regulator-min-microvolt = <1880000>;
  341. regulator-max-microvolt = <3647000>;
  342. lltc,fb-voltage-divider = <200000 56200>;
  343. regulator-ramp-delay = <7000>;
  344. regulator-boot-on;
  345. regulator-always-on;
  346. };
  347. /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */
  348. reg_1p8a: ldo2 {
  349. regulator-name = "vdd1p8a";
  350. regulator-min-microvolt = <1816125>;
  351. regulator-max-microvolt = <1816125>;
  352. lltc,fb-voltage-divider = <301000 200000>;
  353. regulator-boot-on;
  354. regulator-always-on;
  355. };
  356. /* VDD_1P8b: HDMI In analog */
  357. reg_1p8b: ldo3 {
  358. regulator-name = "vdd1p8b";
  359. regulator-min-microvolt = <1800000>;
  360. regulator-max-microvolt = <1800000>;
  361. regulator-boot-on;
  362. };
  363. /* VDD_HIGH (1+R1/R2 = 4.17) */
  364. reg_3p0: ldo4 {
  365. regulator-name = "vdd3p0";
  366. regulator-min-microvolt = <3023250>;
  367. regulator-max-microvolt = <3023250>;
  368. lltc,fb-voltage-divider = <634000 200000>;
  369. regulator-boot-on;
  370. regulator-always-on;
  371. };
  372. };
  373. };
  374. };
  375. &i2c3 {
  376. clock-frequency = <100000>;
  377. pinctrl-names = "default";
  378. pinctrl-0 = <&pinctrl_i2c3>;
  379. status = "okay";
  380. gpio_exp: pca9555@24 {
  381. compatible = "nxp,pca9555";
  382. reg = <0x24>;
  383. gpio-controller;
  384. #gpio-cells = <2>;
  385. };
  386. hdmi_receiver: hdmi-receiver@48 {
  387. compatible = "nxp,tda19971";
  388. pinctrl-names = "default";
  389. pinctrl-0 = <&pinctrl_tda1997x>;
  390. reg = <0x48>;
  391. interrupt-parent = <&gpio1>;
  392. interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
  393. DOVDD-supply = <&reg_3p3>;
  394. AVDD-supply = <&reg_1p8b>;
  395. DVDD-supply = <&reg_1p8a>;
  396. #sound-dai-cells = <0>;
  397. nxp,audout-format = "i2s";
  398. nxp,audout-layout = <0>;
  399. nxp,audout-width = <16>;
  400. nxp,audout-mclk-fs = <128>;
  401. /*
  402. * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
  403. * and Y[11:4] across 16bits in the same cycle
  404. * which we map to VP[15:08]<->CSI_DATA[19:12]
  405. */
  406. nxp,vidout-portcfg =
  407. /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
  408. < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
  409. /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
  410. < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
  411. /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
  412. < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
  413. /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
  414. < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
  415. port {
  416. tda1997x_to_ipu1_csi0_mux: endpoint {
  417. remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  418. bus-width = <16>;
  419. hsync-active = <1>;
  420. vsync-active = <1>;
  421. data-active = <1>;
  422. };
  423. };
  424. };
  425. };
  426. &ipu1_csi0_from_ipu1_csi0_mux {
  427. bus-width = <16>;
  428. };
  429. &ipu1_csi0_mux_from_parallel_sensor {
  430. remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
  431. bus-width = <16>;
  432. };
  433. &ipu1_csi0 {
  434. pinctrl-names = "default";
  435. pinctrl-0 = <&pinctrl_ipu1_csi0>;
  436. };
  437. &pcie {
  438. pinctrl-names = "default";
  439. pinctrl-0 = <&pinctrl_pcie>;
  440. reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
  441. status = "okay";
  442. };
  443. &pwm2 {
  444. pinctrl-names = "default";
  445. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  446. status = "disabled";
  447. };
  448. &pwm3 {
  449. pinctrl-names = "default";
  450. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  451. status = "disabled";
  452. };
  453. &ssi1 {
  454. status = "okay";
  455. };
  456. &uart2 {
  457. pinctrl-names = "default";
  458. pinctrl-0 = <&pinctrl_uart2>;
  459. status = "okay";
  460. };
  461. &uart3 {
  462. pinctrl-names = "default";
  463. pinctrl-0 = <&pinctrl_uart3>;
  464. status = "okay";
  465. };
  466. &usbotg {
  467. vbus-supply = <&reg_usb_otg_vbus>;
  468. pinctrl-names = "default";
  469. pinctrl-0 = <&pinctrl_usbotg>;
  470. disable-over-current;
  471. dr_mode = "otg";
  472. status = "okay";
  473. };
  474. &usbh1 {
  475. vbus-supply = <&reg_usb_h1_vbus>;
  476. status = "okay";
  477. };
  478. &wdog1 {
  479. pinctrl-names = "default";
  480. pinctrl-0 = <&pinctrl_wdog>;
  481. fsl,ext-reset-output;
  482. };
  483. &iomuxc {
  484. pinctrl_audmux: audmuxgrp {
  485. fsl,pins = <
  486. MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
  487. MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0
  488. MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0
  489. >;
  490. };
  491. pinctrl_flexcan1: flexcan1grp {
  492. fsl,pins = <
  493. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  494. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  495. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
  496. >;
  497. };
  498. pinctrl_gpio_leds: gpioledsgrp {
  499. fsl,pins = <
  500. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  501. >;
  502. };
  503. pinctrl_gpmi_nand: gpminandgrp {
  504. fsl,pins = <
  505. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  506. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  507. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  508. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  509. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  510. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  511. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  512. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  513. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  514. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  515. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  516. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  517. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  518. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  519. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  520. >;
  521. };
  522. pinctrl_i2c1: i2c1grp {
  523. fsl,pins = <
  524. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  525. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  526. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  527. >;
  528. };
  529. pinctrl_i2c2: i2c2grp {
  530. fsl,pins = <
  531. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  532. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  533. >;
  534. };
  535. pinctrl_i2c3: i2c3grp {
  536. fsl,pins = <
  537. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  538. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  539. >;
  540. };
  541. pinctrl_ipu1_csi0: ipu1_csi0grp {
  542. fsl,pins = <
  543. MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
  544. MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
  545. MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
  546. MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
  547. MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
  548. MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
  549. MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
  550. MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
  551. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
  552. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
  553. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
  554. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
  555. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
  556. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
  557. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
  558. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
  559. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
  560. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
  561. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
  562. >;
  563. };
  564. pinctrl_pcie: pciegrp {
  565. fsl,pins = <
  566. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
  567. >;
  568. };
  569. pinctrl_pmic: pmicgrp {
  570. fsl,pins = <
  571. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  572. >;
  573. };
  574. pinctrl_pwm2: pwm2grp {
  575. fsl,pins = <
  576. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  577. >;
  578. };
  579. pinctrl_pwm3: pwm3grp {
  580. fsl,pins = <
  581. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  582. >;
  583. };
  584. pinctrl_tda1997x: tda1997xgrp {
  585. fsl,pins = <
  586. MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
  587. >;
  588. };
  589. pinctrl_uart2: uart2grp {
  590. fsl,pins = <
  591. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  592. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  593. >;
  594. };
  595. pinctrl_uart3: uart3grp {
  596. fsl,pins = <
  597. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  598. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  599. >;
  600. };
  601. pinctrl_usbotg: usbotggrp {
  602. fsl,pins = <
  603. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  604. >;
  605. };
  606. pinctrl_wdog: wdoggrp {
  607. fsl,pins = <
  608. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  609. >;
  610. };
  611. };