imx6qdl-gw54xx.dtsi 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/sound/fsl-imx-audmux.h>
  9. / {
  10. /* these are used by bootloader for disabling nodes */
  11. aliases {
  12. led0 = &led0;
  13. led1 = &led1;
  14. led2 = &led2;
  15. mmc0 = &usdhc3;
  16. nand = &gpmi;
  17. ssi0 = &ssi1;
  18. usb0 = &usbh1;
  19. usb1 = &usbotg;
  20. };
  21. chosen {
  22. bootargs = "console=ttymxc1,115200";
  23. };
  24. backlight {
  25. compatible = "pwm-backlight";
  26. pwms = <&pwm4 0 5000000>;
  27. brightness-levels = <0 4 8 16 32 64 128 255>;
  28. default-brightness-level = <7>;
  29. };
  30. gpio-keys {
  31. compatible = "gpio-keys";
  32. #address-cells = <1>;
  33. #size-cells = <0>;
  34. user-pb {
  35. label = "user_pb";
  36. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  37. linux,code = <BTN_0>;
  38. };
  39. user-pb1x {
  40. label = "user_pb1x";
  41. linux,code = <BTN_1>;
  42. interrupt-parent = <&gsc>;
  43. interrupts = <0>;
  44. };
  45. key-erased {
  46. label = "key-erased";
  47. linux,code = <BTN_2>;
  48. interrupt-parent = <&gsc>;
  49. interrupts = <1>;
  50. };
  51. eeprom-wp {
  52. label = "eeprom_wp";
  53. linux,code = <BTN_3>;
  54. interrupt-parent = <&gsc>;
  55. interrupts = <2>;
  56. };
  57. tamper {
  58. label = "tamper";
  59. linux,code = <BTN_4>;
  60. interrupt-parent = <&gsc>;
  61. interrupts = <5>;
  62. };
  63. switch-hold {
  64. label = "switch_hold";
  65. linux,code = <BTN_5>;
  66. interrupt-parent = <&gsc>;
  67. interrupts = <7>;
  68. };
  69. };
  70. leds {
  71. compatible = "gpio-leds";
  72. pinctrl-names = "default";
  73. pinctrl-0 = <&pinctrl_gpio_leds>;
  74. led0: user1 {
  75. label = "user1";
  76. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  77. default-state = "on";
  78. linux,default-trigger = "heartbeat";
  79. };
  80. led1: user2 {
  81. label = "user2";
  82. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  83. default-state = "off";
  84. };
  85. led2: user3 {
  86. label = "user3";
  87. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  88. default-state = "off";
  89. };
  90. };
  91. memory@10000000 {
  92. device_type = "memory";
  93. reg = <0x10000000 0x40000000>;
  94. };
  95. pps {
  96. compatible = "pps-gpio";
  97. pinctrl-names = "default";
  98. pinctrl-0 = <&pinctrl_pps>;
  99. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  100. status = "okay";
  101. };
  102. regulators {
  103. compatible = "simple-bus";
  104. #address-cells = <1>;
  105. #size-cells = <0>;
  106. reg_1p0v: regulator@0 {
  107. compatible = "regulator-fixed";
  108. reg = <0>;
  109. regulator-name = "1P0V";
  110. regulator-min-microvolt = <1000000>;
  111. regulator-max-microvolt = <1000000>;
  112. regulator-always-on;
  113. };
  114. reg_3p3v: regulator@1 {
  115. compatible = "regulator-fixed";
  116. reg = <1>;
  117. regulator-name = "3P3V";
  118. regulator-min-microvolt = <3300000>;
  119. regulator-max-microvolt = <3300000>;
  120. regulator-always-on;
  121. };
  122. reg_usb_h1_vbus: regulator@2 {
  123. compatible = "regulator-fixed";
  124. reg = <2>;
  125. regulator-name = "usb_h1_vbus";
  126. regulator-min-microvolt = <5000000>;
  127. regulator-max-microvolt = <5000000>;
  128. regulator-always-on;
  129. };
  130. reg_usb_otg_vbus: regulator@3 {
  131. compatible = "regulator-fixed";
  132. reg = <3>;
  133. regulator-name = "usb_otg_vbus";
  134. regulator-min-microvolt = <5000000>;
  135. regulator-max-microvolt = <5000000>;
  136. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  137. enable-active-high;
  138. };
  139. };
  140. sound-analog {
  141. compatible = "fsl,imx6q-ventana-sgtl5000",
  142. "fsl,imx-audio-sgtl5000";
  143. model = "sgtl5000-audio";
  144. ssi-controller = <&ssi1>;
  145. audio-codec = <&sgtl5000>;
  146. audio-routing =
  147. "MIC_IN", "Mic Jack",
  148. "Mic Jack", "Mic Bias",
  149. "Headphone Jack", "HP_OUT";
  150. mux-int-port = <1>;
  151. mux-ext-port = <4>;
  152. };
  153. };
  154. &audmux {
  155. pinctrl-names = "default";
  156. pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
  157. status = "okay";
  158. ssi2 {
  159. fsl,audmux-port = <1>;
  160. fsl,port-config = <
  161. (IMX_AUDMUX_V2_PTCR_TFSDIR |
  162. IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
  163. IMX_AUDMUX_V2_PTCR_TCLKDIR |
  164. IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
  165. IMX_AUDMUX_V2_PTCR_SYN)
  166. IMX_AUDMUX_V2_PDCR_RXDSEL(4)
  167. >;
  168. };
  169. aud5 {
  170. fsl,audmux-port = <4>;
  171. fsl,port-config = <
  172. IMX_AUDMUX_V2_PTCR_SYN
  173. IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
  174. };
  175. };
  176. &can1 {
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&pinctrl_flexcan1>;
  179. status = "okay";
  180. };
  181. &clks {
  182. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  183. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  184. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  185. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  186. };
  187. &ecspi2 {
  188. cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
  189. pinctrl-names = "default";
  190. pinctrl-0 = <&pinctrl_ecspi2>;
  191. status = "okay";
  192. };
  193. &fec {
  194. pinctrl-names = "default";
  195. pinctrl-0 = <&pinctrl_enet>;
  196. phy-mode = "rgmii-id";
  197. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  198. status = "okay";
  199. };
  200. &gpmi {
  201. pinctrl-names = "default";
  202. pinctrl-0 = <&pinctrl_gpmi_nand>;
  203. status = "okay";
  204. };
  205. &hdmi {
  206. ddc-i2c-bus = <&i2c3>;
  207. status = "okay";
  208. };
  209. &i2c1 {
  210. clock-frequency = <100000>;
  211. pinctrl-names = "default";
  212. pinctrl-0 = <&pinctrl_i2c1>;
  213. status = "okay";
  214. gsc: gsc@20 {
  215. compatible = "gw,gsc";
  216. reg = <0x20>;
  217. interrupt-parent = <&gpio1>;
  218. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  219. interrupt-controller;
  220. #interrupt-cells = <1>;
  221. #address-cells = <1>;
  222. #size-cells = <0>;
  223. adc {
  224. compatible = "gw,gsc-adc";
  225. #address-cells = <1>;
  226. #size-cells = <0>;
  227. channel@0 {
  228. gw,mode = <0>;
  229. reg = <0x00>;
  230. label = "temp";
  231. };
  232. channel@2 {
  233. gw,mode = <1>;
  234. reg = <0x02>;
  235. label = "vdd_vin";
  236. };
  237. channel@5 {
  238. gw,mode = <1>;
  239. reg = <0x05>;
  240. label = "vdd_3p3";
  241. };
  242. channel@8 {
  243. gw,mode = <1>;
  244. reg = <0x08>;
  245. label = "vdd_bat";
  246. };
  247. channel@b {
  248. gw,mode = <1>;
  249. reg = <0x0b>;
  250. label = "vdd_5p0";
  251. };
  252. channel@e {
  253. gw,mode = <1>;
  254. reg = <0xe>;
  255. label = "vdd_arm";
  256. };
  257. channel@11 {
  258. gw,mode = <1>;
  259. reg = <0x11>;
  260. label = "vdd_soc";
  261. };
  262. channel@14 {
  263. gw,mode = <1>;
  264. reg = <0x14>;
  265. label = "vdd_3p0";
  266. };
  267. channel@17 {
  268. gw,mode = <1>;
  269. reg = <0x17>;
  270. label = "vdd_1p5";
  271. };
  272. channel@1d {
  273. gw,mode = <1>;
  274. reg = <0x1d>;
  275. label = "vdd_1p8";
  276. };
  277. channel@20 {
  278. gw,mode = <1>;
  279. reg = <0x20>;
  280. label = "vdd_1p0";
  281. };
  282. channel@23 {
  283. gw,mode = <1>;
  284. reg = <0x23>;
  285. label = "vdd_2p5";
  286. };
  287. channel@26 {
  288. gw,mode = <1>;
  289. reg = <0x26>;
  290. label = "vdd_gps";
  291. };
  292. };
  293. fan-controller@2c {
  294. compatible = "gw,gsc-fan";
  295. #address-cells = <1>;
  296. #size-cells = <0>;
  297. reg = <0x2c>;
  298. };
  299. };
  300. gsc_gpio: gpio@23 {
  301. compatible = "nxp,pca9555";
  302. reg = <0x23>;
  303. gpio-controller;
  304. #gpio-cells = <2>;
  305. interrupt-parent = <&gsc>;
  306. interrupts = <4>;
  307. };
  308. eeprom1: eeprom@50 {
  309. compatible = "atmel,24c02";
  310. reg = <0x50>;
  311. pagesize = <16>;
  312. };
  313. eeprom2: eeprom@51 {
  314. compatible = "atmel,24c02";
  315. reg = <0x51>;
  316. pagesize = <16>;
  317. };
  318. eeprom3: eeprom@52 {
  319. compatible = "atmel,24c02";
  320. reg = <0x52>;
  321. pagesize = <16>;
  322. };
  323. eeprom4: eeprom@53 {
  324. compatible = "atmel,24c02";
  325. reg = <0x53>;
  326. pagesize = <16>;
  327. };
  328. rtc: ds1672@68 {
  329. compatible = "dallas,ds1672";
  330. reg = <0x68>;
  331. };
  332. };
  333. &i2c2 {
  334. clock-frequency = <100000>;
  335. pinctrl-names = "default";
  336. pinctrl-0 = <&pinctrl_i2c2>;
  337. status = "okay";
  338. pmic: pfuze100@8 {
  339. compatible = "fsl,pfuze100";
  340. reg = <0x08>;
  341. regulators {
  342. sw1a_reg: sw1ab {
  343. regulator-min-microvolt = <300000>;
  344. regulator-max-microvolt = <1875000>;
  345. regulator-boot-on;
  346. regulator-always-on;
  347. regulator-ramp-delay = <6250>;
  348. };
  349. sw1c_reg: sw1c {
  350. regulator-min-microvolt = <300000>;
  351. regulator-max-microvolt = <1875000>;
  352. regulator-boot-on;
  353. regulator-always-on;
  354. regulator-ramp-delay = <6250>;
  355. };
  356. sw2_reg: sw2 {
  357. regulator-min-microvolt = <800000>;
  358. regulator-max-microvolt = <3950000>;
  359. regulator-boot-on;
  360. regulator-always-on;
  361. };
  362. sw3a_reg: sw3a {
  363. regulator-min-microvolt = <400000>;
  364. regulator-max-microvolt = <1975000>;
  365. regulator-boot-on;
  366. regulator-always-on;
  367. };
  368. sw3b_reg: sw3b {
  369. regulator-min-microvolt = <400000>;
  370. regulator-max-microvolt = <1975000>;
  371. regulator-boot-on;
  372. regulator-always-on;
  373. };
  374. sw4_reg: sw4 {
  375. regulator-min-microvolt = <800000>;
  376. regulator-max-microvolt = <3300000>;
  377. };
  378. swbst_reg: swbst {
  379. regulator-min-microvolt = <5000000>;
  380. regulator-max-microvolt = <5150000>;
  381. regulator-boot-on;
  382. regulator-always-on;
  383. };
  384. snvs_reg: vsnvs {
  385. regulator-min-microvolt = <1000000>;
  386. regulator-max-microvolt = <3000000>;
  387. regulator-boot-on;
  388. regulator-always-on;
  389. };
  390. vref_reg: vrefddr {
  391. regulator-boot-on;
  392. regulator-always-on;
  393. };
  394. vgen1_reg: vgen1 {
  395. regulator-min-microvolt = <800000>;
  396. regulator-max-microvolt = <1550000>;
  397. };
  398. vgen2_reg: vgen2 {
  399. regulator-min-microvolt = <800000>;
  400. regulator-max-microvolt = <1550000>;
  401. };
  402. vgen3_reg: vgen3 {
  403. regulator-min-microvolt = <1800000>;
  404. regulator-max-microvolt = <3300000>;
  405. };
  406. vgen4_reg: vgen4 {
  407. regulator-min-microvolt = <1800000>;
  408. regulator-max-microvolt = <3300000>;
  409. regulator-always-on;
  410. };
  411. vgen5_reg: vgen5 {
  412. regulator-min-microvolt = <1800000>;
  413. regulator-max-microvolt = <3300000>;
  414. regulator-always-on;
  415. };
  416. vgen6_reg: vgen6 {
  417. regulator-min-microvolt = <1800000>;
  418. regulator-max-microvolt = <3300000>;
  419. regulator-always-on;
  420. };
  421. };
  422. };
  423. };
  424. &i2c3 {
  425. clock-frequency = <100000>;
  426. pinctrl-names = "default";
  427. pinctrl-0 = <&pinctrl_i2c3>;
  428. status = "okay";
  429. sgtl5000: audio-codec@a {
  430. compatible = "fsl,sgtl5000";
  431. reg = <0x0a>;
  432. clocks = <&clks IMX6QDL_CLK_CKO>;
  433. VDDA-supply = <&sw4_reg>;
  434. VDDIO-supply = <&reg_3p3v>;
  435. };
  436. touchscreen: egalax_ts@4 {
  437. compatible = "eeti,egalax_ts";
  438. reg = <0x04>;
  439. interrupt-parent = <&gpio7>;
  440. interrupts = <12 2>;
  441. wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
  442. };
  443. accel@1e {
  444. compatible = "nxp,fxos8700";
  445. reg = <0x1e>;
  446. };
  447. };
  448. &ldb {
  449. status = "okay";
  450. lvds-channel@0 {
  451. fsl,data-mapping = "spwg";
  452. fsl,data-width = <18>;
  453. status = "okay";
  454. display-timings {
  455. native-mode = <&timing0>;
  456. timing0: hsd100pxn1 {
  457. clock-frequency = <65000000>;
  458. hactive = <1024>;
  459. vactive = <768>;
  460. hback-porch = <220>;
  461. hfront-porch = <40>;
  462. vback-porch = <21>;
  463. vfront-porch = <7>;
  464. hsync-len = <60>;
  465. vsync-len = <10>;
  466. };
  467. };
  468. };
  469. };
  470. &pcie {
  471. pinctrl-names = "default";
  472. pinctrl-0 = <&pinctrl_pcie>;
  473. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  474. status = "okay";
  475. };
  476. &pwm1 {
  477. pinctrl-names = "default";
  478. pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
  479. status = "disabled";
  480. };
  481. &pwm2 {
  482. pinctrl-names = "default";
  483. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  484. status = "disabled";
  485. };
  486. &pwm3 {
  487. pinctrl-names = "default";
  488. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  489. status = "disabled";
  490. };
  491. &pwm4 {
  492. #pwm-cells = <2>;
  493. pinctrl-names = "default", "state_dio";
  494. pinctrl-0 = <&pinctrl_pwm4_backlight>;
  495. pinctrl-1 = <&pinctrl_pwm4_dio>;
  496. status = "okay";
  497. };
  498. &ssi1 {
  499. status = "okay";
  500. };
  501. &ssi2 {
  502. status = "okay";
  503. };
  504. &uart1 {
  505. pinctrl-names = "default";
  506. pinctrl-0 = <&pinctrl_uart1>;
  507. rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  508. status = "okay";
  509. };
  510. &uart2 {
  511. pinctrl-names = "default";
  512. pinctrl-0 = <&pinctrl_uart2>;
  513. status = "okay";
  514. };
  515. &uart5 {
  516. pinctrl-names = "default";
  517. pinctrl-0 = <&pinctrl_uart5>;
  518. status = "okay";
  519. };
  520. &usbotg {
  521. vbus-supply = <&reg_usb_otg_vbus>;
  522. pinctrl-names = "default";
  523. pinctrl-0 = <&pinctrl_usbotg>;
  524. disable-over-current;
  525. dr_mode = "otg";
  526. status = "okay";
  527. };
  528. &usbh1 {
  529. vbus-supply = <&reg_usb_h1_vbus>;
  530. status = "okay";
  531. };
  532. &usdhc3 {
  533. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  534. pinctrl-0 = <&pinctrl_usdhc3>;
  535. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  536. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  537. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  538. vmmc-supply = <&reg_3p3v>;
  539. no-1-8-v; /* firmware will remove if board revision supports */
  540. status = "okay";
  541. };
  542. &wdog1 {
  543. status = "disabled";
  544. };
  545. &wdog2 {
  546. pinctrl-names = "default";
  547. pinctrl-0 = <&pinctrl_wdog>;
  548. fsl,ext-reset-output;
  549. status = "okay";
  550. };
  551. &iomuxc {
  552. pinctrl_audmux: audmuxgrp {
  553. fsl,pins = <
  554. MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
  555. MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
  556. MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
  557. MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
  558. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
  559. MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
  560. MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
  561. MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
  562. >;
  563. };
  564. pinctrl_enet: enetgrp {
  565. fsl,pins = <
  566. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  567. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  568. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  569. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  570. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  571. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  572. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  573. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  574. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  575. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  576. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  577. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  578. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  579. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  580. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  581. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  582. >;
  583. };
  584. pinctrl_ecspi2: escpi2grp {
  585. fsl,pins = <
  586. MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
  587. MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
  588. MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
  589. MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
  590. >;
  591. };
  592. pinctrl_flexcan1: flexcan1grp {
  593. fsl,pins = <
  594. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  595. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  596. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
  597. >;
  598. };
  599. pinctrl_gpio_leds: gpioledsgrp {
  600. fsl,pins = <
  601. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  602. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  603. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  604. >;
  605. };
  606. pinctrl_gpmi_nand: gpminandgrp {
  607. fsl,pins = <
  608. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  609. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  610. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  611. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  612. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  613. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  614. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  615. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  616. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  617. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  618. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  619. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  620. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  621. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  622. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  623. >;
  624. };
  625. pinctrl_i2c1: i2c1grp {
  626. fsl,pins = <
  627. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  628. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  629. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  630. >;
  631. };
  632. pinctrl_i2c2: i2c2grp {
  633. fsl,pins = <
  634. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  635. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  636. >;
  637. };
  638. pinctrl_i2c3: i2c3grp {
  639. fsl,pins = <
  640. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  641. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  642. >;
  643. };
  644. pinctrl_pcie: pciegrp {
  645. fsl,pins = <
  646. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
  647. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
  648. >;
  649. };
  650. pinctrl_pps: ppsgrp {
  651. fsl,pins = <
  652. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  653. >;
  654. };
  655. pinctrl_pwm1: pwm1grp {
  656. fsl,pins = <
  657. MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
  658. >;
  659. };
  660. pinctrl_pwm2: pwm2grp {
  661. fsl,pins = <
  662. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  663. >;
  664. };
  665. pinctrl_pwm3: pwm3grp {
  666. fsl,pins = <
  667. MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  668. >;
  669. };
  670. pinctrl_pwm4_backlight: pwm4grpbacklight {
  671. fsl,pins = <
  672. /* LVDS_PWM J6.5 */
  673. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  674. >;
  675. };
  676. pinctrl_pwm4_dio: pwm4grpdio {
  677. fsl,pins = <
  678. /* DIO3 J16.4 */
  679. MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
  680. >;
  681. };
  682. pinctrl_uart1: uart1grp {
  683. fsl,pins = <
  684. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  685. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  686. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
  687. >;
  688. };
  689. pinctrl_uart2: uart2grp {
  690. fsl,pins = <
  691. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  692. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  693. >;
  694. };
  695. pinctrl_uart5: uart5grp {
  696. fsl,pins = <
  697. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  698. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  699. >;
  700. };
  701. pinctrl_usbotg: usbotggrp {
  702. fsl,pins = <
  703. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  704. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
  705. >;
  706. };
  707. pinctrl_usdhc3: usdhc3grp {
  708. fsl,pins = <
  709. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  710. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  711. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  712. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  713. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  714. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  715. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  716. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  717. >;
  718. };
  719. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  720. fsl,pins = <
  721. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  722. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  723. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  724. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  725. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  726. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  727. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  728. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  729. >;
  730. };
  731. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  732. fsl,pins = <
  733. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  734. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  735. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  736. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  737. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  738. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  739. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  740. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  741. >;
  742. };
  743. pinctrl_wdog: wdoggrp {
  744. fsl,pins = <
  745. MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
  746. >;
  747. };
  748. };