imx6qdl-gw52xx.dtsi 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. led2 = &led2;
  14. mmc0 = &usdhc3;
  15. nand = &gpmi;
  16. ssi0 = &ssi1;
  17. usb0 = &usbh1;
  18. usb1 = &usbotg;
  19. };
  20. chosen {
  21. bootargs = "console=ttymxc1,115200";
  22. };
  23. backlight {
  24. compatible = "pwm-backlight";
  25. pwms = <&pwm4 0 5000000>;
  26. brightness-levels = <0 4 8 16 32 64 128 255>;
  27. default-brightness-level = <7>;
  28. };
  29. gpio-keys {
  30. compatible = "gpio-keys";
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33. user-pb {
  34. label = "user_pb";
  35. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  36. linux,code = <BTN_0>;
  37. };
  38. user-pb1x {
  39. label = "user_pb1x";
  40. linux,code = <BTN_1>;
  41. interrupt-parent = <&gsc>;
  42. interrupts = <0>;
  43. };
  44. key-erased {
  45. label = "key-erased";
  46. linux,code = <BTN_2>;
  47. interrupt-parent = <&gsc>;
  48. interrupts = <1>;
  49. };
  50. eeprom-wp {
  51. label = "eeprom_wp";
  52. linux,code = <BTN_3>;
  53. interrupt-parent = <&gsc>;
  54. interrupts = <2>;
  55. };
  56. tamper {
  57. label = "tamper";
  58. linux,code = <BTN_4>;
  59. interrupt-parent = <&gsc>;
  60. interrupts = <5>;
  61. };
  62. switch-hold {
  63. label = "switch_hold";
  64. linux,code = <BTN_5>;
  65. interrupt-parent = <&gsc>;
  66. interrupts = <7>;
  67. };
  68. };
  69. leds {
  70. compatible = "gpio-leds";
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&pinctrl_gpio_leds>;
  73. led0: user1 {
  74. label = "user1";
  75. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  76. default-state = "on";
  77. linux,default-trigger = "heartbeat";
  78. };
  79. led1: user2 {
  80. label = "user2";
  81. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  82. default-state = "off";
  83. };
  84. led2: user3 {
  85. label = "user3";
  86. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  87. default-state = "off";
  88. };
  89. };
  90. memory@10000000 {
  91. device_type = "memory";
  92. reg = <0x10000000 0x20000000>;
  93. };
  94. pps {
  95. compatible = "pps-gpio";
  96. pinctrl-names = "default";
  97. pinctrl-0 = <&pinctrl_pps>;
  98. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  99. status = "okay";
  100. };
  101. reg_1p0v: regulator-1p0v {
  102. compatible = "regulator-fixed";
  103. regulator-name = "1P0V";
  104. regulator-min-microvolt = <1000000>;
  105. regulator-max-microvolt = <1000000>;
  106. regulator-always-on;
  107. };
  108. reg_3p3v: regulator-3p3v {
  109. compatible = "regulator-fixed";
  110. regulator-name = "3P3V";
  111. regulator-min-microvolt = <3300000>;
  112. regulator-max-microvolt = <3300000>;
  113. regulator-always-on;
  114. };
  115. reg_5p0v: regulator-5p0v {
  116. compatible = "regulator-fixed";
  117. regulator-name = "5P0V";
  118. regulator-min-microvolt = <5000000>;
  119. regulator-max-microvolt = <5000000>;
  120. regulator-always-on;
  121. };
  122. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  123. compatible = "regulator-fixed";
  124. regulator-name = "usb_otg_vbus";
  125. regulator-min-microvolt = <5000000>;
  126. regulator-max-microvolt = <5000000>;
  127. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  128. enable-active-high;
  129. };
  130. sound {
  131. compatible = "fsl,imx6q-ventana-sgtl5000",
  132. "fsl,imx-audio-sgtl5000";
  133. model = "sgtl5000-audio";
  134. ssi-controller = <&ssi1>;
  135. audio-codec = <&codec>;
  136. audio-routing =
  137. "MIC_IN", "Mic Jack",
  138. "Mic Jack", "Mic Bias",
  139. "Headphone Jack", "HP_OUT";
  140. mux-int-port = <1>;
  141. mux-ext-port = <4>;
  142. };
  143. };
  144. &audmux {
  145. pinctrl-names = "default";
  146. pinctrl-0 = <&pinctrl_audmux>;
  147. status = "okay";
  148. };
  149. &can1 {
  150. pinctrl-names = "default";
  151. pinctrl-0 = <&pinctrl_flexcan1>;
  152. status = "okay";
  153. };
  154. &clks {
  155. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  156. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  157. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  158. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  159. };
  160. &ecspi3 {
  161. cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  162. pinctrl-names = "default";
  163. pinctrl-0 = <&pinctrl_ecspi3>;
  164. status = "okay";
  165. };
  166. &fec {
  167. pinctrl-names = "default";
  168. pinctrl-0 = <&pinctrl_enet>;
  169. phy-mode = "rgmii-id";
  170. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  171. status = "okay";
  172. };
  173. &gpmi {
  174. pinctrl-names = "default";
  175. pinctrl-0 = <&pinctrl_gpmi_nand>;
  176. status = "okay";
  177. };
  178. &hdmi {
  179. ddc-i2c-bus = <&i2c3>;
  180. status = "okay";
  181. };
  182. &i2c1 {
  183. clock-frequency = <100000>;
  184. pinctrl-names = "default";
  185. pinctrl-0 = <&pinctrl_i2c1>;
  186. status = "okay";
  187. gsc: gsc@20 {
  188. compatible = "gw,gsc";
  189. reg = <0x20>;
  190. interrupt-parent = <&gpio1>;
  191. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  192. interrupt-controller;
  193. #interrupt-cells = <1>;
  194. #size-cells = <0>;
  195. adc {
  196. compatible = "gw,gsc-adc";
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. channel@0 {
  200. gw,mode = <0>;
  201. reg = <0x00>;
  202. label = "temp";
  203. };
  204. channel@2 {
  205. gw,mode = <1>;
  206. reg = <0x02>;
  207. label = "vdd_vin";
  208. };
  209. channel@5 {
  210. gw,mode = <1>;
  211. reg = <0x05>;
  212. label = "vdd_3p3";
  213. };
  214. channel@8 {
  215. gw,mode = <1>;
  216. reg = <0x08>;
  217. label = "vdd_bat";
  218. };
  219. channel@b {
  220. gw,mode = <1>;
  221. reg = <0x0b>;
  222. label = "vdd_5p0";
  223. };
  224. channel@e {
  225. gw,mode = <1>;
  226. reg = <0xe>;
  227. label = "vdd_arm";
  228. };
  229. channel@11 {
  230. gw,mode = <1>;
  231. reg = <0x11>;
  232. label = "vdd_soc";
  233. };
  234. channel@14 {
  235. gw,mode = <1>;
  236. reg = <0x14>;
  237. label = "vdd_3p0";
  238. };
  239. channel@17 {
  240. gw,mode = <1>;
  241. reg = <0x17>;
  242. label = "vdd_1p5";
  243. };
  244. channel@1d {
  245. gw,mode = <1>;
  246. reg = <0x1d>;
  247. label = "vdd_1p8";
  248. };
  249. channel@20 {
  250. gw,mode = <1>;
  251. reg = <0x20>;
  252. label = "vdd_1p0";
  253. };
  254. channel@23 {
  255. gw,mode = <1>;
  256. reg = <0x23>;
  257. label = "vdd_2p5";
  258. };
  259. channel@29 {
  260. gw,mode = <1>;
  261. reg = <0x29>;
  262. label = "vdd_an1";
  263. };
  264. };
  265. };
  266. gsc_gpio: gpio@23 {
  267. compatible = "nxp,pca9555";
  268. reg = <0x23>;
  269. gpio-controller;
  270. #gpio-cells = <2>;
  271. interrupt-parent = <&gsc>;
  272. interrupts = <4>;
  273. };
  274. eeprom1: eeprom@50 {
  275. compatible = "atmel,24c02";
  276. reg = <0x50>;
  277. pagesize = <16>;
  278. };
  279. eeprom2: eeprom@51 {
  280. compatible = "atmel,24c02";
  281. reg = <0x51>;
  282. pagesize = <16>;
  283. };
  284. eeprom3: eeprom@52 {
  285. compatible = "atmel,24c02";
  286. reg = <0x52>;
  287. pagesize = <16>;
  288. };
  289. eeprom4: eeprom@53 {
  290. compatible = "atmel,24c02";
  291. reg = <0x53>;
  292. pagesize = <16>;
  293. };
  294. rtc: ds1672@68 {
  295. compatible = "dallas,ds1672";
  296. reg = <0x68>;
  297. };
  298. };
  299. &i2c2 {
  300. clock-frequency = <100000>;
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&pinctrl_i2c2>;
  303. status = "okay";
  304. ltc3676: pmic@3c {
  305. compatible = "lltc,ltc3676";
  306. reg = <0x3c>;
  307. pinctrl-names = "default";
  308. pinctrl-0 = <&pinctrl_pmic>;
  309. interrupt-parent = <&gpio1>;
  310. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  311. regulators {
  312. /* VDD_SOC (1+R1/R2 = 1.635) */
  313. reg_vdd_soc: sw1 {
  314. regulator-name = "vddsoc";
  315. regulator-min-microvolt = <674400>;
  316. regulator-max-microvolt = <1308000>;
  317. lltc,fb-voltage-divider = <127000 200000>;
  318. regulator-ramp-delay = <7000>;
  319. regulator-boot-on;
  320. regulator-always-on;
  321. };
  322. /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
  323. reg_1p8v: sw2 {
  324. regulator-name = "vdd1p8";
  325. regulator-min-microvolt = <1033310>;
  326. regulator-max-microvolt = <2004000>;
  327. lltc,fb-voltage-divider = <301000 200000>;
  328. regulator-ramp-delay = <7000>;
  329. regulator-boot-on;
  330. regulator-always-on;
  331. };
  332. /* VDD_ARM (1+R1/R2 = 1.635) */
  333. reg_vdd_arm: sw3 {
  334. regulator-name = "vddarm";
  335. regulator-min-microvolt = <674400>;
  336. regulator-max-microvolt = <1308000>;
  337. lltc,fb-voltage-divider = <127000 200000>;
  338. regulator-ramp-delay = <7000>;
  339. regulator-boot-on;
  340. regulator-always-on;
  341. };
  342. /* VDD_DDR (1+R1/R2 = 2.105) */
  343. reg_vdd_ddr: sw4 {
  344. regulator-name = "vddddr";
  345. regulator-min-microvolt = <868310>;
  346. regulator-max-microvolt = <1684000>;
  347. lltc,fb-voltage-divider = <221000 200000>;
  348. regulator-ramp-delay = <7000>;
  349. regulator-boot-on;
  350. regulator-always-on;
  351. };
  352. /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
  353. reg_2p5v: ldo2 {
  354. regulator-name = "vdd2p5";
  355. regulator-min-microvolt = <2490375>;
  356. regulator-max-microvolt = <2490375>;
  357. lltc,fb-voltage-divider = <487000 200000>;
  358. regulator-boot-on;
  359. regulator-always-on;
  360. };
  361. /* VDD_AUD_1P8: Audio codec */
  362. reg_aud_1p8v: ldo3 {
  363. regulator-name = "vdd1p8a";
  364. regulator-min-microvolt = <1800000>;
  365. regulator-max-microvolt = <1800000>;
  366. regulator-boot-on;
  367. };
  368. /* VDD_HIGH (1+R1/R2 = 4.17) */
  369. reg_3p0v: ldo4 {
  370. regulator-name = "vdd3p0";
  371. regulator-min-microvolt = <3023250>;
  372. regulator-max-microvolt = <3023250>;
  373. lltc,fb-voltage-divider = <634000 200000>;
  374. regulator-boot-on;
  375. regulator-always-on;
  376. };
  377. };
  378. };
  379. };
  380. &i2c3 {
  381. clock-frequency = <100000>;
  382. pinctrl-names = "default";
  383. pinctrl-0 = <&pinctrl_i2c3>;
  384. status = "okay";
  385. codec: sgtl5000@a {
  386. compatible = "fsl,sgtl5000";
  387. reg = <0x0a>;
  388. clocks = <&clks IMX6QDL_CLK_CKO>;
  389. VDDA-supply = <&reg_1p8v>;
  390. VDDIO-supply = <&reg_3p3v>;
  391. };
  392. touchscreen: egalax_ts@4 {
  393. compatible = "eeti,egalax_ts";
  394. reg = <0x04>;
  395. interrupt-parent = <&gpio7>;
  396. interrupts = <12 2>;
  397. wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
  398. };
  399. accel@1e {
  400. compatible = "nxp,fxos8700";
  401. reg = <0x1e>;
  402. };
  403. };
  404. &ldb {
  405. status = "okay";
  406. lvds-channel@0 {
  407. fsl,data-mapping = "spwg";
  408. fsl,data-width = <18>;
  409. status = "okay";
  410. display-timings {
  411. native-mode = <&timing0>;
  412. timing0: hsd100pxn1 {
  413. clock-frequency = <65000000>;
  414. hactive = <1024>;
  415. vactive = <768>;
  416. hback-porch = <220>;
  417. hfront-porch = <40>;
  418. vback-porch = <21>;
  419. vfront-porch = <7>;
  420. hsync-len = <60>;
  421. vsync-len = <10>;
  422. };
  423. };
  424. };
  425. };
  426. &pcie {
  427. pinctrl-names = "default";
  428. pinctrl-0 = <&pinctrl_pcie>;
  429. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  430. status = "okay";
  431. };
  432. &pwm2 {
  433. pinctrl-names = "default";
  434. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  435. status = "disabled";
  436. };
  437. &pwm3 {
  438. pinctrl-names = "default";
  439. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  440. status = "disabled";
  441. };
  442. &pwm4 {
  443. #pwm-cells = <2>;
  444. pinctrl-names = "default";
  445. pinctrl-0 = <&pinctrl_pwm4>;
  446. status = "okay";
  447. };
  448. &ssi1 {
  449. status = "okay";
  450. };
  451. &uart1 {
  452. pinctrl-names = "default";
  453. pinctrl-0 = <&pinctrl_uart1>;
  454. rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  455. status = "okay";
  456. };
  457. &uart2 {
  458. pinctrl-names = "default";
  459. pinctrl-0 = <&pinctrl_uart2>;
  460. status = "okay";
  461. };
  462. &uart5 {
  463. pinctrl-names = "default";
  464. pinctrl-0 = <&pinctrl_uart5>;
  465. status = "okay";
  466. };
  467. &usbotg {
  468. vbus-supply = <&reg_usb_otg_vbus>;
  469. pinctrl-names = "default";
  470. pinctrl-0 = <&pinctrl_usbotg>;
  471. disable-over-current;
  472. dr_mode = "otg";
  473. status = "okay";
  474. };
  475. &usbh1 {
  476. status = "okay";
  477. };
  478. &usdhc3 {
  479. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  480. pinctrl-0 = <&pinctrl_usdhc3>;
  481. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  482. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  483. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  484. vmmc-supply = <&reg_3p3v>;
  485. no-1-8-v; /* firmware will remove if board revision supports */
  486. status = "okay";
  487. };
  488. &wdog1 {
  489. pinctrl-names = "default";
  490. pinctrl-0 = <&pinctrl_wdog>;
  491. fsl,ext-reset-output;
  492. };
  493. &iomuxc {
  494. pinctrl_audmux: audmuxgrp {
  495. fsl,pins = <
  496. MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
  497. MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
  498. MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
  499. MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
  500. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
  501. >;
  502. };
  503. pinctrl_ecspi3: escpi3grp {
  504. fsl,pins = <
  505. MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  506. MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  507. MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  508. MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
  509. >;
  510. };
  511. pinctrl_enet: enetgrp {
  512. fsl,pins = <
  513. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  514. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  515. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  516. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  517. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  518. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  519. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  520. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  521. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  522. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  523. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  524. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  525. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  526. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  527. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  528. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  529. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
  530. >;
  531. };
  532. pinctrl_flexcan1: flexcan1grp {
  533. fsl,pins = <
  534. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  535. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  536. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
  537. >;
  538. };
  539. pinctrl_gpio_leds: gpioledsgrp {
  540. fsl,pins = <
  541. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  542. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  543. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  544. >;
  545. };
  546. pinctrl_gpmi_nand: gpminandgrp {
  547. fsl,pins = <
  548. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  549. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  550. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  551. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  552. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  553. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  554. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  555. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  556. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  557. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  558. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  559. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  560. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  561. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  562. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  563. >;
  564. };
  565. pinctrl_i2c1: i2c1grp {
  566. fsl,pins = <
  567. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  568. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  569. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  570. >;
  571. };
  572. pinctrl_i2c2: i2c2grp {
  573. fsl,pins = <
  574. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  575. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  576. >;
  577. };
  578. pinctrl_i2c3: i2c3grp {
  579. fsl,pins = <
  580. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  581. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  582. >;
  583. };
  584. pinctrl_pcie: pciegrp {
  585. fsl,pins = <
  586. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
  587. >;
  588. };
  589. pinctrl_pmic: pmicgrp {
  590. fsl,pins = <
  591. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  592. >;
  593. };
  594. pinctrl_pps: ppsgrp {
  595. fsl,pins = <
  596. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  597. >;
  598. };
  599. pinctrl_pwm2: pwm2grp {
  600. fsl,pins = <
  601. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  602. >;
  603. };
  604. pinctrl_pwm3: pwm3grp {
  605. fsl,pins = <
  606. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  607. >;
  608. };
  609. pinctrl_pwm4: pwm4grp {
  610. fsl,pins = <
  611. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  612. >;
  613. };
  614. pinctrl_uart1: uart1grp {
  615. fsl,pins = <
  616. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  617. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  618. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
  619. >;
  620. };
  621. pinctrl_uart2: uart2grp {
  622. fsl,pins = <
  623. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  624. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  625. >;
  626. };
  627. pinctrl_uart5: uart5grp {
  628. fsl,pins = <
  629. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  630. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  631. >;
  632. };
  633. pinctrl_usbotg: usbotggrp {
  634. fsl,pins = <
  635. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  636. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
  637. >;
  638. };
  639. pinctrl_usdhc3: usdhc3grp {
  640. fsl,pins = <
  641. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  642. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  643. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  644. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  645. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  646. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  647. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  648. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  649. >;
  650. };
  651. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  652. fsl,pins = <
  653. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  654. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
  655. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  656. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  657. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  658. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  659. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  660. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  661. >;
  662. };
  663. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  664. fsl,pins = <
  665. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  666. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  667. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  668. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  669. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  670. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  671. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  672. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  673. >;
  674. };
  675. pinctrl_wdog: wdoggrp {
  676. fsl,pins = <
  677. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  678. >;
  679. };
  680. };