imx6qdl-gw51xx.dtsi 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. nand = &gpmi;
  14. usb0 = &usbh1;
  15. usb1 = &usbotg;
  16. };
  17. chosen {
  18. bootargs = "console=ttymxc1,115200";
  19. };
  20. gpio-keys {
  21. compatible = "gpio-keys";
  22. user-pb {
  23. label = "user_pb";
  24. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  25. linux,code = <BTN_0>;
  26. };
  27. user-pb1x {
  28. label = "user_pb1x";
  29. linux,code = <BTN_1>;
  30. interrupt-parent = <&gsc>;
  31. interrupts = <0>;
  32. };
  33. key-erased {
  34. label = "key-erased";
  35. linux,code = <BTN_2>;
  36. interrupt-parent = <&gsc>;
  37. interrupts = <1>;
  38. };
  39. eeprom-wp {
  40. label = "eeprom_wp";
  41. linux,code = <BTN_3>;
  42. interrupt-parent = <&gsc>;
  43. interrupts = <2>;
  44. };
  45. tamper {
  46. label = "tamper";
  47. linux,code = <BTN_4>;
  48. interrupt-parent = <&gsc>;
  49. interrupts = <5>;
  50. };
  51. switch-hold {
  52. label = "switch_hold";
  53. linux,code = <BTN_5>;
  54. interrupt-parent = <&gsc>;
  55. interrupts = <7>;
  56. };
  57. };
  58. leds {
  59. compatible = "gpio-leds";
  60. pinctrl-names = "default";
  61. pinctrl-0 = <&pinctrl_gpio_leds>;
  62. led0: user1 {
  63. label = "user1";
  64. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  65. default-state = "on";
  66. linux,default-trigger = "heartbeat";
  67. };
  68. led1: user2 {
  69. label = "user2";
  70. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  71. default-state = "off";
  72. };
  73. };
  74. memory@10000000 {
  75. device_type = "memory";
  76. reg = <0x10000000 0x20000000>;
  77. };
  78. pps {
  79. compatible = "pps-gpio";
  80. pinctrl-names = "default";
  81. pinctrl-0 = <&pinctrl_pps>;
  82. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  83. status = "okay";
  84. };
  85. reg_3p3v: regulator-3p3v {
  86. compatible = "regulator-fixed";
  87. regulator-name = "3P3V";
  88. regulator-min-microvolt = <3300000>;
  89. regulator-max-microvolt = <3300000>;
  90. regulator-always-on;
  91. };
  92. reg_5p0v: regulator-5p0v {
  93. compatible = "regulator-fixed";
  94. regulator-name = "5P0V";
  95. regulator-min-microvolt = <5000000>;
  96. regulator-max-microvolt = <5000000>;
  97. regulator-always-on;
  98. };
  99. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  100. compatible = "regulator-fixed";
  101. regulator-name = "usb_otg_vbus";
  102. regulator-min-microvolt = <5000000>;
  103. regulator-max-microvolt = <5000000>;
  104. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  105. enable-active-high;
  106. };
  107. };
  108. &fec {
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_enet>;
  111. phy-mode = "rgmii-id";
  112. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  113. status = "okay";
  114. };
  115. &gpmi {
  116. pinctrl-names = "default";
  117. pinctrl-0 = <&pinctrl_gpmi_nand>;
  118. status = "okay";
  119. };
  120. &hdmi {
  121. ddc-i2c-bus = <&i2c3>;
  122. status = "okay";
  123. };
  124. &i2c1 {
  125. clock-frequency = <100000>;
  126. pinctrl-names = "default";
  127. pinctrl-0 = <&pinctrl_i2c1>;
  128. status = "okay";
  129. gsc: gsc@20 {
  130. compatible = "gw,gsc";
  131. reg = <0x20>;
  132. interrupt-parent = <&gpio1>;
  133. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  134. interrupt-controller;
  135. #interrupt-cells = <1>;
  136. #size-cells = <0>;
  137. adc {
  138. compatible = "gw,gsc-adc";
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. channel@0 {
  142. gw,mode = <0>;
  143. reg = <0x00>;
  144. label = "temp";
  145. };
  146. channel@2 {
  147. gw,mode = <1>;
  148. reg = <0x02>;
  149. label = "vdd_vin";
  150. };
  151. channel@5 {
  152. gw,mode = <1>;
  153. reg = <0x05>;
  154. label = "vdd_3p3";
  155. };
  156. channel@8 {
  157. gw,mode = <1>;
  158. reg = <0x08>;
  159. label = "vdd_bat";
  160. };
  161. channel@b {
  162. gw,mode = <1>;
  163. reg = <0x0b>;
  164. label = "vdd_5p0";
  165. };
  166. channel@e {
  167. gw,mode = <1>;
  168. reg = <0xe>;
  169. label = "vdd_arm";
  170. };
  171. channel@11 {
  172. gw,mode = <1>;
  173. reg = <0x11>;
  174. label = "vdd_soc";
  175. };
  176. channel@14 {
  177. gw,mode = <1>;
  178. reg = <0x14>;
  179. label = "vdd_3p0";
  180. };
  181. channel@17 {
  182. gw,mode = <1>;
  183. reg = <0x17>;
  184. label = "vdd_1p5";
  185. };
  186. channel@1d {
  187. gw,mode = <1>;
  188. reg = <0x1d>;
  189. label = "vdd_1p8";
  190. };
  191. channel@20 {
  192. gw,mode = <1>;
  193. reg = <0x20>;
  194. label = "vdd_an1";
  195. };
  196. channel@23 {
  197. gw,mode = <1>;
  198. reg = <0x23>;
  199. label = "vdd_2p5";
  200. };
  201. };
  202. };
  203. gsc_gpio: gpio@23 {
  204. compatible = "nxp,pca9555";
  205. reg = <0x23>;
  206. gpio-controller;
  207. #gpio-cells = <2>;
  208. interrupt-parent = <&gsc>;
  209. interrupts = <4>;
  210. };
  211. eeprom1: eeprom@50 {
  212. compatible = "atmel,24c02";
  213. reg = <0x50>;
  214. pagesize = <16>;
  215. };
  216. eeprom2: eeprom@51 {
  217. compatible = "atmel,24c02";
  218. reg = <0x51>;
  219. pagesize = <16>;
  220. };
  221. eeprom3: eeprom@52 {
  222. compatible = "atmel,24c02";
  223. reg = <0x52>;
  224. pagesize = <16>;
  225. };
  226. eeprom4: eeprom@53 {
  227. compatible = "atmel,24c02";
  228. reg = <0x53>;
  229. pagesize = <16>;
  230. };
  231. rtc: ds1672@68 {
  232. compatible = "dallas,ds1672";
  233. reg = <0x68>;
  234. };
  235. };
  236. &i2c2 {
  237. clock-frequency = <100000>;
  238. pinctrl-names = "default";
  239. pinctrl-0 = <&pinctrl_i2c2>;
  240. status = "okay";
  241. ltc3676: pmic@3c {
  242. compatible = "lltc,ltc3676";
  243. reg = <0x3c>;
  244. pinctrl-names = "default";
  245. pinctrl-0 = <&pinctrl_pmic>;
  246. interrupt-parent = <&gpio1>;
  247. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  248. regulators {
  249. /* VDD_SOC (1+R1/R2 = 1.635) */
  250. reg_vdd_soc: sw1 {
  251. regulator-name = "vddsoc";
  252. regulator-min-microvolt = <674400>;
  253. regulator-max-microvolt = <1308000>;
  254. lltc,fb-voltage-divider = <127000 200000>;
  255. regulator-ramp-delay = <7000>;
  256. regulator-boot-on;
  257. regulator-always-on;
  258. };
  259. /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
  260. reg_1p8v: sw2 {
  261. regulator-name = "vdd1p8";
  262. regulator-min-microvolt = <1033310>;
  263. regulator-max-microvolt = <2004000>;
  264. lltc,fb-voltage-divider = <301000 200000>;
  265. regulator-ramp-delay = <7000>;
  266. regulator-boot-on;
  267. regulator-always-on;
  268. };
  269. /* VDD_ARM (1+R1/R2 = 1.635) */
  270. reg_vdd_arm: sw3 {
  271. regulator-name = "vddarm";
  272. regulator-min-microvolt = <674400>;
  273. regulator-max-microvolt = <1308000>;
  274. lltc,fb-voltage-divider = <127000 200000>;
  275. regulator-ramp-delay = <7000>;
  276. regulator-boot-on;
  277. regulator-always-on;
  278. };
  279. /* VDD_DDR (1+R1/R2 = 2.105) */
  280. reg_vdd_ddr: sw4 {
  281. regulator-name = "vddddr";
  282. regulator-min-microvolt = <868310>;
  283. regulator-max-microvolt = <1684000>;
  284. lltc,fb-voltage-divider = <221000 200000>;
  285. regulator-ramp-delay = <7000>;
  286. regulator-boot-on;
  287. regulator-always-on;
  288. };
  289. /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
  290. reg_2p5v: ldo2 {
  291. regulator-name = "vdd2p5";
  292. regulator-min-microvolt = <2490375>;
  293. regulator-max-microvolt = <2490375>;
  294. lltc,fb-voltage-divider = <487000 200000>;
  295. regulator-boot-on;
  296. regulator-always-on;
  297. };
  298. /* VDD_HIGH (1+R1/R2 = 4.17) */
  299. reg_3p0v: ldo4 {
  300. regulator-name = "vdd3p0";
  301. regulator-min-microvolt = <3023250>;
  302. regulator-max-microvolt = <3023250>;
  303. lltc,fb-voltage-divider = <634000 200000>;
  304. regulator-boot-on;
  305. regulator-always-on;
  306. };
  307. };
  308. };
  309. };
  310. &i2c3 {
  311. clock-frequency = <100000>;
  312. pinctrl-names = "default";
  313. pinctrl-0 = <&pinctrl_i2c3>;
  314. status = "okay";
  315. adv7180: camera@20 {
  316. compatible = "adi,adv7180";
  317. pinctrl-names = "default";
  318. pinctrl-0 = <&pinctrl_adv7180>;
  319. reg = <0x20>;
  320. powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
  321. interrupt-parent = <&gpio5>;
  322. interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
  323. port {
  324. adv7180_to_ipu1_csi0_mux: endpoint {
  325. remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  326. bus-width = <8>;
  327. };
  328. };
  329. };
  330. };
  331. &ipu1_csi0_from_ipu1_csi0_mux {
  332. bus-width = <8>;
  333. };
  334. &ipu1_csi0_mux_from_parallel_sensor {
  335. remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
  336. bus-width = <8>;
  337. };
  338. &ipu1_csi0 {
  339. pinctrl-names = "default";
  340. pinctrl-0 = <&pinctrl_ipu1_csi0>;
  341. };
  342. &pcie {
  343. pinctrl-names = "default";
  344. pinctrl-0 = <&pinctrl_pcie>;
  345. reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
  346. status = "okay";
  347. };
  348. &pwm2 {
  349. pinctrl-names = "default";
  350. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  351. status = "disabled";
  352. };
  353. &pwm3 {
  354. pinctrl-names = "default";
  355. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  356. status = "disabled";
  357. };
  358. &pwm4 {
  359. pinctrl-names = "default";
  360. pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
  361. status = "disabled";
  362. };
  363. &uart1 {
  364. pinctrl-names = "default";
  365. pinctrl-0 = <&pinctrl_uart1>;
  366. status = "okay";
  367. };
  368. &uart2 {
  369. pinctrl-names = "default";
  370. pinctrl-0 = <&pinctrl_uart2>;
  371. status = "okay";
  372. };
  373. &uart3 {
  374. pinctrl-names = "default";
  375. pinctrl-0 = <&pinctrl_uart3>;
  376. status = "okay";
  377. };
  378. &uart5 {
  379. pinctrl-names = "default";
  380. pinctrl-0 = <&pinctrl_uart5>;
  381. status = "okay";
  382. };
  383. &usbotg {
  384. vbus-supply = <&reg_usb_otg_vbus>;
  385. pinctrl-names = "default";
  386. pinctrl-0 = <&pinctrl_usbotg>;
  387. disable-over-current;
  388. dr_mode = "otg";
  389. status = "okay";
  390. };
  391. &usbh1 {
  392. status = "okay";
  393. };
  394. &wdog1 {
  395. pinctrl-names = "default";
  396. pinctrl-0 = <&pinctrl_wdog>;
  397. fsl,ext-reset-output;
  398. };
  399. &iomuxc {
  400. pinctrl_adv7180: adv7180grp {
  401. fsl,pins = <
  402. MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
  403. MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
  404. >;
  405. };
  406. pinctrl_enet: enetgrp {
  407. fsl,pins = <
  408. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  409. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  410. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  411. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  412. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  413. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  414. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  415. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  416. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  417. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  418. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  419. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  420. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  421. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  422. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  423. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  424. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
  425. >;
  426. };
  427. pinctrl_gpio_leds: gpioledsgrp {
  428. fsl,pins = <
  429. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  430. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  431. >;
  432. };
  433. pinctrl_gpmi_nand: gpminandgrp {
  434. fsl,pins = <
  435. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  436. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  437. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  438. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  439. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  440. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  441. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  442. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  443. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  444. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  445. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  446. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  447. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  448. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  449. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  450. >;
  451. };
  452. pinctrl_i2c1: i2c1grp {
  453. fsl,pins = <
  454. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  455. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  456. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
  457. >;
  458. };
  459. pinctrl_i2c2: i2c2grp {
  460. fsl,pins = <
  461. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  462. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  463. >;
  464. };
  465. pinctrl_i2c3: i2c3grp {
  466. fsl,pins = <
  467. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  468. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  469. >;
  470. };
  471. pinctrl_ipu1_csi0: ipu1csi0grp {
  472. fsl,pins = <
  473. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
  474. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
  475. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
  476. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
  477. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
  478. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
  479. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
  480. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
  481. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
  482. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
  483. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
  484. >;
  485. };
  486. pinctrl_pcie: pciegrp {
  487. fsl,pins = <
  488. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
  489. >;
  490. };
  491. pinctrl_pmic: pmicgrp {
  492. fsl,pins = <
  493. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  494. >;
  495. };
  496. pinctrl_pps: ppsgrp {
  497. fsl,pins = <
  498. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  499. >;
  500. };
  501. pinctrl_pwm2: pwm2grp {
  502. fsl,pins = <
  503. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  504. >;
  505. };
  506. pinctrl_pwm3: pwm3grp {
  507. fsl,pins = <
  508. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  509. >;
  510. };
  511. pinctrl_pwm4: pwm4grp {
  512. fsl,pins = <
  513. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  514. >;
  515. };
  516. pinctrl_uart1: uart1grp {
  517. fsl,pins = <
  518. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  519. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  520. >;
  521. };
  522. pinctrl_uart2: uart2grp {
  523. fsl,pins = <
  524. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  525. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  526. >;
  527. };
  528. pinctrl_uart3: uart3grp {
  529. fsl,pins = <
  530. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  531. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  532. >;
  533. };
  534. pinctrl_uart5: uart5grp {
  535. fsl,pins = <
  536. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  537. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  538. >;
  539. };
  540. pinctrl_usbotg: usbotggrp {
  541. fsl,pins = <
  542. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  543. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
  544. >;
  545. };
  546. pinctrl_wdog: wdoggrp {
  547. fsl,pins = <
  548. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  549. >;
  550. };
  551. };