imx6q-gw54xx.dts 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Gateworks Corporation
  4. */
  5. /dts-v1/;
  6. #include "imx6q.dtsi"
  7. #include "imx6qdl-gw54xx.dtsi"
  8. #include <dt-bindings/media/tda1997x.h>
  9. / {
  10. model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
  11. compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
  12. sound-digital {
  13. compatible = "simple-audio-card";
  14. simple-audio-card,name = "tda1997x-audio";
  15. simple-audio-card,format = "i2s";
  16. simple-audio-card,bitclock-master = <&sound_codec>;
  17. simple-audio-card,frame-master = <&sound_codec>;
  18. sound_cpu: simple-audio-card,cpu {
  19. sound-dai = <&ssi2>;
  20. };
  21. sound_codec: simple-audio-card,codec {
  22. sound-dai = <&hdmi_receiver>;
  23. };
  24. };
  25. };
  26. &i2c3 {
  27. adv7180: camera@20 {
  28. compatible = "adi,adv7180";
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&pinctrl_adv7180>;
  31. reg = <0x20>;
  32. powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
  33. interrupt-parent = <&gpio3>;
  34. interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  35. port {
  36. adv7180_to_ipu2_csi1_mux: endpoint {
  37. remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
  38. bus-width = <8>;
  39. };
  40. };
  41. };
  42. hdmi_receiver: hdmi-receiver@48 {
  43. compatible = "nxp,tda19971";
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&pinctrl_tda1997x>;
  46. reg = <0x48>;
  47. interrupt-parent = <&gpio1>;
  48. interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
  49. DOVDD-supply = <&reg_3p3v>;
  50. AVDD-supply = <&sw4_reg>;
  51. DVDD-supply = <&sw4_reg>;
  52. #sound-dai-cells = <0>;
  53. nxp,audout-format = "i2s";
  54. nxp,audout-layout = <0>;
  55. nxp,audout-width = <16>;
  56. nxp,audout-mclk-fs = <128>;
  57. /*
  58. * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
  59. * and Y[11:4] across 16bits in the same cycle
  60. * which we map to VP[15:08]<->CSI_DATA[19:12]
  61. */
  62. nxp,vidout-portcfg =
  63. /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
  64. < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
  65. /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
  66. < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
  67. /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
  68. < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
  69. /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
  70. < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
  71. port {
  72. tda1997x_to_ipu1_csi0_mux: endpoint {
  73. remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  74. bus-width = <16>;
  75. hsync-active = <1>;
  76. vsync-active = <1>;
  77. data-active = <1>;
  78. };
  79. };
  80. };
  81. };
  82. &ipu1_csi0_from_ipu1_csi0_mux {
  83. bus-width = <16>;
  84. };
  85. &ipu1_csi0_mux_from_parallel_sensor {
  86. remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
  87. bus-width = <16>;
  88. };
  89. &ipu1_csi0 {
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&pinctrl_ipu1_csi0>;
  92. };
  93. &ipu2_csi1_from_ipu2_csi1_mux {
  94. bus-width = <8>;
  95. };
  96. &ipu2_csi1_mux_from_parallel_sensor {
  97. remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
  98. bus-width = <8>;
  99. };
  100. &ipu2_csi1 {
  101. pinctrl-names = "default";
  102. pinctrl-0 = <&pinctrl_ipu2_csi1>;
  103. };
  104. &sata {
  105. status = "okay";
  106. };
  107. &iomuxc {
  108. pinctrl_adv7180: adv7180grp {
  109. fsl,pins = <
  110. MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
  111. MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
  112. >;
  113. };
  114. pinctrl_ipu1_csi0: ipu1_csi0grp {
  115. fsl,pins = <
  116. MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
  117. MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
  118. MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
  119. MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
  120. MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
  121. MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
  122. MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
  123. MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
  124. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
  125. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
  126. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
  127. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
  128. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
  129. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
  130. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
  131. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
  132. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
  133. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
  134. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
  135. >;
  136. };
  137. pinctrl_ipu2_csi1: ipu2_csi1grp {
  138. fsl,pins = <
  139. MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
  140. MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
  141. MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
  142. MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
  143. MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
  144. MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
  145. MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
  146. MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
  147. MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
  148. MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
  149. MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
  150. >;
  151. };
  152. pinctrl_tda1997x: tda1997xgrp {
  153. fsl,pins = <
  154. MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
  155. >;
  156. };
  157. };