Kconfig 48 KB

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  1. menu "ARM architecture"
  2. depends on ARM
  3. config SYS_ARCH
  4. default "arm"
  5. config ARM64
  6. bool
  7. select PHYS_64BIT
  8. select SYS_CACHE_SHIFT_6
  9. if ARM64
  10. config POSITION_INDEPENDENT
  11. bool "Generate position-independent pre-relocation code"
  12. help
  13. U-Boot expects to be linked to a specific hard-coded address, and to
  14. be loaded to and run from that address. This option lifts that
  15. restriction, thus allowing the code to be loaded to and executed from
  16. almost any 4K aligned address. This logic relies on the relocation
  17. information that is embedded in the binary to support U-Boot
  18. relocating itself to the top-of-RAM later during execution.
  19. config INIT_SP_RELATIVE
  20. bool "Specify the early stack pointer relative to the .bss section"
  21. default n if ARCH_QEMU
  22. default y if POSITION_INDEPENDENT
  23. help
  24. U-Boot typically uses a hard-coded value for the stack pointer
  25. before relocation. Enable this option to instead calculate the
  26. initial SP at run-time. This is useful to avoid hard-coding addresses
  27. into U-Boot, so that it can be loaded and executed at arbitrary
  28. addresses and thus avoid using arbitrary addresses at runtime.
  29. If this option is enabled, the early stack pointer is set to
  30. &_bss_start with a offset value added. The offset is specified by
  31. SYS_INIT_SP_BSS_OFFSET.
  32. config SYS_INIT_SP_BSS_OFFSET
  33. int "Early stack offset from the .bss base address"
  34. depends on INIT_SP_RELATIVE
  35. default 524288
  36. help
  37. This option's value is the offset added to &_bss_start in order to
  38. calculate the stack pointer. This offset should be large enough so
  39. that the early malloc region, global data (gd), and early stack usage
  40. do not overlap any appended DTB.
  41. config LINUX_KERNEL_IMAGE_HEADER
  42. bool
  43. help
  44. Place a Linux kernel image header at the start of the U-Boot binary.
  45. The format of the header is described in the Linux kernel source at
  46. Documentation/arm64/booting.txt. This feature is useful since the
  47. image header reports the amount of memory (BSS and similar) that
  48. U-Boot needs to use, but which isn't part of the binary.
  49. if LINUX_KERNEL_IMAGE_HEADER
  50. config LNX_KRNL_IMG_TEXT_OFFSET_BASE
  51. hex
  52. help
  53. The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
  54. TEXT_OFFSET value written to the Linux kernel image header.
  55. endif
  56. endif
  57. config GIC_V3_ITS
  58. bool "ARM GICV3 ITS"
  59. select REGMAP
  60. select SYSCON
  61. help
  62. ARM GICV3 Interrupt translation service (ITS).
  63. Basic support for programming locality specific peripheral
  64. interrupts (LPI) configuration tables and enable LPI tables.
  65. LPI configuration table can be used by u-boot or Linux.
  66. ARM GICV3 has limitation, once the LPI table is enabled, LPI
  67. configuration table can not be re-programmed, unless GICV3 reset.
  68. config STATIC_RELA
  69. bool
  70. default y if ARM64
  71. config DMA_ADDR_T_64BIT
  72. bool
  73. default y if ARM64
  74. config HAS_VBAR
  75. bool
  76. config HAS_THUMB2
  77. bool
  78. # Used for compatibility with asm files copied from the kernel
  79. config ARM_ASM_UNIFIED
  80. bool
  81. default y
  82. # Used for compatibility with asm files copied from the kernel
  83. config THUMB2_KERNEL
  84. bool
  85. config SYS_ICACHE_OFF
  86. bool "Do not enable icache"
  87. default n
  88. help
  89. Do not enable instruction cache in U-Boot.
  90. config SPL_SYS_ICACHE_OFF
  91. bool "Do not enable icache in SPL"
  92. depends on SPL
  93. default SYS_ICACHE_OFF
  94. help
  95. Do not enable instruction cache in SPL.
  96. config SYS_DCACHE_OFF
  97. bool "Do not enable dcache"
  98. default n
  99. help
  100. Do not enable data cache in U-Boot.
  101. config SPL_SYS_DCACHE_OFF
  102. bool "Do not enable dcache in SPL"
  103. depends on SPL
  104. default SYS_DCACHE_OFF
  105. help
  106. Do not enable data cache in SPL.
  107. config SYS_ARM_CACHE_CP15
  108. bool "CP15 based cache enabling support"
  109. help
  110. Select this if your processor suports enabling caches by using
  111. CP15 registers.
  112. config SYS_ARM_MMU
  113. bool "MMU-based Paged Memory Management Support"
  114. select SYS_ARM_CACHE_CP15
  115. help
  116. Select if you want MMU-based virtualised addressing space
  117. support via paged memory management.
  118. config SYS_ARM_MPU
  119. bool 'Use the ARM v7 PMSA Compliant MPU'
  120. help
  121. Some ARM systems without an MMU have instead a Memory Protection
  122. Unit (MPU) that defines the type and permissions for regions of
  123. memory.
  124. If your CPU has an MPU then you should choose 'y' here unless you
  125. know that you do not want to use the MPU.
  126. # If set, the workarounds for these ARM errata are applied early during U-Boot
  127. # startup. Note that in general these options force the workarounds to be
  128. # applied; no CPU-type/version detection exists, unlike the similar options in
  129. # the Linux kernel. Do not set these options unless they apply! Also note that
  130. # the following can be machine-specific errata. These do have ability to
  131. # provide rudimentary version and machine-specific checks, but expect no
  132. # product checks:
  133. # CONFIG_ARM_ERRATA_430973
  134. # CONFIG_ARM_ERRATA_454179
  135. # CONFIG_ARM_ERRATA_621766
  136. # CONFIG_ARM_ERRATA_798870
  137. # CONFIG_ARM_ERRATA_801819
  138. # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
  139. # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
  140. config ARM_ERRATA_430973
  141. bool
  142. config ARM_ERRATA_454179
  143. bool
  144. config ARM_ERRATA_621766
  145. bool
  146. config ARM_ERRATA_716044
  147. bool
  148. config ARM_ERRATA_725233
  149. bool
  150. config ARM_ERRATA_742230
  151. bool
  152. config ARM_ERRATA_743622
  153. bool
  154. config ARM_ERRATA_751472
  155. bool
  156. config ARM_ERRATA_761320
  157. bool
  158. config ARM_ERRATA_773022
  159. bool
  160. config ARM_ERRATA_774769
  161. bool
  162. config ARM_ERRATA_794072
  163. bool
  164. config ARM_ERRATA_798870
  165. bool
  166. config ARM_ERRATA_801819
  167. bool
  168. config ARM_ERRATA_826974
  169. bool
  170. config ARM_ERRATA_828024
  171. bool
  172. config ARM_ERRATA_829520
  173. bool
  174. config ARM_ERRATA_833069
  175. bool
  176. config ARM_ERRATA_833471
  177. bool
  178. config ARM_ERRATA_845369
  179. bool
  180. config ARM_ERRATA_852421
  181. bool
  182. config ARM_ERRATA_852423
  183. bool
  184. config ARM_ERRATA_855873
  185. bool
  186. config ARM_CORTEX_A8_CVE_2017_5715
  187. bool
  188. config ARM_CORTEX_A15_CVE_2017_5715
  189. bool
  190. config CPU_ARM720T
  191. bool
  192. select SYS_CACHE_SHIFT_5
  193. imply SYS_ARM_MMU
  194. config CPU_ARM920T
  195. bool
  196. select SYS_CACHE_SHIFT_5
  197. imply SYS_ARM_MMU
  198. config CPU_ARM926EJS
  199. bool
  200. select SYS_CACHE_SHIFT_5
  201. imply SYS_ARM_MMU
  202. config CPU_ARM946ES
  203. bool
  204. select SYS_CACHE_SHIFT_5
  205. imply SYS_ARM_MMU
  206. config CPU_ARM1136
  207. bool
  208. select SYS_CACHE_SHIFT_5
  209. imply SYS_ARM_MMU
  210. config CPU_ARM1176
  211. bool
  212. select HAS_VBAR
  213. select SYS_CACHE_SHIFT_5
  214. imply SYS_ARM_MMU
  215. config CPU_V7A
  216. bool
  217. select HAS_THUMB2
  218. select HAS_VBAR
  219. select SYS_CACHE_SHIFT_6
  220. imply SYS_ARM_MMU
  221. config CPU_V7M
  222. bool
  223. select HAS_THUMB2
  224. select SYS_ARM_MPU
  225. select SYS_CACHE_SHIFT_5
  226. select SYS_THUMB_BUILD
  227. select THUMB2_KERNEL
  228. config CPU_V7R
  229. bool
  230. select HAS_THUMB2
  231. select SYS_ARM_CACHE_CP15
  232. select SYS_ARM_MPU
  233. select SYS_CACHE_SHIFT_6
  234. config CPU_PXA
  235. bool
  236. select SYS_CACHE_SHIFT_5
  237. imply SYS_ARM_MMU
  238. config CPU_SA1100
  239. bool
  240. select SYS_CACHE_SHIFT_5
  241. imply SYS_ARM_MMU
  242. config SYS_CPU
  243. default "arm720t" if CPU_ARM720T
  244. default "arm920t" if CPU_ARM920T
  245. default "arm926ejs" if CPU_ARM926EJS
  246. default "arm946es" if CPU_ARM946ES
  247. default "arm1136" if CPU_ARM1136
  248. default "arm1176" if CPU_ARM1176
  249. default "armv7" if CPU_V7A
  250. default "armv7" if CPU_V7R
  251. default "armv7m" if CPU_V7M
  252. default "pxa" if CPU_PXA
  253. default "sa1100" if CPU_SA1100
  254. default "armv8" if ARM64
  255. config SYS_ARM_ARCH
  256. int
  257. default 4 if CPU_ARM720T
  258. default 4 if CPU_ARM920T
  259. default 5 if CPU_ARM926EJS
  260. default 5 if CPU_ARM946ES
  261. default 6 if CPU_ARM1136
  262. default 6 if CPU_ARM1176
  263. default 7 if CPU_V7A
  264. default 7 if CPU_V7M
  265. default 7 if CPU_V7R
  266. default 5 if CPU_PXA
  267. default 4 if CPU_SA1100
  268. default 8 if ARM64
  269. config SYS_CACHE_SHIFT_5
  270. bool
  271. config SYS_CACHE_SHIFT_6
  272. bool
  273. config SYS_CACHE_SHIFT_7
  274. bool
  275. config SYS_CACHELINE_SIZE
  276. int
  277. default 128 if SYS_CACHE_SHIFT_7
  278. default 64 if SYS_CACHE_SHIFT_6
  279. default 32 if SYS_CACHE_SHIFT_5
  280. choice
  281. prompt "Select the ARM data write cache policy"
  282. default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
  283. TARGET_BCMNSP || CPU_PXA || RZA1
  284. default SYS_ARM_CACHE_WRITEBACK
  285. config SYS_ARM_CACHE_WRITEBACK
  286. bool "Write-back (WB)"
  287. help
  288. A write updates the cache only and marks the cache line as dirty.
  289. External memory is updated only when the line is evicted or explicitly
  290. cleaned.
  291. config SYS_ARM_CACHE_WRITETHROUGH
  292. bool "Write-through (WT)"
  293. help
  294. A write updates both the cache and the external memory system.
  295. This does not mark the cache line as dirty.
  296. config SYS_ARM_CACHE_WRITEALLOC
  297. bool "Write allocation (WA)"
  298. help
  299. A cache line is allocated on a write miss. This means that executing a
  300. store instruction on the processor might cause a burst read to occur.
  301. There is a linefill to obtain the data for the cache line, before the
  302. write is performed.
  303. endchoice
  304. config ARCH_CPU_INIT
  305. bool "Enable ARCH_CPU_INIT"
  306. help
  307. Some architectures require a call to arch_cpu_init().
  308. Say Y here to enable it
  309. config SYS_ARCH_TIMER
  310. bool "ARM Generic Timer support"
  311. depends on CPU_V7A || ARM64
  312. default y if ARM64
  313. help
  314. The ARM Generic Timer (aka arch-timer) provides an architected
  315. interface to a timer source on an SoC.
  316. It is mandatory for ARMv8 implementation and widely available
  317. on ARMv7 systems.
  318. config ARM_SMCCC
  319. bool "Support for ARM SMC Calling Convention (SMCCC)"
  320. depends on CPU_V7A || ARM64
  321. select ARM_PSCI_FW
  322. help
  323. Say Y here if you want to enable ARM SMC Calling Convention.
  324. This should be enabled if U-Boot needs to communicate with system
  325. firmware (for example, PSCI) according to SMCCC.
  326. config SEMIHOSTING
  327. bool "support boot from semihosting"
  328. help
  329. In emulated environments, semihosting is a way for
  330. the hosted environment to call out to the emulator to
  331. retrieve files from the host machine.
  332. config SYS_THUMB_BUILD
  333. bool "Build U-Boot using the Thumb instruction set"
  334. depends on !ARM64
  335. help
  336. Use this flag to build U-Boot using the Thumb instruction set for
  337. ARM architectures. Thumb instruction set provides better code
  338. density. For ARM architectures that support Thumb2 this flag will
  339. result in Thumb2 code generated by GCC.
  340. config SPL_SYS_THUMB_BUILD
  341. bool "Build SPL using the Thumb instruction set"
  342. default y if SYS_THUMB_BUILD
  343. depends on !ARM64 && SPL
  344. help
  345. Use this flag to build SPL using the Thumb instruction set for
  346. ARM architectures. Thumb instruction set provides better code
  347. density. For ARM architectures that support Thumb2 this flag will
  348. result in Thumb2 code generated by GCC.
  349. config TPL_SYS_THUMB_BUILD
  350. bool "Build TPL using the Thumb instruction set"
  351. default y if SYS_THUMB_BUILD
  352. depends on TPL && !ARM64
  353. help
  354. Use this flag to build TPL using the Thumb instruction set for
  355. ARM architectures. Thumb instruction set provides better code
  356. density. For ARM architectures that support Thumb2 this flag will
  357. result in Thumb2 code generated by GCC.
  358. config SYS_L2CACHE_OFF
  359. bool "L2cache off"
  360. help
  361. If SoC does not support L2CACHE or one does not want to enable
  362. L2CACHE, choose this option.
  363. config ENABLE_ARM_SOC_BOOT0_HOOK
  364. bool "prepare BOOT0 header"
  365. help
  366. If the SoC's BOOT0 requires a header area filled with (magic)
  367. values, then choose this option, and create a file included as
  368. <asm/arch/boot0.h> which contains the required assembler code.
  369. config ARM_CORTEX_CPU_IS_UP
  370. bool
  371. default n
  372. config USE_ARCH_MEMCPY
  373. bool "Use an assembly optimized implementation of memcpy"
  374. default y
  375. depends on !ARM64
  376. help
  377. Enable the generation of an optimized version of memcpy.
  378. Such an implementation may be faster under some conditions
  379. but may increase the binary size.
  380. config SPL_USE_ARCH_MEMCPY
  381. bool "Use an assembly optimized implementation of memcpy for SPL"
  382. default y if USE_ARCH_MEMCPY
  383. depends on !ARM64 && SPL
  384. help
  385. Enable the generation of an optimized version of memcpy.
  386. Such an implementation may be faster under some conditions
  387. but may increase the binary size.
  388. config TPL_USE_ARCH_MEMCPY
  389. bool "Use an assembly optimized implementation of memcpy for TPL"
  390. default y if USE_ARCH_MEMCPY
  391. depends on !ARM64 && TPL
  392. help
  393. Enable the generation of an optimized version of memcpy.
  394. Such an implementation may be faster under some conditions
  395. but may increase the binary size.
  396. config USE_ARCH_MEMSET
  397. bool "Use an assembly optimized implementation of memset"
  398. default y
  399. depends on !ARM64
  400. help
  401. Enable the generation of an optimized version of memset.
  402. Such an implementation may be faster under some conditions
  403. but may increase the binary size.
  404. config SPL_USE_ARCH_MEMSET
  405. bool "Use an assembly optimized implementation of memset for SPL"
  406. default y if USE_ARCH_MEMSET
  407. depends on !ARM64 && SPL
  408. help
  409. Enable the generation of an optimized version of memset.
  410. Such an implementation may be faster under some conditions
  411. but may increase the binary size.
  412. config TPL_USE_ARCH_MEMSET
  413. bool "Use an assembly optimized implementation of memset for TPL"
  414. default y if USE_ARCH_MEMSET
  415. depends on !ARM64 && TPL
  416. help
  417. Enable the generation of an optimized version of memset.
  418. Such an implementation may be faster under some conditions
  419. but may increase the binary size.
  420. config ARM64_SUPPORT_AARCH32
  421. bool "ARM64 system support AArch32 execution state"
  422. depends on ARM64
  423. default y if !TARGET_THUNDERX_88XX
  424. help
  425. This ARM64 system supports AArch32 execution state.
  426. choice
  427. prompt "Target select"
  428. default TARGET_HIKEY
  429. config ARCH_AT91
  430. bool "Atmel AT91"
  431. select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
  432. select SPL_SEPARATE_BSS if SPL
  433. config TARGET_EDB93XX
  434. bool "Support edb93xx"
  435. select CPU_ARM920T
  436. select PL010_SERIAL
  437. config TARGET_ASPENITE
  438. bool "Support aspenite"
  439. select CPU_ARM926EJS
  440. config TARGET_GPLUGD
  441. bool "Support gplugd"
  442. select CPU_ARM926EJS
  443. config ARCH_DAVINCI
  444. bool "TI DaVinci"
  445. select CPU_ARM926EJS
  446. select SPL_DM_SPI if SPL
  447. imply CMD_SAVES
  448. help
  449. Support for TI's DaVinci platform.
  450. config ARCH_KIRKWOOD
  451. bool "Marvell Kirkwood"
  452. select ARCH_MISC_INIT
  453. select BOARD_EARLY_INIT_F
  454. select CPU_ARM926EJS
  455. config ARCH_MVEBU
  456. bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
  457. select DM
  458. select DM_ETH
  459. select DM_SERIAL
  460. select DM_SPI
  461. select DM_SPI_FLASH
  462. select SPL_DM_SPI if SPL
  463. select SPL_DM_SPI_FLASH if SPL
  464. select OF_CONTROL
  465. select OF_SEPARATE
  466. select SPI
  467. imply CMD_DM
  468. config TARGET_APF27
  469. bool "Support apf27"
  470. select CPU_ARM926EJS
  471. select SUPPORT_SPL
  472. config ARCH_ORION5X
  473. bool "Marvell Orion"
  474. select CPU_ARM926EJS
  475. config TARGET_SPEAR300
  476. bool "Support spear300"
  477. select BOARD_EARLY_INIT_F
  478. select CPU_ARM926EJS
  479. select PL011_SERIAL
  480. imply CMD_SAVES
  481. config TARGET_SPEAR310
  482. bool "Support spear310"
  483. select BOARD_EARLY_INIT_F
  484. select CPU_ARM926EJS
  485. select PL011_SERIAL
  486. imply CMD_SAVES
  487. config TARGET_SPEAR320
  488. bool "Support spear320"
  489. select BOARD_EARLY_INIT_F
  490. select CPU_ARM926EJS
  491. select PL011_SERIAL
  492. imply CMD_SAVES
  493. config TARGET_SPEAR600
  494. bool "Support spear600"
  495. select BOARD_EARLY_INIT_F
  496. select CPU_ARM926EJS
  497. select PL011_SERIAL
  498. imply CMD_SAVES
  499. config TARGET_STV0991
  500. bool "Support stv0991"
  501. select CPU_V7A
  502. select DM
  503. select DM_SERIAL
  504. select DM_SPI
  505. select DM_SPI_FLASH
  506. select PL01X_SERIAL
  507. select SPI
  508. select SPI_FLASH
  509. imply CMD_DM
  510. config TARGET_X600
  511. bool "Support x600"
  512. select BOARD_LATE_INIT
  513. select CPU_ARM926EJS
  514. select PL011_SERIAL
  515. select SUPPORT_SPL
  516. config TARGET_FLEA3
  517. bool "Support flea3"
  518. select CPU_ARM1136
  519. config ARCH_BCM283X
  520. bool "Broadcom BCM283X family"
  521. select DM
  522. select DM_GPIO
  523. select DM_SERIAL
  524. select OF_CONTROL
  525. select PL01X_SERIAL
  526. select SERIAL_SEARCH_ALL
  527. imply CMD_DM
  528. imply FAT_WRITE
  529. config ARCH_BCM63158
  530. bool "Broadcom BCM63158 family"
  531. select DM
  532. select OF_CONTROL
  533. imply CMD_DM
  534. config ARCH_BCM68360
  535. bool "Broadcom BCM68360 family"
  536. select DM
  537. select OF_CONTROL
  538. imply CMD_DM
  539. config ARCH_BCM6858
  540. bool "Broadcom BCM6858 family"
  541. select DM
  542. select OF_CONTROL
  543. imply CMD_DM
  544. config TARGET_VEXPRESS_CA15_TC2
  545. bool "Support vexpress_ca15_tc2"
  546. select CPU_V7A
  547. select CPU_V7_HAS_NONSEC
  548. select CPU_V7_HAS_VIRT
  549. select PL011_SERIAL
  550. config ARCH_BCMSTB
  551. bool "Broadcom BCM7XXX family"
  552. select CPU_V7A
  553. select DM
  554. select OF_CONTROL
  555. select OF_PRIOR_STAGE
  556. imply CMD_DM
  557. help
  558. This enables support for Broadcom ARM-based set-top box
  559. chipsets, including the 7445 family of chips.
  560. config TARGET_VEXPRESS_CA5X2
  561. bool "Support vexpress_ca5x2"
  562. select CPU_V7A
  563. select PL011_SERIAL
  564. config TARGET_VEXPRESS_CA9X4
  565. bool "Support vexpress_ca9x4"
  566. select CPU_V7A
  567. select PL011_SERIAL
  568. config TARGET_BCM23550_W1D
  569. bool "Support bcm23550_w1d"
  570. select CPU_V7A
  571. imply CRC32_VERIFY
  572. imply FAT_WRITE
  573. config TARGET_BCM28155_AP
  574. bool "Support bcm28155_ap"
  575. select CPU_V7A
  576. imply CRC32_VERIFY
  577. imply FAT_WRITE
  578. config TARGET_BCMCYGNUS
  579. bool "Support bcmcygnus"
  580. select CPU_V7A
  581. imply BCM_SF2_ETH
  582. imply BCM_SF2_ETH_GMAC
  583. imply CMD_HASH
  584. imply CRC32_VERIFY
  585. imply FAT_WRITE
  586. imply HASH_VERIFY
  587. imply NETDEVICES
  588. config TARGET_BCMNSP
  589. bool "Support bcmnsp"
  590. select CPU_V7A
  591. config TARGET_BCMNS2
  592. bool "Support Broadcom Northstar2"
  593. select ARM64
  594. help
  595. Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
  596. ARMv8 Cortex-A57 processors targeting a broad range of networking
  597. applications.
  598. config TARGET_BCMNS3
  599. bool "Support Broadcom NS3"
  600. select ARM64
  601. select BOARD_LATE_INIT
  602. help
  603. Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
  604. ARMv8 Cortex-A72 processors targeting a broad range of networking
  605. applications.
  606. config ARCH_EXYNOS
  607. bool "Samsung EXYNOS"
  608. select DM
  609. select DM_GPIO
  610. select DM_I2C
  611. select DM_KEYBOARD
  612. select DM_SERIAL
  613. select DM_SPI
  614. select DM_SPI_FLASH
  615. select SPI
  616. imply SYS_THUMB_BUILD
  617. imply CMD_DM
  618. imply FAT_WRITE
  619. config ARCH_S5PC1XX
  620. bool "Samsung S5PC1XX"
  621. select CPU_V7A
  622. select DM
  623. select DM_GPIO
  624. select DM_I2C
  625. select DM_SERIAL
  626. imply CMD_DM
  627. config ARCH_HIGHBANK
  628. bool "Calxeda Highbank"
  629. select CPU_V7A
  630. select PL011_SERIAL
  631. config ARCH_INTEGRATOR
  632. bool "ARM Ltd. Integrator family"
  633. select DM
  634. select DM_SERIAL
  635. select PL01X_SERIAL
  636. imply CMD_DM
  637. config ARCH_IPQ40XX
  638. bool "Qualcomm IPQ40xx SoCs"
  639. select CPU_V7A
  640. select DM
  641. select DM_GPIO
  642. select DM_SERIAL
  643. select DM_RESET
  644. select MSM_SMEM
  645. select PINCTRL
  646. select CLK
  647. select SMEM
  648. select OF_CONTROL
  649. imply CMD_DM
  650. config ARCH_KEYSTONE
  651. bool "TI Keystone"
  652. select CMD_POWEROFF
  653. select CPU_V7A
  654. select SUPPORT_SPL
  655. select SYS_ARCH_TIMER
  656. select SYS_THUMB_BUILD
  657. imply CMD_MTDPARTS
  658. imply CMD_SAVES
  659. imply FIT
  660. config ARCH_K3
  661. bool "Texas Instruments' K3 Architecture"
  662. select SPL
  663. select SUPPORT_SPL
  664. select FIT
  665. config ARCH_OMAP2PLUS
  666. bool "TI OMAP2+"
  667. select CPU_V7A
  668. select SPL_BOARD_INIT if SPL
  669. select SPL_STACK_R if SPL
  670. select SUPPORT_SPL
  671. imply TI_SYSC if DM && OF_CONTROL
  672. imply FIT
  673. config ARCH_MESON
  674. bool "Amlogic Meson"
  675. imply DISTRO_DEFAULTS
  676. imply DM_RNG
  677. help
  678. Support for the Meson SoC family developed by Amlogic Inc.,
  679. targeted at media players and tablet computers. We currently
  680. support the S905 (GXBaby) 64-bit SoC.
  681. config ARCH_MEDIATEK
  682. bool "MediaTek SoCs"
  683. select DM
  684. select OF_CONTROL
  685. select SPL_DM if SPL
  686. select SPL_LIBCOMMON_SUPPORT if SPL
  687. select SPL_LIBGENERIC_SUPPORT if SPL
  688. select SPL_OF_CONTROL if SPL
  689. select SUPPORT_SPL
  690. help
  691. Support for the MediaTek SoCs family developed by MediaTek Inc.
  692. Please refer to doc/README.mediatek for more information.
  693. config ARCH_LPC32XX
  694. bool "NXP LPC32xx platform"
  695. select CPU_ARM926EJS
  696. select DM
  697. select DM_GPIO
  698. select DM_SERIAL
  699. select SPL_DM if SPL
  700. select SUPPORT_SPL
  701. imply CMD_DM
  702. config ARCH_IMX8
  703. bool "NXP i.MX8 platform"
  704. select ARM64
  705. select DM
  706. select OF_CONTROL
  707. select ENABLE_ARM_SOC_BOOT0_HOOK
  708. config ARCH_IMX8M
  709. bool "NXP i.MX8M platform"
  710. select ARM64
  711. select SYS_FSL_HAS_SEC if IMX_HAB
  712. select SYS_FSL_SEC_COMPAT_4
  713. select SYS_FSL_SEC_LE
  714. select DM
  715. select SUPPORT_SPL
  716. imply CMD_DM
  717. config ARCH_IMXRT
  718. bool "NXP i.MXRT platform"
  719. select CPU_V7M
  720. select DM
  721. select DM_SERIAL
  722. select SUPPORT_SPL
  723. imply CMD_DM
  724. config ARCH_MX23
  725. bool "NXP i.MX23 family"
  726. select CPU_ARM926EJS
  727. select PL011_SERIAL
  728. select SUPPORT_SPL
  729. config ARCH_MX25
  730. bool "NXP MX25"
  731. select CPU_ARM926EJS
  732. imply MXC_GPIO
  733. config ARCH_MX28
  734. bool "NXP i.MX28 family"
  735. select CPU_ARM926EJS
  736. select PL011_SERIAL
  737. select SUPPORT_SPL
  738. config ARCH_MX31
  739. bool "NXP i.MX31 family"
  740. select CPU_ARM1136
  741. config ARCH_MX7ULP
  742. bool "NXP MX7ULP"
  743. select CPU_V7A
  744. select SYS_FSL_HAS_SEC if IMX_HAB
  745. select SYS_FSL_SEC_COMPAT_4
  746. select SYS_FSL_SEC_LE
  747. select ROM_UNIFIED_SECTIONS
  748. imply MXC_GPIO
  749. imply SYS_THUMB_BUILD
  750. config ARCH_MX7
  751. bool "Freescale MX7"
  752. select ARCH_MISC_INIT
  753. select CPU_V7A
  754. select SYS_FSL_HAS_SEC if IMX_HAB
  755. select SYS_FSL_SEC_COMPAT_4
  756. select SYS_FSL_SEC_LE
  757. imply BOARD_EARLY_INIT_F
  758. imply MXC_GPIO
  759. imply SYS_THUMB_BUILD
  760. config ARCH_MX6
  761. bool "Freescale MX6"
  762. select CPU_V7A
  763. select SYS_FSL_HAS_SEC
  764. select SYS_FSL_SEC_COMPAT_4
  765. select SYS_FSL_SEC_LE
  766. imply MXC_GPIO
  767. imply SYS_THUMB_BUILD
  768. if ARCH_MX6
  769. config SPL_LDSCRIPT
  770. default "arch/arm/mach-omap2/u-boot-spl.lds"
  771. endif
  772. config ARCH_MX5
  773. bool "Freescale MX5"
  774. select BOARD_EARLY_INIT_F
  775. select CPU_V7A
  776. imply MXC_GPIO
  777. config ARCH_NEXELL
  778. bool "Nexell S5P4418/S5P6818 SoC"
  779. select ENABLE_ARM_SOC_BOOT0_HOOK
  780. select DM
  781. config ARCH_OWL
  782. bool "Actions Semi OWL SoCs"
  783. select DM
  784. select DM_ETH
  785. select DM_SERIAL
  786. select OWL_SERIAL
  787. select CLK
  788. select CLK_OWL
  789. select OF_CONTROL
  790. select SYS_RELOC_GD_ENV_ADDR
  791. imply CMD_DM
  792. config ARCH_QEMU
  793. bool "QEMU Virtual Platform"
  794. select DM
  795. select DM_SERIAL
  796. select OF_CONTROL
  797. select PL01X_SERIAL
  798. imply CMD_DM
  799. imply DM_RNG
  800. imply DM_RTC
  801. imply RTC_PL031
  802. config ARCH_RMOBILE
  803. bool "Renesas ARM SoCs"
  804. select DM
  805. select DM_SERIAL
  806. imply BOARD_EARLY_INIT_F
  807. imply CMD_DM
  808. imply FAT_WRITE
  809. imply SYS_THUMB_BUILD
  810. imply ARCH_MISC_INIT if DISPLAY_CPUINFO
  811. config TARGET_S32V234EVB
  812. bool "Support s32v234evb"
  813. select ARM64
  814. select SYS_FSL_ERRATUM_ESDHC111
  815. config ARCH_SNAPDRAGON
  816. bool "Qualcomm Snapdragon SoCs"
  817. select ARM64
  818. select DM
  819. select DM_GPIO
  820. select DM_SERIAL
  821. select MSM_SMEM
  822. select OF_CONTROL
  823. select OF_SEPARATE
  824. select SMEM
  825. select SPMI
  826. imply CMD_DM
  827. config ARCH_SOCFPGA
  828. bool "Altera SOCFPGA family"
  829. select ARCH_EARLY_INIT_R
  830. select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
  831. select ARM64 if TARGET_SOCFPGA_SOC64
  832. select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
  833. select DM
  834. select DM_SERIAL
  835. select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
  836. select OF_CONTROL
  837. select SPL_DM_RESET if DM_RESET
  838. select SPL_DM_SERIAL
  839. select SPL_LIBCOMMON_SUPPORT
  840. select SPL_LIBGENERIC_SUPPORT
  841. select SPL_NAND_SUPPORT if SPL_NAND_DENALI
  842. select SPL_OF_CONTROL
  843. select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
  844. select SPL_SERIAL_SUPPORT
  845. select SPL_SYSRESET
  846. select SPL_WATCHDOG_SUPPORT
  847. select SUPPORT_SPL
  848. select SYS_NS16550
  849. select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
  850. select SYSRESET
  851. select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
  852. select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
  853. imply CMD_DM
  854. imply CMD_MTDPARTS
  855. imply CRC32_VERIFY
  856. imply DM_SPI
  857. imply DM_SPI_FLASH
  858. imply FAT_WRITE
  859. imply SPL
  860. imply SPL_DM
  861. imply SPL_DM_SPI
  862. imply SPL_DM_SPI_FLASH
  863. imply SPL_LIBDISK_SUPPORT
  864. imply SPL_MMC_SUPPORT
  865. imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
  866. imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
  867. imply SPL_SPI_FLASH_SUPPORT
  868. imply SPL_SPI_SUPPORT
  869. imply L2X0_CACHE
  870. config ARCH_SUNXI
  871. bool "Support sunxi (Allwinner) SoCs"
  872. select BINMAN
  873. select CMD_GPIO
  874. select CMD_MMC if MMC
  875. select CMD_USB if DISTRO_DEFAULTS
  876. select CLK
  877. select DM
  878. select DM_ETH
  879. select DM_GPIO
  880. select DM_KEYBOARD
  881. select DM_MMC if MMC
  882. select DM_SCSI if SCSI
  883. select DM_SERIAL
  884. select DM_USB if DISTRO_DEFAULTS
  885. select OF_BOARD_SETUP
  886. select OF_CONTROL
  887. select OF_SEPARATE
  888. select SPECIFY_CONSOLE_INDEX
  889. select SPL_STACK_R if SPL
  890. select SPL_SYS_MALLOC_SIMPLE if SPL
  891. select SPL_SYS_THUMB_BUILD if !ARM64
  892. select SUNXI_GPIO
  893. select SYS_NS16550
  894. select SYS_THUMB_BUILD if !ARM64
  895. select USB if DISTRO_DEFAULTS
  896. select USB_KEYBOARD if DISTRO_DEFAULTS
  897. select USB_STORAGE if DISTRO_DEFAULTS
  898. select SPL_USE_TINY_PRINTF
  899. select USE_PREBOOT
  900. select SYS_RELOC_GD_ENV_ADDR
  901. imply BOARD_LATE_INIT
  902. imply CMD_DM
  903. imply CMD_GPT
  904. imply CMD_UBI if MTD_RAW_NAND
  905. imply DISTRO_DEFAULTS
  906. imply FAT_WRITE
  907. imply FIT
  908. imply OF_LIBFDT_OVERLAY
  909. imply PRE_CONSOLE_BUFFER
  910. imply SPL_GPIO_SUPPORT
  911. imply SPL_LIBCOMMON_SUPPORT
  912. imply SPL_LIBGENERIC_SUPPORT
  913. imply SPL_MMC_SUPPORT if MMC
  914. imply SPL_POWER_SUPPORT
  915. imply SPL_SERIAL_SUPPORT
  916. imply USB_GADGET
  917. config ARCH_U8500
  918. bool "ST-Ericsson U8500 Series"
  919. select CPU_V7A
  920. select DM
  921. select DM_GPIO
  922. select DM_MMC if MMC
  923. select DM_SERIAL
  924. select DM_USB if USB
  925. select OF_CONTROL
  926. select SYSRESET
  927. select TIMER
  928. imply ARM_PL180_MMCI
  929. imply DM_RTC
  930. imply NOMADIK_MTU_TIMER
  931. imply PL01X_SERIAL
  932. imply RTC_PL031
  933. imply SYSRESET_SYSCON
  934. config ARCH_VERSAL
  935. bool "Support Xilinx Versal Platform"
  936. select ARM64
  937. select CLK
  938. select DM
  939. select DM_ETH if NET
  940. select DM_MMC if MMC
  941. select DM_SERIAL
  942. select OF_CONTROL
  943. imply BOARD_LATE_INIT
  944. imply ENV_VARS_UBOOT_RUNTIME_CONFIG
  945. config ARCH_VF610
  946. bool "Freescale Vybrid"
  947. select CPU_V7A
  948. select SYS_FSL_ERRATUM_ESDHC111
  949. imply CMD_MTDPARTS
  950. imply MTD_RAW_NAND
  951. config ARCH_ZYNQ
  952. bool "Xilinx Zynq based platform"
  953. select CLK
  954. select CLK_ZYNQ
  955. select CPU_V7A
  956. select DM
  957. select DM_ETH if NET
  958. select DM_MMC if MMC
  959. select DM_SERIAL
  960. select DM_SPI
  961. select DM_SPI_FLASH
  962. select DM_USB if USB
  963. select OF_CONTROL
  964. select SPI
  965. select SPL_BOARD_INIT if SPL
  966. select SPL_CLK if SPL
  967. select SPL_DM if SPL
  968. select SPL_DM_SPI if SPL
  969. select SPL_DM_SPI_FLASH if SPL
  970. select SPL_OF_CONTROL if SPL
  971. select SPL_SEPARATE_BSS if SPL
  972. select SUPPORT_SPL
  973. imply ARCH_EARLY_INIT_R
  974. imply BOARD_LATE_INIT
  975. imply CMD_CLK
  976. imply CMD_DM
  977. imply CMD_SPL
  978. imply ENV_VARS_UBOOT_RUNTIME_CONFIG
  979. imply FAT_WRITE
  980. config ARCH_ZYNQMP_R5
  981. bool "Xilinx ZynqMP R5 based platform"
  982. select CLK
  983. select CPU_V7R
  984. select DM
  985. select DM_ETH if NET
  986. select DM_MMC if MMC
  987. select DM_SERIAL
  988. select OF_CONTROL
  989. imply CMD_DM
  990. imply DM_USB_GADGET
  991. config ARCH_ZYNQMP
  992. bool "Xilinx ZynqMP based platform"
  993. select ARM64
  994. select CLK
  995. select DM
  996. select DM_ETH if NET
  997. select DM_MAILBOX
  998. select DM_MMC if MMC
  999. select DM_SERIAL
  1000. select DM_SPI if SPI
  1001. select DM_SPI_FLASH if DM_SPI
  1002. select DM_USB if USB
  1003. select FIRMWARE
  1004. select OF_CONTROL
  1005. select SPL_BOARD_INIT if SPL
  1006. select SPL_CLK if SPL
  1007. select SPL_DM if SPL
  1008. select SPL_DM_SPI if SPI && SPL_DM
  1009. select SPL_DM_SPI_FLASH if SPL_DM_SPI
  1010. select SPL_DM_MAILBOX if SPL
  1011. select SPL_FIRMWARE if SPL
  1012. select SPL_SEPARATE_BSS if SPL
  1013. select SUPPORT_SPL
  1014. select ZYNQMP_IPI
  1015. imply BOARD_LATE_INIT
  1016. imply CMD_DM
  1017. imply ENV_VARS_UBOOT_RUNTIME_CONFIG
  1018. imply FAT_WRITE
  1019. imply MP
  1020. imply DM_USB_GADGET
  1021. config ARCH_TEGRA
  1022. bool "NVIDIA Tegra"
  1023. imply DISTRO_DEFAULTS
  1024. imply FAT_WRITE
  1025. config TARGET_VEXPRESS64_AEMV8A
  1026. bool "Support vexpress_aemv8a"
  1027. select ARM64
  1028. select PL01X_SERIAL
  1029. config TARGET_VEXPRESS64_BASE_FVP
  1030. bool "Support Versatile Express ARMv8a FVP BASE model"
  1031. select ARM64
  1032. select PL01X_SERIAL
  1033. select SEMIHOSTING
  1034. config TARGET_VEXPRESS64_JUNO
  1035. bool "Support Versatile Express Juno Development Platform"
  1036. select ARM64
  1037. select PL01X_SERIAL
  1038. select DM
  1039. select OF_CONTROL
  1040. select OF_BOARD
  1041. select CLK
  1042. select DM_SERIAL
  1043. select ARM_PSCI_FW
  1044. select PSCI_RESET
  1045. select DM_ETH
  1046. select BLK
  1047. select USB
  1048. select DM_USB
  1049. config TARGET_TOTAL_COMPUTE
  1050. bool "Support Total Compute Platform"
  1051. select ARM64
  1052. select PL01X_SERIAL
  1053. select DM
  1054. select DM_SERIAL
  1055. select DM_MMC
  1056. select DM_GPIO
  1057. config TARGET_LS2080A_EMU
  1058. bool "Support ls2080a_emu"
  1059. select ARCH_LS2080A
  1060. select ARM64
  1061. select ARMV8_MULTIENTRY
  1062. select FSL_DDR_SYNC_REFRESH
  1063. help
  1064. Support for Freescale LS2080A_EMU platform.
  1065. The LS2080A Development System (EMULATOR) is a pre-silicon
  1066. development platform that supports the QorIQ LS2080A
  1067. Layerscape Architecture processor.
  1068. config TARGET_LS1088AQDS
  1069. bool "Support ls1088aqds"
  1070. select ARCH_LS1088A
  1071. select ARM64
  1072. select ARMV8_MULTIENTRY
  1073. select ARCH_SUPPORT_TFABOOT
  1074. select BOARD_LATE_INIT
  1075. select SUPPORT_SPL
  1076. select FSL_DDR_INTERACTIVE if !SD_BOOT
  1077. help
  1078. Support for NXP LS1088AQDS platform.
  1079. The LS1088A Development System (QDS) is a high-performance
  1080. development platform that supports the QorIQ LS1088A
  1081. Layerscape Architecture processor.
  1082. config TARGET_LS2080AQDS
  1083. bool "Support ls2080aqds"
  1084. select ARCH_LS2080A
  1085. select ARM64
  1086. select ARMV8_MULTIENTRY
  1087. select ARCH_SUPPORT_TFABOOT
  1088. select BOARD_LATE_INIT
  1089. select SUPPORT_SPL
  1090. imply SCSI
  1091. imply SCSI_AHCI
  1092. select FSL_DDR_BIST
  1093. select FSL_DDR_INTERACTIVE if !SPL
  1094. help
  1095. Support for Freescale LS2080AQDS platform.
  1096. The LS2080A Development System (QDS) is a high-performance
  1097. development platform that supports the QorIQ LS2080A
  1098. Layerscape Architecture processor.
  1099. config TARGET_LS2080ARDB
  1100. bool "Support ls2080ardb"
  1101. select ARCH_LS2080A
  1102. select ARM64
  1103. select ARMV8_MULTIENTRY
  1104. select ARCH_SUPPORT_TFABOOT
  1105. select BOARD_LATE_INIT
  1106. select SUPPORT_SPL
  1107. select FSL_DDR_BIST
  1108. select FSL_DDR_INTERACTIVE if !SPL
  1109. imply SCSI
  1110. imply SCSI_AHCI
  1111. help
  1112. Support for Freescale LS2080ARDB platform.
  1113. The LS2080A Reference design board (RDB) is a high-performance
  1114. development platform that supports the QorIQ LS2080A
  1115. Layerscape Architecture processor.
  1116. config TARGET_LS2081ARDB
  1117. bool "Support ls2081ardb"
  1118. select ARCH_LS2080A
  1119. select ARM64
  1120. select ARMV8_MULTIENTRY
  1121. select BOARD_LATE_INIT
  1122. select SUPPORT_SPL
  1123. help
  1124. Support for Freescale LS2081ARDB platform.
  1125. The LS2081A Reference design board (RDB) is a high-performance
  1126. development platform that supports the QorIQ LS2081A/LS2041A
  1127. Layerscape Architecture processor.
  1128. config TARGET_LX2160ARDB
  1129. bool "Support lx2160ardb"
  1130. select ARCH_LX2160A
  1131. select ARM64
  1132. select ARMV8_MULTIENTRY
  1133. select ARCH_SUPPORT_TFABOOT
  1134. select BOARD_LATE_INIT
  1135. help
  1136. Support for NXP LX2160ARDB platform.
  1137. The lx2160ardb (LX2160A Reference design board (RDB)
  1138. is a high-performance development platform that supports the
  1139. QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
  1140. config TARGET_LX2160AQDS
  1141. bool "Support lx2160aqds"
  1142. select ARCH_LX2160A
  1143. select ARM64
  1144. select ARMV8_MULTIENTRY
  1145. select ARCH_SUPPORT_TFABOOT
  1146. select BOARD_LATE_INIT
  1147. help
  1148. Support for NXP LX2160AQDS platform.
  1149. The lx2160aqds (LX2160A QorIQ Development System (QDS)
  1150. is a high-performance development platform that supports the
  1151. QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
  1152. config TARGET_LX2162AQDS
  1153. bool "Support lx2162aqds"
  1154. select ARCH_LX2162A
  1155. select ARCH_MISC_INIT
  1156. select ARM64
  1157. select ARMV8_MULTIENTRY
  1158. select ARCH_SUPPORT_TFABOOT
  1159. select BOARD_LATE_INIT
  1160. help
  1161. Support for NXP LX2162AQDS platform.
  1162. The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
  1163. config TARGET_HIKEY
  1164. bool "Support HiKey 96boards Consumer Edition Platform"
  1165. select ARM64
  1166. select DM
  1167. select DM_GPIO
  1168. select DM_SERIAL
  1169. select OF_CONTROL
  1170. select PL01X_SERIAL
  1171. select SPECIFY_CONSOLE_INDEX
  1172. imply CMD_DM
  1173. help
  1174. Support for HiKey 96boards platform. It features a HI6220
  1175. SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
  1176. config TARGET_HIKEY960
  1177. bool "Support HiKey960 96boards Consumer Edition Platform"
  1178. select ARM64
  1179. select DM
  1180. select DM_SERIAL
  1181. select OF_CONTROL
  1182. select PL01X_SERIAL
  1183. imply CMD_DM
  1184. help
  1185. Support for HiKey960 96boards platform. It features a HI3660
  1186. SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
  1187. config TARGET_POPLAR
  1188. bool "Support Poplar 96boards Enterprise Edition Platform"
  1189. select ARM64
  1190. select DM
  1191. select DM_SERIAL
  1192. select DM_USB
  1193. select OF_CONTROL
  1194. select PL01X_SERIAL
  1195. imply CMD_DM
  1196. help
  1197. Support for Poplar 96boards EE platform. It features a HI3798cv200
  1198. SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
  1199. making it capable of running any commercial set-top solution based on
  1200. Linux or Android.
  1201. config TARGET_LS1012AQDS
  1202. bool "Support ls1012aqds"
  1203. select ARCH_LS1012A
  1204. select ARM64
  1205. select ARCH_SUPPORT_TFABOOT
  1206. select BOARD_LATE_INIT
  1207. help
  1208. Support for Freescale LS1012AQDS platform.
  1209. The LS1012A Development System (QDS) is a high-performance
  1210. development platform that supports the QorIQ LS1012A
  1211. Layerscape Architecture processor.
  1212. config TARGET_LS1012ARDB
  1213. bool "Support ls1012ardb"
  1214. select ARCH_LS1012A
  1215. select ARM64
  1216. select ARCH_SUPPORT_TFABOOT
  1217. select BOARD_LATE_INIT
  1218. imply SCSI
  1219. imply SCSI_AHCI
  1220. help
  1221. Support for Freescale LS1012ARDB platform.
  1222. The LS1012A Reference design board (RDB) is a high-performance
  1223. development platform that supports the QorIQ LS1012A
  1224. Layerscape Architecture processor.
  1225. config TARGET_LS1012A2G5RDB
  1226. bool "Support ls1012a2g5rdb"
  1227. select ARCH_LS1012A
  1228. select ARM64
  1229. select ARCH_SUPPORT_TFABOOT
  1230. select BOARD_LATE_INIT
  1231. imply SCSI
  1232. help
  1233. Support for Freescale LS1012A2G5RDB platform.
  1234. The LS1012A 2G5 Reference design board (RDB) is a high-performance
  1235. development platform that supports the QorIQ LS1012A
  1236. Layerscape Architecture processor.
  1237. config TARGET_LS1012AFRWY
  1238. bool "Support ls1012afrwy"
  1239. select ARCH_LS1012A
  1240. select ARM64
  1241. select ARCH_SUPPORT_TFABOOT
  1242. select BOARD_LATE_INIT
  1243. imply SCSI
  1244. imply SCSI_AHCI
  1245. help
  1246. Support for Freescale LS1012AFRWY platform.
  1247. The LS1012A FRWY board (FRWY) is a high-performance
  1248. development platform that supports the QorIQ LS1012A
  1249. Layerscape Architecture processor.
  1250. config TARGET_LS1012AFRDM
  1251. bool "Support ls1012afrdm"
  1252. select ARCH_LS1012A
  1253. select ARM64
  1254. select ARCH_SUPPORT_TFABOOT
  1255. help
  1256. Support for Freescale LS1012AFRDM platform.
  1257. The LS1012A Freedom board (FRDM) is a high-performance
  1258. development platform that supports the QorIQ LS1012A
  1259. Layerscape Architecture processor.
  1260. config TARGET_LS1028AQDS
  1261. bool "Support ls1028aqds"
  1262. select ARCH_LS1028A
  1263. select ARM64
  1264. select ARMV8_MULTIENTRY
  1265. select ARCH_SUPPORT_TFABOOT
  1266. select BOARD_LATE_INIT
  1267. help
  1268. Support for Freescale LS1028AQDS platform
  1269. The LS1028A Development System (QDS) is a high-performance
  1270. development platform that supports the QorIQ LS1028A
  1271. Layerscape Architecture processor.
  1272. config TARGET_LS1028ARDB
  1273. bool "Support ls1028ardb"
  1274. select ARCH_LS1028A
  1275. select ARM64
  1276. select ARMV8_MULTIENTRY
  1277. select ARCH_SUPPORT_TFABOOT
  1278. select BOARD_LATE_INIT
  1279. help
  1280. Support for Freescale LS1028ARDB platform
  1281. The LS1028A Development System (RDB) is a high-performance
  1282. development platform that supports the QorIQ LS1028A
  1283. Layerscape Architecture processor.
  1284. config TARGET_LS1088ARDB
  1285. bool "Support ls1088ardb"
  1286. select ARCH_LS1088A
  1287. select ARM64
  1288. select ARMV8_MULTIENTRY
  1289. select ARCH_SUPPORT_TFABOOT
  1290. select BOARD_LATE_INIT
  1291. select SUPPORT_SPL
  1292. select FSL_DDR_INTERACTIVE if !SD_BOOT
  1293. help
  1294. Support for NXP LS1088ARDB platform.
  1295. The LS1088A Reference design board (RDB) is a high-performance
  1296. development platform that supports the QorIQ LS1088A
  1297. Layerscape Architecture processor.
  1298. config TARGET_LS1021AQDS
  1299. bool "Support ls1021aqds"
  1300. select ARCH_LS1021A
  1301. select ARCH_SUPPORT_PSCI
  1302. select BOARD_EARLY_INIT_F
  1303. select BOARD_LATE_INIT
  1304. select CPU_V7A
  1305. select CPU_V7_HAS_NONSEC
  1306. select CPU_V7_HAS_VIRT
  1307. select LS1_DEEP_SLEEP
  1308. select SUPPORT_SPL
  1309. select SYS_FSL_DDR
  1310. select FSL_DDR_INTERACTIVE
  1311. select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
  1312. select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
  1313. imply SCSI
  1314. config TARGET_LS1021ATWR
  1315. bool "Support ls1021atwr"
  1316. select ARCH_LS1021A
  1317. select ARCH_SUPPORT_PSCI
  1318. select BOARD_EARLY_INIT_F
  1319. select BOARD_LATE_INIT
  1320. select CPU_V7A
  1321. select CPU_V7_HAS_NONSEC
  1322. select CPU_V7_HAS_VIRT
  1323. select LS1_DEEP_SLEEP
  1324. select SUPPORT_SPL
  1325. select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
  1326. imply SCSI
  1327. config TARGET_LS1021ATSN
  1328. bool "Support ls1021atsn"
  1329. select ARCH_LS1021A
  1330. select ARCH_SUPPORT_PSCI
  1331. select BOARD_EARLY_INIT_F
  1332. select BOARD_LATE_INIT
  1333. select CPU_V7A
  1334. select CPU_V7_HAS_NONSEC
  1335. select CPU_V7_HAS_VIRT
  1336. select LS1_DEEP_SLEEP
  1337. select SUPPORT_SPL
  1338. imply SCSI
  1339. config TARGET_LS1021AIOT
  1340. bool "Support ls1021aiot"
  1341. select ARCH_LS1021A
  1342. select ARCH_SUPPORT_PSCI
  1343. select BOARD_LATE_INIT
  1344. select CPU_V7A
  1345. select CPU_V7_HAS_NONSEC
  1346. select CPU_V7_HAS_VIRT
  1347. select SUPPORT_SPL
  1348. select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
  1349. imply SCSI
  1350. help
  1351. Support for Freescale LS1021AIOT platform.
  1352. The LS1021A Freescale board (IOT) is a high-performance
  1353. development platform that supports the QorIQ LS1021A
  1354. Layerscape Architecture processor.
  1355. config TARGET_LS1043AQDS
  1356. bool "Support ls1043aqds"
  1357. select ARCH_LS1043A
  1358. select ARM64
  1359. select ARMV8_MULTIENTRY
  1360. select ARCH_SUPPORT_TFABOOT
  1361. select BOARD_EARLY_INIT_F
  1362. select BOARD_LATE_INIT
  1363. select SUPPORT_SPL
  1364. select FSL_DDR_INTERACTIVE if !SPL
  1365. select FSL_DSPI if !SPL_NO_DSPI
  1366. select DM_SPI_FLASH if FSL_DSPI
  1367. imply SCSI
  1368. imply SCSI_AHCI
  1369. help
  1370. Support for Freescale LS1043AQDS platform.
  1371. config TARGET_LS1043ARDB
  1372. bool "Support ls1043ardb"
  1373. select ARCH_LS1043A
  1374. select ARM64
  1375. select ARMV8_MULTIENTRY
  1376. select ARCH_SUPPORT_TFABOOT
  1377. select BOARD_EARLY_INIT_F
  1378. select BOARD_LATE_INIT
  1379. select SUPPORT_SPL
  1380. select FSL_DSPI if !SPL_NO_DSPI
  1381. select DM_SPI_FLASH if FSL_DSPI
  1382. help
  1383. Support for Freescale LS1043ARDB platform.
  1384. config TARGET_LS1046AQDS
  1385. bool "Support ls1046aqds"
  1386. select ARCH_LS1046A
  1387. select ARM64
  1388. select ARMV8_MULTIENTRY
  1389. select ARCH_SUPPORT_TFABOOT
  1390. select BOARD_EARLY_INIT_F
  1391. select BOARD_LATE_INIT
  1392. select DM_SPI_FLASH if DM_SPI
  1393. select SUPPORT_SPL
  1394. select FSL_DDR_BIST if !SPL
  1395. select FSL_DDR_INTERACTIVE if !SPL
  1396. select FSL_DDR_INTERACTIVE if !SPL
  1397. imply SCSI
  1398. help
  1399. Support for Freescale LS1046AQDS platform.
  1400. The LS1046A Development System (QDS) is a high-performance
  1401. development platform that supports the QorIQ LS1046A
  1402. Layerscape Architecture processor.
  1403. config TARGET_LS1046ARDB
  1404. bool "Support ls1046ardb"
  1405. select ARCH_LS1046A
  1406. select ARM64
  1407. select ARMV8_MULTIENTRY
  1408. select ARCH_SUPPORT_TFABOOT
  1409. select BOARD_EARLY_INIT_F
  1410. select BOARD_LATE_INIT
  1411. select DM_SPI_FLASH if DM_SPI
  1412. select POWER_MC34VR500
  1413. select SUPPORT_SPL
  1414. select FSL_DDR_BIST
  1415. select FSL_DDR_INTERACTIVE if !SPL
  1416. imply SCSI
  1417. help
  1418. Support for Freescale LS1046ARDB platform.
  1419. The LS1046A Reference Design Board (RDB) is a high-performance
  1420. development platform that supports the QorIQ LS1046A
  1421. Layerscape Architecture processor.
  1422. config TARGET_LS1046AFRWY
  1423. bool "Support ls1046afrwy"
  1424. select ARCH_LS1046A
  1425. select ARM64
  1426. select ARMV8_MULTIENTRY
  1427. select ARCH_SUPPORT_TFABOOT
  1428. select BOARD_EARLY_INIT_F
  1429. select BOARD_LATE_INIT
  1430. select DM_SPI_FLASH if DM_SPI
  1431. imply SCSI
  1432. help
  1433. Support for Freescale LS1046AFRWY platform.
  1434. The LS1046A Freeway Board (FRWY) is a high-performance
  1435. development platform that supports the QorIQ LS1046A
  1436. Layerscape Architecture processor.
  1437. config TARGET_SL28
  1438. bool "Support sl28"
  1439. select ARCH_LS1028A
  1440. select ARM64
  1441. select ARMV8_MULTIENTRY
  1442. select SUPPORT_SPL
  1443. select BINMAN
  1444. help
  1445. Support for Kontron SMARC-sAL28 board.
  1446. config TARGET_COLIBRI_PXA270
  1447. bool "Support colibri_pxa270"
  1448. select CPU_PXA
  1449. config ARCH_UNIPHIER
  1450. bool "Socionext UniPhier SoCs"
  1451. select BOARD_LATE_INIT
  1452. select DM
  1453. select DM_ETH
  1454. select DM_GPIO
  1455. select DM_I2C
  1456. select DM_MMC
  1457. select DM_MTD
  1458. select DM_RESET
  1459. select DM_SERIAL
  1460. select DM_USB
  1461. select OF_BOARD_SETUP
  1462. select OF_CONTROL
  1463. select OF_LIBFDT
  1464. select PINCTRL
  1465. select SPL_BOARD_INIT if SPL
  1466. select SPL_DM if SPL
  1467. select SPL_LIBCOMMON_SUPPORT if SPL
  1468. select SPL_LIBGENERIC_SUPPORT if SPL
  1469. select SPL_OF_CONTROL if SPL
  1470. select SPL_PINCTRL if SPL
  1471. select SUPPORT_SPL
  1472. imply CMD_DM
  1473. imply DISTRO_DEFAULTS
  1474. imply FAT_WRITE
  1475. help
  1476. Support for UniPhier SoC family developed by Socionext Inc.
  1477. (formerly, System LSI Business Division of Panasonic Corporation)
  1478. config ARCH_STM32
  1479. bool "Support STMicroelectronics STM32 MCU with cortex M"
  1480. select CPU_V7M
  1481. select DM
  1482. select DM_SERIAL
  1483. imply CMD_DM
  1484. config ARCH_STI
  1485. bool "Support STMicrolectronics SoCs"
  1486. select BLK
  1487. select CPU_V7A
  1488. select DM
  1489. select DM_MMC
  1490. select DM_RESET
  1491. select DM_SERIAL
  1492. imply CMD_DM
  1493. help
  1494. Support for STMicroelectronics STiH407/10 SoC family.
  1495. This SoC is used on Linaro 96Board STiH410-B2260
  1496. config ARCH_STM32MP
  1497. bool "Support STMicroelectronics STM32MP Socs with cortex A"
  1498. select ARCH_MISC_INIT
  1499. select ARCH_SUPPORT_TFABOOT
  1500. select BOARD_LATE_INIT
  1501. select CLK
  1502. select DM
  1503. select DM_GPIO
  1504. select DM_RESET
  1505. select DM_SERIAL
  1506. select MISC
  1507. select OF_CONTROL
  1508. select OF_LIBFDT
  1509. select OF_SYSTEM_SETUP
  1510. select PINCTRL
  1511. select REGMAP
  1512. select SUPPORT_SPL
  1513. select SYSCON
  1514. select SYSRESET
  1515. select SYS_THUMB_BUILD
  1516. imply SPL_SYSRESET
  1517. imply CMD_DM
  1518. imply CMD_POWEROFF
  1519. imply OF_LIBFDT_OVERLAY
  1520. imply ENV_VARS_UBOOT_RUNTIME_CONFIG
  1521. imply USE_PREBOOT
  1522. help
  1523. Support for STM32MP SoC family developed by STMicroelectronics,
  1524. MPUs based on ARM cortex A core
  1525. U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
  1526. FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
  1527. chain.
  1528. SPL is the unsecure FSBL for the basic boot chain.
  1529. config ARCH_ROCKCHIP
  1530. bool "Support Rockchip SoCs"
  1531. select BLK
  1532. select BINMAN if SPL_OPTEE
  1533. select DM
  1534. select DM_GPIO
  1535. select DM_I2C
  1536. select DM_MMC
  1537. select DM_PWM
  1538. select DM_REGULATOR
  1539. select DM_SERIAL
  1540. select DM_SPI
  1541. select DM_SPI_FLASH
  1542. select DM_USB if USB
  1543. select ENABLE_ARM_SOC_BOOT0_HOOK
  1544. select OF_CONTROL
  1545. select SPI
  1546. select SPL_DM if SPL
  1547. select SPL_DM_SPI if SPL
  1548. select SPL_DM_SPI_FLASH if SPL
  1549. select SYS_MALLOC_F
  1550. select SYS_THUMB_BUILD if !ARM64
  1551. imply ADC
  1552. imply CMD_DM
  1553. imply DEBUG_UART_BOARD_INIT
  1554. imply DISTRO_DEFAULTS
  1555. imply FAT_WRITE
  1556. imply SARADC_ROCKCHIP
  1557. imply SPL_SYSRESET
  1558. imply SPL_SYS_MALLOC_SIMPLE
  1559. imply SYS_NS16550
  1560. imply TPL_SYSRESET
  1561. imply USB_FUNCTION_FASTBOOT
  1562. config ARCH_OCTEONTX
  1563. bool "Support OcteonTX SoCs"
  1564. select CLK
  1565. select DM
  1566. select ARM64
  1567. select OF_CONTROL
  1568. select OF_LIVE
  1569. select BOARD_LATE_INIT
  1570. select SYS_CACHE_SHIFT_7
  1571. config ARCH_OCTEONTX2
  1572. bool "Support OcteonTX2 SoCs"
  1573. select CLK
  1574. select DM
  1575. select ARM64
  1576. select OF_CONTROL
  1577. select OF_LIVE
  1578. select BOARD_LATE_INIT
  1579. select SYS_CACHE_SHIFT_7
  1580. config TARGET_THUNDERX_88XX
  1581. bool "Support ThunderX 88xx"
  1582. select ARM64
  1583. select OF_CONTROL
  1584. select PL01X_SERIAL
  1585. select SYS_CACHE_SHIFT_7
  1586. config ARCH_ASPEED
  1587. bool "Support Aspeed SoCs"
  1588. select DM
  1589. select OF_CONTROL
  1590. imply CMD_DM
  1591. config TARGET_DURIAN
  1592. bool "Support Phytium Durian Platform"
  1593. select ARM64
  1594. help
  1595. Support for durian platform.
  1596. It has 2GB Sdram, uart and pcie.
  1597. config TARGET_PRESIDIO_ASIC
  1598. bool "Support Cortina Presidio ASIC Platform"
  1599. select ARM64
  1600. config TARGET_XENGUEST_ARM64
  1601. bool "Xen guest ARM64"
  1602. select ARM64
  1603. select XEN
  1604. select OF_CONTROL
  1605. select LINUX_KERNEL_IMAGE_HEADER
  1606. select XEN_SERIAL
  1607. select SSCANF
  1608. endchoice
  1609. config ARCH_SUPPORT_TFABOOT
  1610. bool
  1611. config TFABOOT
  1612. bool "Support for booting from TF-A"
  1613. depends on ARCH_SUPPORT_TFABOOT
  1614. default n
  1615. help
  1616. Some platforms support the setup of secure registers (for instance
  1617. for CPU errata handling) or provide secure services like PSCI.
  1618. Those services could also be provided by other firmware parts
  1619. like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
  1620. does not need to (and cannot) execute this code.
  1621. Enabling this option will make a U-Boot binary that is relying
  1622. on other firmware layers to provide secure functionality.
  1623. config TI_SECURE_DEVICE
  1624. bool "HS Device Type Support"
  1625. depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
  1626. help
  1627. If a high secure (HS) device type is being used, this config
  1628. must be set. This option impacts various aspects of the
  1629. build system (to create signed boot images that can be
  1630. authenticated) and the code. See the doc/README.ti-secure
  1631. file for further details.
  1632. if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
  1633. config ISW_ENTRY_ADDR
  1634. hex "Address in memory or XIP address of bootloader entry point"
  1635. default 0x402F4000 if AM43XX
  1636. default 0x402F0400 if AM33XX
  1637. default 0x40301350 if OMAP54XX
  1638. help
  1639. After any reset, the boot ROM searches the boot media for a valid
  1640. boot image. For non-XIP devices, the ROM then copies the image into
  1641. internal memory. For all boot modes, after the ROM processes the
  1642. boot image it eventually computes the entry point address depending
  1643. on the device type (secure/non-secure), boot media (xip/non-xip) and
  1644. image headers.
  1645. endif
  1646. source "arch/arm/mach-aspeed/Kconfig"
  1647. source "arch/arm/mach-at91/Kconfig"
  1648. source "arch/arm/mach-bcm283x/Kconfig"
  1649. source "arch/arm/mach-bcmstb/Kconfig"
  1650. source "arch/arm/mach-davinci/Kconfig"
  1651. source "arch/arm/mach-exynos/Kconfig"
  1652. source "arch/arm/mach-highbank/Kconfig"
  1653. source "arch/arm/mach-integrator/Kconfig"
  1654. source "arch/arm/mach-ipq40xx/Kconfig"
  1655. source "arch/arm/mach-k3/Kconfig"
  1656. source "arch/arm/mach-keystone/Kconfig"
  1657. source "arch/arm/mach-kirkwood/Kconfig"
  1658. source "arch/arm/mach-lpc32xx/Kconfig"
  1659. source "arch/arm/mach-mvebu/Kconfig"
  1660. source "arch/arm/mach-octeontx/Kconfig"
  1661. source "arch/arm/mach-octeontx2/Kconfig"
  1662. source "arch/arm/cpu/armv7/ls102xa/Kconfig"
  1663. source "arch/arm/mach-imx/mx2/Kconfig"
  1664. source "arch/arm/mach-imx/mx3/Kconfig"
  1665. source "arch/arm/mach-imx/mx5/Kconfig"
  1666. source "arch/arm/mach-imx/mx6/Kconfig"
  1667. source "arch/arm/mach-imx/mx7/Kconfig"
  1668. source "arch/arm/mach-imx/mx7ulp/Kconfig"
  1669. source "arch/arm/mach-imx/imx8/Kconfig"
  1670. source "arch/arm/mach-imx/imx8m/Kconfig"
  1671. source "arch/arm/mach-imx/imxrt/Kconfig"
  1672. source "arch/arm/mach-imx/mxs/Kconfig"
  1673. source "arch/arm/mach-omap2/Kconfig"
  1674. source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
  1675. source "arch/arm/mach-orion5x/Kconfig"
  1676. source "arch/arm/mach-owl/Kconfig"
  1677. source "arch/arm/mach-rmobile/Kconfig"
  1678. source "arch/arm/mach-meson/Kconfig"
  1679. source "arch/arm/mach-mediatek/Kconfig"
  1680. source "arch/arm/mach-qemu/Kconfig"
  1681. source "arch/arm/mach-rockchip/Kconfig"
  1682. source "arch/arm/mach-s5pc1xx/Kconfig"
  1683. source "arch/arm/mach-snapdragon/Kconfig"
  1684. source "arch/arm/mach-socfpga/Kconfig"
  1685. source "arch/arm/mach-sti/Kconfig"
  1686. source "arch/arm/mach-stm32/Kconfig"
  1687. source "arch/arm/mach-stm32mp/Kconfig"
  1688. source "arch/arm/mach-sunxi/Kconfig"
  1689. source "arch/arm/mach-tegra/Kconfig"
  1690. source "arch/arm/mach-u8500/Kconfig"
  1691. source "arch/arm/mach-uniphier/Kconfig"
  1692. source "arch/arm/cpu/armv7/vf610/Kconfig"
  1693. source "arch/arm/mach-zynq/Kconfig"
  1694. source "arch/arm/mach-zynqmp/Kconfig"
  1695. source "arch/arm/mach-versal/Kconfig"
  1696. source "arch/arm/mach-zynqmp-r5/Kconfig"
  1697. source "arch/arm/cpu/armv7/Kconfig"
  1698. source "arch/arm/cpu/armv8/Kconfig"
  1699. source "arch/arm/mach-imx/Kconfig"
  1700. source "arch/arm/mach-nexell/Kconfig"
  1701. source "board/armltd/total_compute/Kconfig"
  1702. source "board/bosch/shc/Kconfig"
  1703. source "board/bosch/guardian/Kconfig"
  1704. source "board/CarMediaLab/flea3/Kconfig"
  1705. source "board/Marvell/aspenite/Kconfig"
  1706. source "board/Marvell/gplugd/Kconfig"
  1707. source "board/Marvell/octeontx/Kconfig"
  1708. source "board/Marvell/octeontx2/Kconfig"
  1709. source "board/armadeus/apf27/Kconfig"
  1710. source "board/armltd/vexpress/Kconfig"
  1711. source "board/armltd/vexpress64/Kconfig"
  1712. source "board/cortina/presidio-asic/Kconfig"
  1713. source "board/broadcom/bcm23550_w1d/Kconfig"
  1714. source "board/broadcom/bcm28155_ap/Kconfig"
  1715. source "board/broadcom/bcm963158/Kconfig"
  1716. source "board/broadcom/bcm968360bg/Kconfig"
  1717. source "board/broadcom/bcm968580xref/Kconfig"
  1718. source "board/broadcom/bcmcygnus/Kconfig"
  1719. source "board/broadcom/bcmnsp/Kconfig"
  1720. source "board/broadcom/bcmns2/Kconfig"
  1721. source "board/broadcom/bcmns3/Kconfig"
  1722. source "board/cavium/thunderx/Kconfig"
  1723. source "board/cirrus/edb93xx/Kconfig"
  1724. source "board/eets/pdu001/Kconfig"
  1725. source "board/emulation/qemu-arm/Kconfig"
  1726. source "board/freescale/ls2080aqds/Kconfig"
  1727. source "board/freescale/ls2080ardb/Kconfig"
  1728. source "board/freescale/ls1088a/Kconfig"
  1729. source "board/freescale/ls1028a/Kconfig"
  1730. source "board/freescale/ls1021aqds/Kconfig"
  1731. source "board/freescale/ls1043aqds/Kconfig"
  1732. source "board/freescale/ls1021atwr/Kconfig"
  1733. source "board/freescale/ls1021atsn/Kconfig"
  1734. source "board/freescale/ls1021aiot/Kconfig"
  1735. source "board/freescale/ls1046aqds/Kconfig"
  1736. source "board/freescale/ls1043ardb/Kconfig"
  1737. source "board/freescale/ls1046ardb/Kconfig"
  1738. source "board/freescale/ls1046afrwy/Kconfig"
  1739. source "board/freescale/ls1012aqds/Kconfig"
  1740. source "board/freescale/ls1012ardb/Kconfig"
  1741. source "board/freescale/ls1012afrdm/Kconfig"
  1742. source "board/freescale/lx2160a/Kconfig"
  1743. source "board/freescale/s32v234evb/Kconfig"
  1744. source "board/grinn/chiliboard/Kconfig"
  1745. source "board/hisilicon/hikey/Kconfig"
  1746. source "board/hisilicon/hikey960/Kconfig"
  1747. source "board/hisilicon/poplar/Kconfig"
  1748. source "board/isee/igep003x/Kconfig"
  1749. source "board/kontron/sl28/Kconfig"
  1750. source "board/myir/mys_6ulx/Kconfig"
  1751. source "board/spear/spear300/Kconfig"
  1752. source "board/spear/spear310/Kconfig"
  1753. source "board/spear/spear320/Kconfig"
  1754. source "board/spear/spear600/Kconfig"
  1755. source "board/spear/x600/Kconfig"
  1756. source "board/st/stv0991/Kconfig"
  1757. source "board/tcl/sl50/Kconfig"
  1758. source "board/toradex/colibri_pxa270/Kconfig"
  1759. source "board/variscite/dart_6ul/Kconfig"
  1760. source "board/vscom/baltos/Kconfig"
  1761. source "board/phytium/durian/Kconfig"
  1762. source "board/xen/xenguest_arm64/Kconfig"
  1763. source "arch/arm/Kconfig.debug"
  1764. endmenu
  1765. config SPL_LDSCRIPT
  1766. default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
  1767. default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
  1768. default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64