p5040_serdes.c 4.0 KB

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  1. /*
  2. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/fsl_serdes.h>
  8. #include <asm/processor.h>
  9. #include <asm/io.h>
  10. #include "fsl_corenet_serdes.h"
  11. /*
  12. * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
  13. * U-Boot only supports one SerDes controller. Therefore, we ignore bank 4 in
  14. * this table. This works because most of the SerDes code is for errata
  15. * work-arounds, and there are no P5040 errata that effect bank 4.
  16. */
  17. static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
  18. [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
  19. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
  20. SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  21. XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
  22. [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
  23. SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
  24. XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
  25. XAUI_FM2, /* SATA1, SATA2 */ },
  26. [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
  27. SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
  28. XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
  29. XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
  30. [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
  31. SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
  32. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
  33. SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
  34. /* SATA1, SATA2 */ },
  35. [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
  36. SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
  37. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
  38. SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
  39. /* SATA1, SATA2 */ },
  40. [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
  41. SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
  42. XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
  43. XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
  44. [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
  45. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
  46. SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  47. XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
  48. [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
  49. SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
  50. XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
  51. XAUI_FM2, /* SATA1, SATA2 */ },
  52. [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
  53. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  54. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
  55. /* NONE, NONE */ },
  56. [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
  57. AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
  58. NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
  59. [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
  60. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  61. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
  62. XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
  63. [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
  64. SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
  65. AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
  66. NONE, SATA1, SATA2, /* NONE, NONE */ },
  67. [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
  68. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
  69. XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
  70. /* NONE, NONE */ },
  71. [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
  72. SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
  73. AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
  74. NONE, SATA1, SATA2, /* NONE, NONE */ },
  75. };
  76. enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
  77. {
  78. if (!serdes_lane_enabled(lane))
  79. return NONE;
  80. return serdes_cfg_tbl[cfg][lane];
  81. }
  82. int is_serdes_prtcl_valid(u32 prtcl)
  83. {
  84. int i;
  85. if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
  86. return 0;
  87. for (i = 0; i < SRDS_MAX_LANES; i++) {
  88. if (serdes_cfg_tbl[prtcl][i] != NONE)
  89. return 1;
  90. }
  91. return 0;
  92. }