spl.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Copyright 2014 Freescale Semiconductor, Inc.
  3. */
  4. #include <common.h>
  5. #include <console.h>
  6. #include <env_internal.h>
  7. #include <asm/spl.h>
  8. #include <malloc.h>
  9. #include <ns16550.h>
  10. #include <nand.h>
  11. #include <mmc.h>
  12. #include <fsl_esdhc.h>
  13. #include <i2c.h>
  14. #include "../common/qixis.h"
  15. #include "t4240qds_qixis.h"
  16. #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
  17. DECLARE_GLOBAL_DATA_PTR;
  18. phys_size_t get_effective_memsize(void)
  19. {
  20. return CONFIG_SYS_L3_SIZE;
  21. }
  22. unsigned long get_board_sys_clk(void)
  23. {
  24. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  25. switch (sysclk_conf & 0x0F) {
  26. case QIXIS_SYSCLK_83:
  27. return 83333333;
  28. case QIXIS_SYSCLK_100:
  29. return 100000000;
  30. case QIXIS_SYSCLK_125:
  31. return 125000000;
  32. case QIXIS_SYSCLK_133:
  33. return 133333333;
  34. case QIXIS_SYSCLK_150:
  35. return 150000000;
  36. case QIXIS_SYSCLK_160:
  37. return 160000000;
  38. case QIXIS_SYSCLK_166:
  39. return 166666666;
  40. }
  41. return 66666666;
  42. }
  43. unsigned long get_board_ddr_clk(void)
  44. {
  45. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  46. switch ((ddrclk_conf & 0x30) >> 4) {
  47. case QIXIS_DDRCLK_100:
  48. return 100000000;
  49. case QIXIS_DDRCLK_125:
  50. return 125000000;
  51. case QIXIS_DDRCLK_133:
  52. return 133333333;
  53. }
  54. return 66666666;
  55. }
  56. void board_init_f(ulong bootflag)
  57. {
  58. u32 plat_ratio, sys_clk, ccb_clk;
  59. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  60. #ifdef CONFIG_SPL_NAND_BOOT
  61. u32 porsr1, pinctl;
  62. #endif
  63. #ifdef CONFIG_SPL_NAND_BOOT
  64. porsr1 = in_be32(&gur->porsr1);
  65. pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
  66. out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
  67. #endif
  68. /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  69. memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  70. /* Update GD pointer */
  71. gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  72. /* compiler optimization barrier needed for GCC >= 3.4 */
  73. __asm__ __volatile__("" : : : "memory");
  74. console_init_f();
  75. /* initialize selected port with appropriate baud rate */
  76. sys_clk = get_board_sys_clk();
  77. plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  78. ccb_clk = sys_clk * plat_ratio / 2;
  79. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  80. ccb_clk / 16 / CONFIG_BAUDRATE);
  81. #ifdef CONFIG_SPL_MMC_BOOT
  82. puts("\nSD boot...\n");
  83. #elif defined(CONFIG_SPL_NAND_BOOT)
  84. puts("\nNAND boot...\n");
  85. #endif
  86. relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
  87. }
  88. void board_init_r(gd_t *gd, ulong dest_addr)
  89. {
  90. bd_t *bd;
  91. bd = (bd_t *)(gd + sizeof(gd_t));
  92. memset(bd, 0, sizeof(bd_t));
  93. gd->bd = bd;
  94. bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
  95. bd->bi_memsize = CONFIG_SYS_L3_SIZE;
  96. arch_cpu_init();
  97. get_clocks();
  98. mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  99. CONFIG_SPL_RELOC_MALLOC_SIZE);
  100. gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  101. #ifdef CONFIG_SPL_NAND_BOOT
  102. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  103. (uchar *)SPL_ENV_ADDR);
  104. #endif
  105. #ifdef CONFIG_SPL_MMC_BOOT
  106. mmc_initialize(bd);
  107. mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  108. (uchar *)SPL_ENV_ADDR);
  109. #endif
  110. gd->env_addr = (ulong)(SPL_ENV_ADDR);
  111. gd->env_valid = ENV_VALID;
  112. i2c_init_all();
  113. dram_init();
  114. #ifdef CONFIG_SPL_MMC_BOOT
  115. mmc_boot();
  116. #elif defined(CONFIG_SPL_NAND_BOOT)
  117. nand_boot();
  118. #endif
  119. }