spl.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Copyright 2013 Freescale Semiconductor, Inc.
  3. */
  4. #include <common.h>
  5. #include <console.h>
  6. #include <env_internal.h>
  7. #include <malloc.h>
  8. #include <ns16550.h>
  9. #include <nand.h>
  10. #include <i2c.h>
  11. #include <mmc.h>
  12. #include <fsl_esdhc.h>
  13. #include <spi_flash.h>
  14. #include "../common/sleep.h"
  15. #include "../common/spl.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. phys_size_t get_effective_memsize(void)
  18. {
  19. return CONFIG_SYS_L3_SIZE;
  20. }
  21. unsigned long get_board_sys_clk(void)
  22. {
  23. return CONFIG_SYS_CLK_FREQ;
  24. }
  25. unsigned long get_board_ddr_clk(void)
  26. {
  27. return CONFIG_DDR_CLK_FREQ;
  28. }
  29. #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
  30. void board_init_f(ulong bootflag)
  31. {
  32. u32 plat_ratio, sys_clk, uart_clk;
  33. #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
  34. u32 porsr1, pinctl;
  35. u32 svr = get_svr();
  36. #endif
  37. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  38. #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
  39. if (IS_SVR_REV(svr, 1, 0)) {
  40. /*
  41. * There is T1040 SoC issue where NOR, FPGA are inaccessible
  42. * during NAND boot because IFC signals > IFC_AD7 are not
  43. * enabled. This workaround changes RCW source to make all
  44. * signals enabled.
  45. */
  46. porsr1 = in_be32(&gur->porsr1);
  47. pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
  48. | 0x24800000);
  49. out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
  50. pinctl);
  51. }
  52. #endif
  53. /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  54. memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  55. /* Update GD pointer */
  56. gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  57. #ifdef CONFIG_DEEP_SLEEP
  58. /* disable the console if boot from deep sleep */
  59. if (is_warm_boot())
  60. fsl_dp_disable_console();
  61. #endif
  62. /* compiler optimization barrier needed for GCC >= 3.4 */
  63. __asm__ __volatile__("" : : : "memory");
  64. console_init_f();
  65. /* initialize selected port with appropriate baud rate */
  66. sys_clk = get_board_sys_clk();
  67. plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  68. uart_clk = sys_clk * plat_ratio / 2;
  69. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  70. uart_clk / 16 / CONFIG_BAUDRATE);
  71. relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
  72. }
  73. void board_init_r(gd_t *gd, ulong dest_addr)
  74. {
  75. bd_t *bd;
  76. bd = (bd_t *)(gd + sizeof(gd_t));
  77. memset(bd, 0, sizeof(bd_t));
  78. gd->bd = bd;
  79. bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
  80. bd->bi_memsize = CONFIG_SYS_L3_SIZE;
  81. arch_cpu_init();
  82. get_clocks();
  83. mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  84. CONFIG_SPL_RELOC_MALLOC_SIZE);
  85. gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  86. #ifdef CONFIG_SPL_MMC_BOOT
  87. mmc_initialize(bd);
  88. #endif
  89. /* relocate environment function pointers etc. */
  90. #if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \
  91. defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  92. #ifdef CONFIG_SPL_NAND_BOOT
  93. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  94. (uchar *)SPL_ENV_ADDR);
  95. #endif
  96. #ifdef CONFIG_SPL_MMC_BOOT
  97. mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  98. (uchar *)SPL_ENV_ADDR);
  99. #endif
  100. #ifdef CONFIG_SPL_SPI_BOOT
  101. fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  102. (uchar *)SPL_ENV_ADDR);
  103. #endif
  104. gd->env_addr = (ulong)(SPL_ENV_ADDR);
  105. gd->env_valid = ENV_VALID;
  106. #endif
  107. i2c_init_all();
  108. puts("\n\n");
  109. dram_init();
  110. #ifdef CONFIG_SPL_MMC_BOOT
  111. mmc_boot();
  112. #elif defined(CONFIG_SPL_SPI_BOOT)
  113. fsl_spi_boot();
  114. #elif defined(CONFIG_SPL_NAND_BOOT)
  115. nand_boot();
  116. #endif
  117. }