spl.c 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <console.h>
  7. #include <env.h>
  8. #include <env_internal.h>
  9. #include <ns16550.h>
  10. #include <malloc.h>
  11. #include <mmc.h>
  12. #include <nand.h>
  13. #include <i2c.h>
  14. #include "../common/ngpixis.h"
  15. #include <fsl_esdhc.h>
  16. #include <spi_flash.h>
  17. #include "../common/spl.h"
  18. DECLARE_GLOBAL_DATA_PTR;
  19. static const u32 sysclk_tbl[] = {
  20. 66666000, 7499900, 83332500, 8999900,
  21. 99999000, 11111000, 12499800, 13333200
  22. };
  23. phys_size_t get_effective_memsize(void)
  24. {
  25. return CONFIG_SYS_L2_SIZE;
  26. }
  27. void board_init_f(ulong bootflag)
  28. {
  29. int px_spd;
  30. u32 plat_ratio, sys_clk, bus_clk;
  31. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  32. console_init_f();
  33. /* Set pmuxcr to allow both i2c1 and i2c2 */
  34. setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
  35. setbits_be32(&gur->pmuxcr,
  36. in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
  37. #ifdef CONFIG_SPL_SPI_BOOT
  38. /* Enable the SPI */
  39. clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
  40. #endif
  41. /* Read back the register to synchronize the write. */
  42. in_be32(&gur->pmuxcr);
  43. /* initialize selected port with appropriate baud rate */
  44. px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
  45. sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
  46. plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  47. bus_clk = sys_clk * plat_ratio / 2;
  48. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  49. bus_clk / 16 / CONFIG_BAUDRATE);
  50. #ifdef CONFIG_SPL_MMC_BOOT
  51. puts("\nSD boot...\n");
  52. #elif defined(CONFIG_SPL_SPI_BOOT)
  53. puts("\nSPI Flash boot...\n");
  54. #endif
  55. /* copy code to RAM and jump to it - this should not return */
  56. /* NOTE - code has to be copied out of NAND buffer before
  57. * other blocks can be read.
  58. */
  59. relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
  60. }
  61. void board_init_r(gd_t *gd, ulong dest_addr)
  62. {
  63. /* Pointer is writable since we allocated a register for it */
  64. gd = (gd_t *)CONFIG_SPL_GD_ADDR;
  65. bd_t *bd;
  66. memset(gd, 0, sizeof(gd_t));
  67. bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
  68. memset(bd, 0, sizeof(bd_t));
  69. gd->bd = bd;
  70. bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
  71. bd->bi_memsize = CONFIG_SYS_L2_SIZE;
  72. arch_cpu_init();
  73. get_clocks();
  74. mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  75. CONFIG_SPL_RELOC_MALLOC_SIZE);
  76. gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  77. #ifndef CONFIG_SPL_NAND_BOOT
  78. env_init();
  79. #endif
  80. #ifdef CONFIG_SPL_MMC_BOOT
  81. mmc_initialize(bd);
  82. #endif
  83. /* relocate environment function pointers etc. */
  84. #ifdef CONFIG_SPL_NAND_BOOT
  85. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  86. (uchar *)SPL_ENV_ADDR);
  87. gd->env_addr = (ulong)(SPL_ENV_ADDR);
  88. gd->env_valid = ENV_VALID;
  89. #else
  90. env_relocate();
  91. #endif
  92. #ifdef CONFIG_SYS_I2C
  93. i2c_init_all();
  94. #else
  95. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  96. #endif
  97. dram_init();
  98. #ifdef CONFIG_SPL_NAND_BOOT
  99. puts("Tertiary program loader running in sram...");
  100. #else
  101. puts("Second program loader running in sram...\n");
  102. #endif
  103. #ifdef CONFIG_SPL_MMC_BOOT
  104. mmc_boot();
  105. #elif defined(CONFIG_SPL_SPI_BOOT)
  106. fsl_spi_boot();
  107. #elif defined(CONFIG_SPL_NAND_BOOT)
  108. nand_boot();
  109. #endif
  110. }