prelink-riscv.inc 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Andes Technology
  4. * Chih-Mao Chen <cmchen@andestech.com>
  5. *
  6. * Statically process runtime relocations on RISC-V ELF images
  7. * so that it can be directly executed when loaded at LMA
  8. * without fixup. Both RV32 and RV64 are supported.
  9. */
  10. #define CONCAT_IMPL(x, y) x##y
  11. #define CONCAT(x, y) CONCAT_IMPL(x, y)
  12. #define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)
  13. #define prelink_bonn CONCAT3(prelink_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
  14. #define uintnn_t CONCAT3(uint, PRELINK_INC_BITS, _t)
  15. #define get_offset_bonn CONCAT3(get_offset_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
  16. #define Elf_Ehdr CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
  17. #define Elf_Phdr CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
  18. #define Elf_Rela CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
  19. #define Elf_Sym CONCAT3(Elf, PRELINK_INC_BITS, _Sym)
  20. #define Elf_Dyn CONCAT3(Elf, PRELINK_INC_BITS, _Dyn)
  21. #define Elf_Addr CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
  22. #define ELF_R_TYPE CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
  23. #define ELF_R_SYM CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
  24. #define target16_to_cpu CONCAT(PRELINK_BYTEORDER, 16_to_cpu)
  25. #define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
  26. #define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
  27. #define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
  28. #define cpu_to_target32 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 32)
  29. #define cpu_to_target64 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 64)
  30. static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
  31. {
  32. Elf_Phdr *p;
  33. for (p = phdrs; p < phdrs + phnum; ++p)
  34. if (targetnn_to_cpu(p->p_vaddr) <= addr && targetnn_to_cpu(p->p_vaddr) + targetnn_to_cpu(p->p_memsz) > addr)
  35. return data + targetnn_to_cpu(p->p_offset) + (addr - targetnn_to_cpu(p->p_vaddr));
  36. return NULL;
  37. }
  38. static void prelink_bonn(void *data)
  39. {
  40. Elf_Ehdr *ehdr = data;
  41. Elf_Phdr *p;
  42. Elf_Dyn *dyn;
  43. Elf_Rela *r;
  44. if (target16_to_cpu(ehdr->e_machine) != EM_RISCV)
  45. die("Machine type is not RISC-V");
  46. Elf_Phdr *phdrs = data + targetnn_to_cpu(ehdr->e_phoff);
  47. Elf_Dyn *dyns = NULL;
  48. for (p = phdrs; p < phdrs + target16_to_cpu(ehdr->e_phnum); ++p) {
  49. if (target32_to_cpu(p->p_type) == PT_DYNAMIC) {
  50. dyns = data + targetnn_to_cpu(p->p_offset);
  51. break;
  52. }
  53. }
  54. if (dyns == NULL)
  55. die("No dynamic section found");
  56. Elf_Rela *rela_dyn = NULL;
  57. size_t rela_count = 0;
  58. Elf_Sym *dynsym = NULL;
  59. for (dyn = dyns;; ++dyn) {
  60. if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
  61. break;
  62. else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
  63. rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
  64. else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
  65. rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
  66. else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
  67. dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
  68. }
  69. if (rela_dyn == NULL)
  70. die("No .rela.dyn found");
  71. if (dynsym == NULL)
  72. die("No .dynsym found");
  73. for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
  74. void* buf = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), targetnn_to_cpu(r->r_offset));
  75. if (buf == NULL)
  76. continue;
  77. if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
  78. *((uintnn_t*) buf) = r->r_addend;
  79. else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
  80. *((uint32_t*) buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
  81. else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
  82. *((uint64_t*) buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
  83. }
  84. }
  85. #undef prelink_bonn
  86. #undef uintnn_t
  87. #undef get_offset_bonn
  88. #undef Elf_Ehdr
  89. #undef Elf_Phdr
  90. #undef Elf_Rela
  91. #undef Elf_Sym
  92. #undef Elf_Dyn
  93. #undef Elf_Addr
  94. #undef ELF_R_TYPE
  95. #undef ELF_R_SYM
  96. #undef target16_to_cpu
  97. #undef target32_to_cpu
  98. #undef target64_to_cpu
  99. #undef targetnn_to_cpu
  100. #undef cpu_to_target32
  101. #undef cpu_to_target64
  102. #undef CONCAT_IMPL
  103. #undef CONCAT
  104. #undef CONCAT3