kwbimage.h 6.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2008
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. */
  7. #ifndef _KWBIMAGE_H_
  8. #define _KWBIMAGE_H_
  9. #include <compiler.h>
  10. #include <stdint.h>
  11. #ifdef __GNUC__
  12. #define __packed __attribute((packed))
  13. #else
  14. #define __packed
  15. #endif
  16. #define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
  17. #define MAX_TEMPBUF_LEN 32
  18. /* NAND ECC Mode */
  19. #define IBR_HDR_ECC_DEFAULT 0x00
  20. #define IBR_HDR_ECC_FORCED_HAMMING 0x01
  21. #define IBR_HDR_ECC_FORCED_RS 0x02
  22. #define IBR_HDR_ECC_DISABLED 0x03
  23. /* Boot Type - block ID */
  24. #define IBR_HDR_I2C_ID 0x4D
  25. #define IBR_HDR_SPI_ID 0x5A
  26. #define IBR_HDR_NAND_ID 0x8B
  27. #define IBR_HDR_SATA_ID 0x78
  28. #define IBR_HDR_PEX_ID 0x9C
  29. #define IBR_HDR_UART_ID 0x69
  30. #define IBR_HDR_SDIO_ID 0xAE
  31. #define IBR_DEF_ATTRIB 0x00
  32. /* Structure of the main header, version 0 (Kirkwood, Dove) */
  33. struct main_hdr_v0 {
  34. uint8_t blockid; /* 0x0 */
  35. uint8_t nandeccmode; /* 0x1 */
  36. uint16_t nandpagesize; /* 0x2-0x3 */
  37. uint32_t blocksize; /* 0x4-0x7 */
  38. uint32_t rsvd1; /* 0x8-0xB */
  39. uint32_t srcaddr; /* 0xC-0xF */
  40. uint32_t destaddr; /* 0x10-0x13 */
  41. uint32_t execaddr; /* 0x14-0x17 */
  42. uint8_t satapiomode; /* 0x18 */
  43. uint8_t rsvd3; /* 0x19 */
  44. uint16_t ddrinitdelay; /* 0x1A-0x1B */
  45. uint16_t rsvd2; /* 0x1C-0x1D */
  46. uint8_t ext; /* 0x1E */
  47. uint8_t checksum; /* 0x1F */
  48. } __packed;
  49. struct ext_hdr_v0_reg {
  50. uint32_t raddr;
  51. uint32_t rdata;
  52. } __packed;
  53. #define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
  54. struct ext_hdr_v0 {
  55. uint32_t offset;
  56. uint8_t reserved[0x20 - sizeof(uint32_t)];
  57. struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
  58. uint8_t reserved2[7];
  59. uint8_t checksum;
  60. } __packed;
  61. struct kwb_header {
  62. struct main_hdr_v0 kwb_hdr;
  63. struct ext_hdr_v0 kwb_exthdr;
  64. } __packed;
  65. /* Structure of the main header, version 1 (Armada 370/38x/XP) */
  66. struct main_hdr_v1 {
  67. uint8_t blockid; /* 0x0 */
  68. uint8_t flags; /* 0x1 */
  69. uint16_t reserved2; /* 0x2-0x3 */
  70. uint32_t blocksize; /* 0x4-0x7 */
  71. uint8_t version; /* 0x8 */
  72. uint8_t headersz_msb; /* 0x9 */
  73. uint16_t headersz_lsb; /* 0xA-0xB */
  74. uint32_t srcaddr; /* 0xC-0xF */
  75. uint32_t destaddr; /* 0x10-0x13 */
  76. uint32_t execaddr; /* 0x14-0x17 */
  77. uint8_t options; /* 0x18 */
  78. uint8_t nandblocksize; /* 0x19 */
  79. uint8_t nandbadblklocation; /* 0x1A */
  80. uint8_t reserved4; /* 0x1B */
  81. uint16_t reserved5; /* 0x1C-0x1D */
  82. uint8_t ext; /* 0x1E */
  83. uint8_t checksum; /* 0x1F */
  84. } __packed;
  85. /*
  86. * Main header options
  87. */
  88. #define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
  89. #define MAIN_HDR_V1_OPT_BAUD_2400 0x1
  90. #define MAIN_HDR_V1_OPT_BAUD_4800 0x2
  91. #define MAIN_HDR_V1_OPT_BAUD_9600 0x3
  92. #define MAIN_HDR_V1_OPT_BAUD_19200 0x4
  93. #define MAIN_HDR_V1_OPT_BAUD_38400 0x5
  94. #define MAIN_HDR_V1_OPT_BAUD_57600 0x6
  95. #define MAIN_HDR_V1_OPT_BAUD_115200 0x7
  96. /*
  97. * Header for the optional headers, version 1 (Armada 370, Armada XP)
  98. */
  99. struct opt_hdr_v1 {
  100. uint8_t headertype;
  101. uint8_t headersz_msb;
  102. uint16_t headersz_lsb;
  103. char data[0];
  104. } __packed;
  105. /*
  106. * Public Key data in DER format
  107. */
  108. struct pubkey_der_v1 {
  109. uint8_t key[524];
  110. } __packed;
  111. /*
  112. * Signature (RSA 2048)
  113. */
  114. struct sig_v1 {
  115. uint8_t sig[256];
  116. } __packed;
  117. /*
  118. * Structure of secure header (Armada 38x)
  119. */
  120. struct secure_hdr_v1 {
  121. uint8_t headertype; /* 0x0 */
  122. uint8_t headersz_msb; /* 0x1 */
  123. uint16_t headersz_lsb; /* 0x2 - 0x3 */
  124. uint32_t reserved1; /* 0x4 - 0x7 */
  125. struct pubkey_der_v1 kak; /* 0x8 - 0x213 */
  126. uint8_t jtag_delay; /* 0x214 */
  127. uint8_t reserved2; /* 0x215 */
  128. uint16_t reserved3; /* 0x216 - 0x217 */
  129. uint32_t boxid; /* 0x218 - 0x21B */
  130. uint32_t flashid; /* 0x21C - 0x21F */
  131. struct sig_v1 hdrsig; /* 0x220 - 0x31F */
  132. struct sig_v1 imgsig; /* 0x320 - 0x41F */
  133. struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */
  134. struct sig_v1 csksig; /* 0x24E0 - 0x25DF */
  135. uint8_t next; /* 0x25E0 */
  136. uint8_t reserved4; /* 0x25E1 */
  137. uint16_t reserved5; /* 0x25E2 - 0x25E3 */
  138. } __packed;
  139. /*
  140. * Structure of register set
  141. */
  142. struct register_set_hdr_v1 {
  143. uint8_t headertype; /* 0x0 */
  144. uint8_t headersz_msb; /* 0x1 */
  145. uint16_t headersz_lsb; /* 0x2 - 0x3 */
  146. union {
  147. struct {
  148. uint32_t address; /* 0x4+8*N - 0x7+8*N */
  149. uint32_t value; /* 0x8+8*N - 0xB+8*N */
  150. } __packed entry;
  151. struct {
  152. uint8_t next; /* 0xC+8*N */
  153. uint8_t delay; /* 0xD+8*N */
  154. uint16_t reserved; /* 0xE+8*N - 0xF+8*N */
  155. } __packed last_entry;
  156. } data[];
  157. } __packed;
  158. /*
  159. * Value 0 in register_set_hdr_v1 delay field is special.
  160. * Instead of delay it setup SDRAM Controller.
  161. */
  162. #define REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP 0
  163. #define REGISTER_SET_HDR_OPT_DELAY_MS(val) ((val) ?: 1)
  164. /*
  165. * Various values for the opt_hdr_v1->headertype field, describing the
  166. * different types of optional headers. The "secure" header contains
  167. * informations related to secure boot (encryption keys, etc.). The
  168. * "binary" header contains ARM binary code to be executed prior to
  169. * executing the main payload (usually the bootloader). This is
  170. * typically used to execute DDR3 training code. The "register" header
  171. * allows to describe a set of (address, value) tuples that are
  172. * generally used to configure the DRAM controller.
  173. */
  174. #define OPT_HDR_V1_SECURE_TYPE 0x1
  175. #define OPT_HDR_V1_BINARY_TYPE 0x2
  176. #define OPT_HDR_V1_REGISTER_TYPE 0x3
  177. #define KWBHEADER_V1_SIZE(hdr) \
  178. (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
  179. enum kwbimage_cmd {
  180. CMD_INVALID,
  181. CMD_BOOT_FROM,
  182. CMD_NAND_ECC_MODE,
  183. CMD_NAND_PAGE_SIZE,
  184. CMD_SATA_PIO_MODE,
  185. CMD_DDR_INIT_DELAY,
  186. CMD_DATA
  187. };
  188. enum kwbimage_cmd_types {
  189. CFG_INVALID = -1,
  190. CFG_COMMAND,
  191. CFG_DATA0,
  192. CFG_DATA1
  193. };
  194. /*
  195. * functions
  196. */
  197. void init_kwb_image_type (void);
  198. /*
  199. * Byte 8 of the image header contains the version number. In the v0
  200. * header, byte 8 was reserved, and always set to 0. In the v1 header,
  201. * byte 8 has been changed to a proper field, set to 1.
  202. */
  203. static inline unsigned int image_version(void *header)
  204. {
  205. unsigned char *ptr = header;
  206. return ptr[8];
  207. }
  208. #endif /* _KWBIMAGE_H_ */