twox.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Binary instructions instr rA,rS
  11. *
  12. * Logic instructions: cntlzw
  13. * Arithmetic instructions: extsb, extsh
  14. * The test contains a pre-built table of instructions, operands and
  15. * expected results. For each table entry, the test will cyclically use
  16. * different sets of operand registers and result registers.
  17. */
  18. #include <post.h>
  19. #include "cpu_asm.h"
  20. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  21. extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
  22. extern ulong cpu_post_makecr (long v);
  23. static struct cpu_post_twox_s
  24. {
  25. ulong cmd;
  26. ulong op;
  27. ulong res;
  28. } cpu_post_twox_table[] =
  29. {
  30. {
  31. OP_EXTSB,
  32. 3,
  33. 3
  34. },
  35. {
  36. OP_EXTSB,
  37. 0xff,
  38. -1
  39. },
  40. {
  41. OP_EXTSH,
  42. 3,
  43. 3
  44. },
  45. {
  46. OP_EXTSH,
  47. 0xff,
  48. 0xff
  49. },
  50. {
  51. OP_EXTSH,
  52. 0xffff,
  53. -1
  54. },
  55. {
  56. OP_CNTLZW,
  57. 0x000fffff,
  58. 12
  59. },
  60. };
  61. static unsigned int cpu_post_twox_size = ARRAY_SIZE(cpu_post_twox_table);
  62. int cpu_post_test_twox (void)
  63. {
  64. int ret = 0;
  65. unsigned int i, reg;
  66. int flag = disable_interrupts();
  67. for (i = 0; i < cpu_post_twox_size && ret == 0; i++)
  68. {
  69. struct cpu_post_twox_s *test = cpu_post_twox_table + i;
  70. for (reg = 0; reg < 32 && ret == 0; reg++)
  71. {
  72. unsigned int reg0 = (reg + 0) % 32;
  73. unsigned int reg1 = (reg + 1) % 32;
  74. unsigned int stk = reg < 16 ? 31 : 15;
  75. unsigned long code[] =
  76. {
  77. ASM_STW(stk, 1, -4),
  78. ASM_ADDI(stk, 1, -16),
  79. ASM_STW(3, stk, 8),
  80. ASM_STW(reg0, stk, 4),
  81. ASM_STW(reg1, stk, 0),
  82. ASM_LWZ(reg0, stk, 8),
  83. ASM_11X(test->cmd, reg1, reg0),
  84. ASM_STW(reg1, stk, 8),
  85. ASM_LWZ(reg1, stk, 0),
  86. ASM_LWZ(reg0, stk, 4),
  87. ASM_LWZ(3, stk, 8),
  88. ASM_ADDI(1, stk, 16),
  89. ASM_LWZ(stk, 1, -4),
  90. ASM_BLR,
  91. };
  92. unsigned long codecr[] =
  93. {
  94. ASM_STW(stk, 1, -4),
  95. ASM_ADDI(stk, 1, -16),
  96. ASM_STW(3, stk, 8),
  97. ASM_STW(reg0, stk, 4),
  98. ASM_STW(reg1, stk, 0),
  99. ASM_LWZ(reg0, stk, 8),
  100. ASM_11X(test->cmd, reg1, reg0) | BIT_C,
  101. ASM_STW(reg1, stk, 8),
  102. ASM_LWZ(reg1, stk, 0),
  103. ASM_LWZ(reg0, stk, 4),
  104. ASM_LWZ(3, stk, 8),
  105. ASM_ADDI(1, stk, 16),
  106. ASM_LWZ(stk, 1, -4),
  107. ASM_BLR,
  108. };
  109. ulong res;
  110. ulong cr;
  111. if (ret == 0)
  112. {
  113. cr = 0;
  114. cpu_post_exec_21 (code, & cr, & res, test->op);
  115. ret = res == test->res && cr == 0 ? 0 : -1;
  116. if (ret != 0)
  117. {
  118. post_log ("Error at twox test %d !\n", i);
  119. }
  120. }
  121. if (ret == 0)
  122. {
  123. cpu_post_exec_21 (codecr, & cr, & res, test->op);
  124. ret = res == test->res &&
  125. (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
  126. if (ret != 0)
  127. {
  128. post_log ("Error at twox test %d !\n", i);
  129. }
  130. }
  131. }
  132. }
  133. if (flag)
  134. enable_interrupts();
  135. return ret;
  136. }
  137. #endif