threex.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Ternary instructions instr rA,rS,rB
  11. *
  12. * Logic instructions: or, orc, xor, nand, nor, eqv
  13. * Shift instructions: slw, srw, sraw
  14. *
  15. * The test contains a pre-built table of instructions, operands and
  16. * expected results. For each table entry, the test will cyclically use
  17. * different sets of operand registers and result registers.
  18. */
  19. #include <post.h>
  20. #include "cpu_asm.h"
  21. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  22. extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
  23. ulong op2);
  24. extern ulong cpu_post_makecr (long v);
  25. static struct cpu_post_threex_s
  26. {
  27. ulong cmd;
  28. ulong op1;
  29. ulong op2;
  30. ulong res;
  31. } cpu_post_threex_table[] =
  32. {
  33. {
  34. OP_OR,
  35. 0x1234,
  36. 0x5678,
  37. 0x1234 | 0x5678
  38. },
  39. {
  40. OP_ORC,
  41. 0x1234,
  42. 0x5678,
  43. 0x1234 | ~0x5678
  44. },
  45. {
  46. OP_XOR,
  47. 0x1234,
  48. 0x5678,
  49. 0x1234 ^ 0x5678
  50. },
  51. {
  52. OP_NAND,
  53. 0x1234,
  54. 0x5678,
  55. ~(0x1234 & 0x5678)
  56. },
  57. {
  58. OP_NOR,
  59. 0x1234,
  60. 0x5678,
  61. ~(0x1234 | 0x5678)
  62. },
  63. {
  64. OP_EQV,
  65. 0x1234,
  66. 0x5678,
  67. ~(0x1234 ^ 0x5678)
  68. },
  69. {
  70. OP_SLW,
  71. 0x80,
  72. 16,
  73. 0x800000
  74. },
  75. {
  76. OP_SLW,
  77. 0x80,
  78. 32,
  79. 0
  80. },
  81. {
  82. OP_SRW,
  83. 0x800000,
  84. 16,
  85. 0x80
  86. },
  87. {
  88. OP_SRW,
  89. 0x800000,
  90. 32,
  91. 0
  92. },
  93. {
  94. OP_SRAW,
  95. 0x80000000,
  96. 3,
  97. 0xf0000000
  98. },
  99. {
  100. OP_SRAW,
  101. 0x8000,
  102. 3,
  103. 0x1000
  104. },
  105. };
  106. static unsigned int cpu_post_threex_size = ARRAY_SIZE(cpu_post_threex_table);
  107. int cpu_post_test_threex (void)
  108. {
  109. int ret = 0;
  110. unsigned int i, reg;
  111. int flag = disable_interrupts();
  112. for (i = 0; i < cpu_post_threex_size && ret == 0; i++)
  113. {
  114. struct cpu_post_threex_s *test = cpu_post_threex_table + i;
  115. for (reg = 0; reg < 32 && ret == 0; reg++)
  116. {
  117. unsigned int reg0 = (reg + 0) % 32;
  118. unsigned int reg1 = (reg + 1) % 32;
  119. unsigned int reg2 = (reg + 2) % 32;
  120. unsigned int stk = reg < 16 ? 31 : 15;
  121. unsigned long code[] =
  122. {
  123. ASM_STW(stk, 1, -4),
  124. ASM_ADDI(stk, 1, -24),
  125. ASM_STW(3, stk, 12),
  126. ASM_STW(4, stk, 16),
  127. ASM_STW(reg0, stk, 8),
  128. ASM_STW(reg1, stk, 4),
  129. ASM_STW(reg2, stk, 0),
  130. ASM_LWZ(reg1, stk, 12),
  131. ASM_LWZ(reg0, stk, 16),
  132. ASM_12X(test->cmd, reg2, reg1, reg0),
  133. ASM_STW(reg2, stk, 12),
  134. ASM_LWZ(reg2, stk, 0),
  135. ASM_LWZ(reg1, stk, 4),
  136. ASM_LWZ(reg0, stk, 8),
  137. ASM_LWZ(3, stk, 12),
  138. ASM_ADDI(1, stk, 24),
  139. ASM_LWZ(stk, 1, -4),
  140. ASM_BLR,
  141. };
  142. unsigned long codecr[] =
  143. {
  144. ASM_STW(stk, 1, -4),
  145. ASM_ADDI(stk, 1, -24),
  146. ASM_STW(3, stk, 12),
  147. ASM_STW(4, stk, 16),
  148. ASM_STW(reg0, stk, 8),
  149. ASM_STW(reg1, stk, 4),
  150. ASM_STW(reg2, stk, 0),
  151. ASM_LWZ(reg1, stk, 12),
  152. ASM_LWZ(reg0, stk, 16),
  153. ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C,
  154. ASM_STW(reg2, stk, 12),
  155. ASM_LWZ(reg2, stk, 0),
  156. ASM_LWZ(reg1, stk, 4),
  157. ASM_LWZ(reg0, stk, 8),
  158. ASM_LWZ(3, stk, 12),
  159. ASM_ADDI(1, stk, 24),
  160. ASM_LWZ(stk, 1, -4),
  161. ASM_BLR,
  162. };
  163. ulong res;
  164. ulong cr;
  165. if (ret == 0)
  166. {
  167. cr = 0;
  168. cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
  169. ret = res == test->res && cr == 0 ? 0 : -1;
  170. if (ret != 0)
  171. {
  172. post_log ("Error at threex test %d !\n", i);
  173. }
  174. }
  175. if (ret == 0)
  176. {
  177. cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
  178. ret = res == test->res &&
  179. (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
  180. if (ret != 0)
  181. {
  182. post_log ("Error at threex test %d !\n", i);
  183. }
  184. }
  185. }
  186. }
  187. if (flag)
  188. enable_interrupts();
  189. return ret;
  190. }
  191. #endif