threei.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Ternary instructions instr rA,rS,UIMM
  11. *
  12. * Logic instructions: ori, oris, xori, xoris
  13. *
  14. * The test contains a pre-built table of instructions, operands and
  15. * expected results. For each table entry, the test will cyclically use
  16. * different sets of operand registers and result registers.
  17. */
  18. #include <post.h>
  19. #include "cpu_asm.h"
  20. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  21. extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
  22. extern ulong cpu_post_makecr (long v);
  23. static struct cpu_post_threei_s
  24. {
  25. ulong cmd;
  26. ulong op1;
  27. ushort op2;
  28. ulong res;
  29. } cpu_post_threei_table[] =
  30. {
  31. {
  32. OP_ORI,
  33. 0x80000000,
  34. 0xffff,
  35. 0x8000ffff
  36. },
  37. {
  38. OP_ORIS,
  39. 0x00008000,
  40. 0xffff,
  41. 0xffff8000
  42. },
  43. {
  44. OP_XORI,
  45. 0x8000ffff,
  46. 0xffff,
  47. 0x80000000
  48. },
  49. {
  50. OP_XORIS,
  51. 0x00008000,
  52. 0xffff,
  53. 0xffff8000
  54. },
  55. };
  56. static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);
  57. int cpu_post_test_threei (void)
  58. {
  59. int ret = 0;
  60. unsigned int i, reg;
  61. int flag = disable_interrupts();
  62. for (i = 0; i < cpu_post_threei_size && ret == 0; i++)
  63. {
  64. struct cpu_post_threei_s *test = cpu_post_threei_table + i;
  65. for (reg = 0; reg < 32 && ret == 0; reg++)
  66. {
  67. unsigned int reg0 = (reg + 0) % 32;
  68. unsigned int reg1 = (reg + 1) % 32;
  69. unsigned int stk = reg < 16 ? 31 : 15;
  70. unsigned long code[] =
  71. {
  72. ASM_STW(stk, 1, -4),
  73. ASM_ADDI(stk, 1, -16),
  74. ASM_STW(3, stk, 8),
  75. ASM_STW(reg0, stk, 4),
  76. ASM_STW(reg1, stk, 0),
  77. ASM_LWZ(reg0, stk, 8),
  78. ASM_11IX(test->cmd, reg1, reg0, test->op2),
  79. ASM_STW(reg1, stk, 8),
  80. ASM_LWZ(reg1, stk, 0),
  81. ASM_LWZ(reg0, stk, 4),
  82. ASM_LWZ(3, stk, 8),
  83. ASM_ADDI(1, stk, 16),
  84. ASM_LWZ(stk, 1, -4),
  85. ASM_BLR,
  86. };
  87. ulong res;
  88. ulong cr;
  89. cr = 0;
  90. cpu_post_exec_21 (code, & cr, & res, test->op1);
  91. ret = res == test->res && cr == 0 ? 0 : -1;
  92. if (ret != 0)
  93. {
  94. post_log ("Error at threei test %d !\n", i);
  95. }
  96. }
  97. }
  98. if (flag)
  99. enable_interrupts();
  100. return ret;
  101. }
  102. #endif