three.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Ternary instructions instr rD,rA,rB
  11. *
  12. * Arithmetic instructions: add, addc, adde, subf, subfc, subfe,
  13. * mullw, mulhw, mulhwu, divw, divwu
  14. *
  15. * The test contains a pre-built table of instructions, operands and
  16. * expected results. For each table entry, the test will cyclically use
  17. * different sets of operand registers and result registers.
  18. */
  19. #include <post.h>
  20. #include "cpu_asm.h"
  21. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  22. extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
  23. ulong op2);
  24. extern ulong cpu_post_makecr (long v);
  25. static struct cpu_post_three_s
  26. {
  27. ulong cmd;
  28. ulong op1;
  29. ulong op2;
  30. ulong res;
  31. } cpu_post_three_table[] =
  32. {
  33. {
  34. OP_ADD,
  35. 100,
  36. 200,
  37. 300
  38. },
  39. {
  40. OP_ADD,
  41. 100,
  42. -200,
  43. -100
  44. },
  45. {
  46. OP_ADDC,
  47. 100,
  48. 200,
  49. 300
  50. },
  51. {
  52. OP_ADDC,
  53. 100,
  54. -200,
  55. -100
  56. },
  57. {
  58. OP_ADDE,
  59. 100,
  60. 200,
  61. 300
  62. },
  63. {
  64. OP_ADDE,
  65. 100,
  66. -200,
  67. -100
  68. },
  69. {
  70. OP_SUBF,
  71. 100,
  72. 200,
  73. 100
  74. },
  75. {
  76. OP_SUBF,
  77. 300,
  78. 200,
  79. -100
  80. },
  81. {
  82. OP_SUBFC,
  83. 100,
  84. 200,
  85. 100
  86. },
  87. {
  88. OP_SUBFC,
  89. 300,
  90. 200,
  91. -100
  92. },
  93. {
  94. OP_SUBFE,
  95. 100,
  96. 200,
  97. 200 + ~100
  98. },
  99. {
  100. OP_SUBFE,
  101. 300,
  102. 200,
  103. 200 + ~300
  104. },
  105. {
  106. OP_MULLW,
  107. 200,
  108. 300,
  109. 200 * 300
  110. },
  111. {
  112. OP_MULHW,
  113. 0x10000000,
  114. 0x10000000,
  115. 0x1000000
  116. },
  117. {
  118. OP_MULHWU,
  119. 0x80000000,
  120. 0x80000000,
  121. 0x40000000
  122. },
  123. {
  124. OP_DIVW,
  125. -20,
  126. 5,
  127. -4
  128. },
  129. {
  130. OP_DIVWU,
  131. 0x8000,
  132. 0x200,
  133. 0x40
  134. },
  135. };
  136. static unsigned int cpu_post_three_size = ARRAY_SIZE(cpu_post_three_table);
  137. int cpu_post_test_three (void)
  138. {
  139. int ret = 0;
  140. unsigned int i, reg;
  141. int flag = disable_interrupts();
  142. for (i = 0; i < cpu_post_three_size && ret == 0; i++)
  143. {
  144. struct cpu_post_three_s *test = cpu_post_three_table + i;
  145. for (reg = 0; reg < 32 && ret == 0; reg++)
  146. {
  147. unsigned int reg0 = (reg + 0) % 32;
  148. unsigned int reg1 = (reg + 1) % 32;
  149. unsigned int reg2 = (reg + 2) % 32;
  150. unsigned int stk = reg < 16 ? 31 : 15;
  151. unsigned long code[] =
  152. {
  153. ASM_STW(stk, 1, -4),
  154. ASM_ADDI(stk, 1, -24),
  155. ASM_STW(3, stk, 12),
  156. ASM_STW(4, stk, 16),
  157. ASM_STW(reg0, stk, 8),
  158. ASM_STW(reg1, stk, 4),
  159. ASM_STW(reg2, stk, 0),
  160. ASM_LWZ(reg1, stk, 12),
  161. ASM_LWZ(reg0, stk, 16),
  162. ASM_12(test->cmd, reg2, reg1, reg0),
  163. ASM_STW(reg2, stk, 12),
  164. ASM_LWZ(reg2, stk, 0),
  165. ASM_LWZ(reg1, stk, 4),
  166. ASM_LWZ(reg0, stk, 8),
  167. ASM_LWZ(3, stk, 12),
  168. ASM_ADDI(1, stk, 24),
  169. ASM_LWZ(stk, 1, -4),
  170. ASM_BLR,
  171. };
  172. unsigned long codecr[] =
  173. {
  174. ASM_STW(stk, 1, -4),
  175. ASM_ADDI(stk, 1, -24),
  176. ASM_STW(3, stk, 12),
  177. ASM_STW(4, stk, 16),
  178. ASM_STW(reg0, stk, 8),
  179. ASM_STW(reg1, stk, 4),
  180. ASM_STW(reg2, stk, 0),
  181. ASM_LWZ(reg1, stk, 12),
  182. ASM_LWZ(reg0, stk, 16),
  183. ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C,
  184. ASM_STW(reg2, stk, 12),
  185. ASM_LWZ(reg2, stk, 0),
  186. ASM_LWZ(reg1, stk, 4),
  187. ASM_LWZ(reg0, stk, 8),
  188. ASM_LWZ(3, stk, 12),
  189. ASM_ADDI(1, stk, 24),
  190. ASM_LWZ(stk, 1, -4),
  191. ASM_BLR,
  192. };
  193. ulong res;
  194. ulong cr;
  195. if (ret == 0)
  196. {
  197. cr = 0;
  198. cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
  199. ret = res == test->res && cr == 0 ? 0 : -1;
  200. if (ret != 0)
  201. {
  202. post_log ("Error at three test %d !\n", i);
  203. }
  204. }
  205. if (ret == 0)
  206. {
  207. cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
  208. ret = res == test->res &&
  209. (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
  210. if (ret != 0)
  211. {
  212. post_log ("Error at three test %d !\n", i);
  213. }
  214. }
  215. }
  216. }
  217. if (flag)
  218. enable_interrupts();
  219. return ret;
  220. }
  221. #endif