store.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Store instructions: stb(x)(u), sth(x)(u), stw(x)(u)
  11. *
  12. * All operations are performed on a 16-byte array. The array
  13. * is 4-byte aligned. The base register points to offset 8.
  14. * The immediate offset (index register) ranges in [-8 ... +7].
  15. * The test cases are composed so that they do not
  16. * cause alignment exceptions.
  17. * The test contains a pre-built table describing all test cases.
  18. * The table entry contains:
  19. * the instruction opcode, the value of the index register and
  20. * the value of the source register. After executing the
  21. * instruction, the test verifies the contents of the array
  22. * and the value of the base register (it must change for "store
  23. * with update" instructions).
  24. */
  25. #include <post.h>
  26. #include "cpu_asm.h"
  27. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  28. extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3);
  29. extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2);
  30. static struct cpu_post_store_s
  31. {
  32. ulong cmd;
  33. uint width;
  34. int update;
  35. int index;
  36. ulong offset;
  37. ulong value;
  38. } cpu_post_store_table[] =
  39. {
  40. {
  41. OP_STW,
  42. 4,
  43. 0,
  44. 0,
  45. -4,
  46. 0xff00ff00
  47. },
  48. {
  49. OP_STH,
  50. 2,
  51. 0,
  52. 0,
  53. -2,
  54. 0xff00
  55. },
  56. {
  57. OP_STB,
  58. 1,
  59. 0,
  60. 0,
  61. -1,
  62. 0xff
  63. },
  64. {
  65. OP_STWU,
  66. 4,
  67. 1,
  68. 0,
  69. -4,
  70. 0xff00ff00
  71. },
  72. {
  73. OP_STHU,
  74. 2,
  75. 1,
  76. 0,
  77. -2,
  78. 0xff00
  79. },
  80. {
  81. OP_STBU,
  82. 1,
  83. 1,
  84. 0,
  85. -1,
  86. 0xff
  87. },
  88. {
  89. OP_STWX,
  90. 4,
  91. 0,
  92. 1,
  93. -4,
  94. 0xff00ff00
  95. },
  96. {
  97. OP_STHX,
  98. 2,
  99. 0,
  100. 1,
  101. -2,
  102. 0xff00
  103. },
  104. {
  105. OP_STBX,
  106. 1,
  107. 0,
  108. 1,
  109. -1,
  110. 0xff
  111. },
  112. {
  113. OP_STWUX,
  114. 4,
  115. 1,
  116. 1,
  117. -4,
  118. 0xff00ff00
  119. },
  120. {
  121. OP_STHUX,
  122. 2,
  123. 1,
  124. 1,
  125. -2,
  126. 0xff00
  127. },
  128. {
  129. OP_STBUX,
  130. 1,
  131. 1,
  132. 1,
  133. -1,
  134. 0xff
  135. },
  136. };
  137. static unsigned int cpu_post_store_size = ARRAY_SIZE(cpu_post_store_table);
  138. int cpu_post_test_store (void)
  139. {
  140. int ret = 0;
  141. unsigned int i;
  142. int flag = disable_interrupts();
  143. for (i = 0; i < cpu_post_store_size && ret == 0; i++)
  144. {
  145. struct cpu_post_store_s *test = cpu_post_store_table + i;
  146. uchar data[16] =
  147. { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
  148. ulong base0 = (ulong) (data + 8);
  149. ulong base = base0;
  150. if (test->index)
  151. {
  152. ulong code[] =
  153. {
  154. ASM_12(test->cmd, 5, 3, 4),
  155. ASM_BLR,
  156. };
  157. cpu_post_exec_12w (code, &base, test->offset, test->value);
  158. }
  159. else
  160. {
  161. ulong code[] =
  162. {
  163. ASM_11I(test->cmd, 4, 3, test->offset),
  164. ASM_BLR,
  165. };
  166. cpu_post_exec_11w (code, &base, test->value);
  167. }
  168. if (ret == 0)
  169. {
  170. if (test->update)
  171. ret = base == base0 + test->offset ? 0 : -1;
  172. else
  173. ret = base == base0 ? 0 : -1;
  174. }
  175. if (ret == 0)
  176. {
  177. switch (test->width)
  178. {
  179. case 1:
  180. ret = *(uchar *)(base0 + test->offset) == test->value ?
  181. 0 : -1;
  182. break;
  183. case 2:
  184. ret = *(ushort *)(base0 + test->offset) == test->value ?
  185. 0 : -1;
  186. break;
  187. case 4:
  188. ret = *(ulong *)(base0 + test->offset) == test->value ?
  189. 0 : -1;
  190. break;
  191. }
  192. }
  193. if (ret != 0)
  194. {
  195. post_log ("Error at store test %d !\n", i);
  196. }
  197. }
  198. if (flag)
  199. enable_interrupts();
  200. return ret;
  201. }
  202. #endif