srawi.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Shift instructions: srawi
  11. *
  12. * The test contains a pre-built table of instructions, operands and
  13. * expected results. For each table entry, the test will cyclically use
  14. * different sets of operand registers and result registers.
  15. */
  16. #include <post.h>
  17. #include "cpu_asm.h"
  18. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  19. extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
  20. extern ulong cpu_post_makecr (long v);
  21. static struct cpu_post_srawi_s
  22. {
  23. ulong cmd;
  24. ulong op1;
  25. uchar op2;
  26. ulong res;
  27. } cpu_post_srawi_table[] =
  28. {
  29. {
  30. OP_SRAWI,
  31. 0x8000,
  32. 3,
  33. 0x1000
  34. },
  35. {
  36. OP_SRAWI,
  37. 0x80000000,
  38. 3,
  39. 0xf0000000
  40. },
  41. };
  42. static unsigned int cpu_post_srawi_size = ARRAY_SIZE(cpu_post_srawi_table);
  43. int cpu_post_test_srawi (void)
  44. {
  45. int ret = 0;
  46. unsigned int i, reg;
  47. int flag = disable_interrupts();
  48. for (i = 0; i < cpu_post_srawi_size && ret == 0; i++)
  49. {
  50. struct cpu_post_srawi_s *test = cpu_post_srawi_table + i;
  51. for (reg = 0; reg < 32 && ret == 0; reg++)
  52. {
  53. unsigned int reg0 = (reg + 0) % 32;
  54. unsigned int reg1 = (reg + 1) % 32;
  55. unsigned int stk = reg < 16 ? 31 : 15;
  56. unsigned long code[] =
  57. {
  58. ASM_STW(stk, 1, -4),
  59. ASM_ADDI(stk, 1, -16),
  60. ASM_STW(3, stk, 8),
  61. ASM_STW(reg0, stk, 4),
  62. ASM_STW(reg1, stk, 0),
  63. ASM_LWZ(reg0, stk, 8),
  64. ASM_11S(test->cmd, reg1, reg0, test->op2),
  65. ASM_STW(reg1, stk, 8),
  66. ASM_LWZ(reg1, stk, 0),
  67. ASM_LWZ(reg0, stk, 4),
  68. ASM_LWZ(3, stk, 8),
  69. ASM_ADDI(1, stk, 16),
  70. ASM_LWZ(stk, 1, -4),
  71. ASM_BLR,
  72. };
  73. unsigned long codecr[] =
  74. {
  75. ASM_STW(stk, 1, -4),
  76. ASM_ADDI(stk, 1, -16),
  77. ASM_STW(3, stk, 8),
  78. ASM_STW(reg0, stk, 4),
  79. ASM_STW(reg1, stk, 0),
  80. ASM_LWZ(reg0, stk, 8),
  81. ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C,
  82. ASM_STW(reg1, stk, 8),
  83. ASM_LWZ(reg1, stk, 0),
  84. ASM_LWZ(reg0, stk, 4),
  85. ASM_LWZ(3, stk, 8),
  86. ASM_ADDI(1, stk, 16),
  87. ASM_LWZ(stk, 1, -4),
  88. ASM_BLR,
  89. };
  90. ulong res;
  91. ulong cr;
  92. if (ret == 0)
  93. {
  94. cr = 0;
  95. cpu_post_exec_21 (code, & cr, & res, test->op1);
  96. ret = res == test->res && cr == 0 ? 0 : -1;
  97. if (ret != 0)
  98. {
  99. post_log ("Error at srawi test %d !\n", i);
  100. }
  101. }
  102. if (ret == 0)
  103. {
  104. cpu_post_exec_21 (codecr, & cr, & res, test->op1);
  105. ret = res == test->res &&
  106. (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
  107. if (ret != 0)
  108. {
  109. post_log ("Error at srawi test %d !\n", i);
  110. }
  111. }
  112. }
  113. }
  114. if (flag)
  115. enable_interrupts();
  116. return ret;
  117. }
  118. #endif