rlwnm.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Shift instructions: rlwnm
  11. *
  12. * The test contains a pre-built table of instructions, operands and
  13. * expected results. For each table entry, the test will cyclically use
  14. * different sets of operand registers and result registers.
  15. */
  16. #include <post.h>
  17. #include "cpu_asm.h"
  18. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  19. extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
  20. ulong op2);
  21. extern ulong cpu_post_makecr (long v);
  22. static struct cpu_post_rlwnm_s
  23. {
  24. ulong cmd;
  25. ulong op1;
  26. ulong op2;
  27. uchar mb;
  28. uchar me;
  29. ulong res;
  30. } cpu_post_rlwnm_table[] =
  31. {
  32. {
  33. OP_RLWNM,
  34. 0xffff0000,
  35. 24,
  36. 16,
  37. 23,
  38. 0x0000ff00
  39. },
  40. };
  41. static unsigned int cpu_post_rlwnm_size = ARRAY_SIZE(cpu_post_rlwnm_table);
  42. int cpu_post_test_rlwnm (void)
  43. {
  44. int ret = 0;
  45. unsigned int i, reg;
  46. int flag = disable_interrupts();
  47. for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++)
  48. {
  49. struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i;
  50. for (reg = 0; reg < 32 && ret == 0; reg++)
  51. {
  52. unsigned int reg0 = (reg + 0) % 32;
  53. unsigned int reg1 = (reg + 1) % 32;
  54. unsigned int reg2 = (reg + 2) % 32;
  55. unsigned int stk = reg < 16 ? 31 : 15;
  56. unsigned long code[] =
  57. {
  58. ASM_STW(stk, 1, -4),
  59. ASM_ADDI(stk, 1, -24),
  60. ASM_STW(3, stk, 12),
  61. ASM_STW(4, stk, 16),
  62. ASM_STW(reg0, stk, 8),
  63. ASM_STW(reg1, stk, 4),
  64. ASM_STW(reg2, stk, 0),
  65. ASM_LWZ(reg1, stk, 12),
  66. ASM_LWZ(reg0, stk, 16),
  67. ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me),
  68. ASM_STW(reg2, stk, 12),
  69. ASM_LWZ(reg2, stk, 0),
  70. ASM_LWZ(reg1, stk, 4),
  71. ASM_LWZ(reg0, stk, 8),
  72. ASM_LWZ(3, stk, 12),
  73. ASM_ADDI(1, stk, 24),
  74. ASM_LWZ(stk, 1, -4),
  75. ASM_BLR,
  76. };
  77. unsigned long codecr[] =
  78. {
  79. ASM_STW(stk, 1, -4),
  80. ASM_ADDI(stk, 1, -24),
  81. ASM_STW(3, stk, 12),
  82. ASM_STW(4, stk, 16),
  83. ASM_STW(reg0, stk, 8),
  84. ASM_STW(reg1, stk, 4),
  85. ASM_STW(reg2, stk, 0),
  86. ASM_LWZ(reg1, stk, 12),
  87. ASM_LWZ(reg0, stk, 16),
  88. ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) |
  89. BIT_C,
  90. ASM_STW(reg2, stk, 12),
  91. ASM_LWZ(reg2, stk, 0),
  92. ASM_LWZ(reg1, stk, 4),
  93. ASM_LWZ(reg0, stk, 8),
  94. ASM_LWZ(3, stk, 12),
  95. ASM_ADDI(1, stk, 24),
  96. ASM_LWZ(stk, 1, -4),
  97. ASM_BLR,
  98. };
  99. ulong res;
  100. ulong cr;
  101. if (ret == 0)
  102. {
  103. cr = 0;
  104. cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
  105. ret = res == test->res && cr == 0 ? 0 : -1;
  106. if (ret != 0)
  107. {
  108. post_log ("Error at rlwnm test %d !\n", i);
  109. }
  110. }
  111. if (ret == 0)
  112. {
  113. cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
  114. ret = res == test->res &&
  115. (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
  116. if (ret != 0)
  117. {
  118. post_log ("Error at rlwnm test %d !\n", i);
  119. }
  120. }
  121. }
  122. }
  123. if (flag)
  124. enable_interrupts();
  125. return ret;
  126. }
  127. #endif