rlwimi.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Shift instructions: rlwimi
  11. *
  12. * The test contains a pre-built table of instructions, operands and
  13. * expected results. For each table entry, the test will cyclically use
  14. * different sets of operand registers and result registers.
  15. */
  16. #include <post.h>
  17. #include "cpu_asm.h"
  18. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  19. extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
  20. ulong op2);
  21. extern ulong cpu_post_makecr (long v);
  22. static struct cpu_post_rlwimi_s
  23. {
  24. ulong cmd;
  25. ulong op0;
  26. ulong op1;
  27. uchar op2;
  28. uchar mb;
  29. uchar me;
  30. ulong res;
  31. } cpu_post_rlwimi_table[] =
  32. {
  33. {
  34. OP_RLWIMI,
  35. 0xff00ffff,
  36. 0x0000aa00,
  37. 8,
  38. 8,
  39. 15,
  40. 0xffaaffff
  41. },
  42. };
  43. static unsigned int cpu_post_rlwimi_size = ARRAY_SIZE(cpu_post_rlwimi_table);
  44. int cpu_post_test_rlwimi (void)
  45. {
  46. int ret = 0;
  47. unsigned int i, reg;
  48. int flag = disable_interrupts();
  49. for (i = 0; i < cpu_post_rlwimi_size && ret == 0; i++)
  50. {
  51. struct cpu_post_rlwimi_s *test = cpu_post_rlwimi_table + i;
  52. for (reg = 0; reg < 32 && ret == 0; reg++)
  53. {
  54. unsigned int reg0 = (reg + 0) % 32;
  55. unsigned int reg1 = (reg + 1) % 32;
  56. unsigned int stk = reg < 16 ? 31 : 15;
  57. unsigned long code[] =
  58. {
  59. ASM_STW(stk, 1, -4),
  60. ASM_ADDI(stk, 1, -20),
  61. ASM_STW(3, stk, 8),
  62. ASM_STW(4, stk, 12),
  63. ASM_STW(reg0, stk, 4),
  64. ASM_STW(reg1, stk, 0),
  65. ASM_LWZ(reg1, stk, 8),
  66. ASM_LWZ(reg0, stk, 12),
  67. ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
  68. ASM_STW(reg1, stk, 8),
  69. ASM_LWZ(reg1, stk, 0),
  70. ASM_LWZ(reg0, stk, 4),
  71. ASM_LWZ(3, stk, 8),
  72. ASM_ADDI(1, stk, 20),
  73. ASM_LWZ(stk, 1, -4),
  74. ASM_BLR,
  75. };
  76. unsigned long codecr[] =
  77. {
  78. ASM_STW(stk, 1, -4),
  79. ASM_ADDI(stk, 1, -20),
  80. ASM_STW(3, stk, 8),
  81. ASM_STW(4, stk, 12),
  82. ASM_STW(reg0, stk, 4),
  83. ASM_STW(reg1, stk, 0),
  84. ASM_LWZ(reg1, stk, 8),
  85. ASM_LWZ(reg0, stk, 12),
  86. ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) |
  87. BIT_C,
  88. ASM_STW(reg1, stk, 8),
  89. ASM_LWZ(reg1, stk, 0),
  90. ASM_LWZ(reg0, stk, 4),
  91. ASM_LWZ(3, stk, 8),
  92. ASM_ADDI(1, stk, 20),
  93. ASM_LWZ(stk, 1, -4),
  94. ASM_BLR,
  95. };
  96. ulong res;
  97. ulong cr;
  98. if (ret == 0)
  99. {
  100. cr = 0;
  101. cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1);
  102. ret = res == test->res && cr == 0 ? 0 : -1;
  103. if (ret != 0)
  104. {
  105. post_log ("Error at rlwimi test %d !\n", i);
  106. }
  107. }
  108. if (ret == 0)
  109. {
  110. cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1);
  111. ret = res == test->res &&
  112. (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
  113. if (ret != 0)
  114. {
  115. post_log ("Error at rlwimi test %d !\n", i);
  116. }
  117. }
  118. }
  119. }
  120. if (flag)
  121. enable_interrupts();
  122. return ret;
  123. }
  124. #endif