load.c 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Load instructions: lbz(x)(u), lhz(x)(u), lha(x)(u), lwz(x)(u)
  11. *
  12. * All operations are performed on a 16-byte array. The array
  13. * is 4-byte aligned. The base register points to offset 8.
  14. * The immediate offset (index register) ranges in [-8 ... +7].
  15. * The test cases are composed so that they do not
  16. * cause alignment exceptions.
  17. * The test contains a pre-built table describing all test cases.
  18. * The table entry contains:
  19. * the instruction opcode, the array contents, the value of the index
  20. * register and the expected value of the destination register.
  21. * After executing the instruction, the test verifies the
  22. * value of the destination register and the value of the base
  23. * register (it must change for "load with update" instructions).
  24. */
  25. #include <post.h>
  26. #include "cpu_asm.h"
  27. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  28. extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3);
  29. extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2);
  30. static struct cpu_post_load_s
  31. {
  32. ulong cmd;
  33. uint width;
  34. int update;
  35. int index;
  36. ulong offset;
  37. } cpu_post_load_table[] =
  38. {
  39. {
  40. OP_LWZ,
  41. 4,
  42. 0,
  43. 0,
  44. 4
  45. },
  46. {
  47. OP_LHA,
  48. 3,
  49. 0,
  50. 0,
  51. 2
  52. },
  53. {
  54. OP_LHZ,
  55. 2,
  56. 0,
  57. 0,
  58. 2
  59. },
  60. {
  61. OP_LBZ,
  62. 1,
  63. 0,
  64. 0,
  65. 1
  66. },
  67. {
  68. OP_LWZU,
  69. 4,
  70. 1,
  71. 0,
  72. 4
  73. },
  74. {
  75. OP_LHAU,
  76. 3,
  77. 1,
  78. 0,
  79. 2
  80. },
  81. {
  82. OP_LHZU,
  83. 2,
  84. 1,
  85. 0,
  86. 2
  87. },
  88. {
  89. OP_LBZU,
  90. 1,
  91. 1,
  92. 0,
  93. 1
  94. },
  95. {
  96. OP_LWZX,
  97. 4,
  98. 0,
  99. 1,
  100. 4
  101. },
  102. {
  103. OP_LHAX,
  104. 3,
  105. 0,
  106. 1,
  107. 2
  108. },
  109. {
  110. OP_LHZX,
  111. 2,
  112. 0,
  113. 1,
  114. 2
  115. },
  116. {
  117. OP_LBZX,
  118. 1,
  119. 0,
  120. 1,
  121. 1
  122. },
  123. {
  124. OP_LWZUX,
  125. 4,
  126. 1,
  127. 1,
  128. 4
  129. },
  130. {
  131. OP_LHAUX,
  132. 3,
  133. 1,
  134. 1,
  135. 2
  136. },
  137. {
  138. OP_LHZUX,
  139. 2,
  140. 1,
  141. 1,
  142. 2
  143. },
  144. {
  145. OP_LBZUX,
  146. 1,
  147. 1,
  148. 1,
  149. 1
  150. },
  151. };
  152. static unsigned int cpu_post_load_size = ARRAY_SIZE(cpu_post_load_table);
  153. int cpu_post_test_load (void)
  154. {
  155. int ret = 0;
  156. unsigned int i;
  157. int flag = disable_interrupts();
  158. for (i = 0; i < cpu_post_load_size && ret == 0; i++)
  159. {
  160. struct cpu_post_load_s *test = cpu_post_load_table + i;
  161. uchar data[16] =
  162. { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
  163. ulong base0 = (ulong) (data + 8);
  164. ulong base = base0;
  165. ulong value;
  166. if (test->index)
  167. {
  168. ulong code[] =
  169. {
  170. ASM_12(test->cmd, 5, 3, 4),
  171. ASM_BLR,
  172. };
  173. cpu_post_exec_22w (code, &base, test->offset, &value);
  174. }
  175. else
  176. {
  177. ulong code[] =
  178. {
  179. ASM_11I(test->cmd, 4, 3, test->offset),
  180. ASM_BLR,
  181. };
  182. cpu_post_exec_21w (code, &base, &value);
  183. }
  184. if (ret == 0)
  185. {
  186. if (test->update)
  187. ret = base == base0 + test->offset ? 0 : -1;
  188. else
  189. ret = base == base0 ? 0 : -1;
  190. }
  191. if (ret == 0)
  192. {
  193. switch (test->width)
  194. {
  195. case 1:
  196. ret = *(uchar *)(base0 + test->offset) == value ?
  197. 0 : -1;
  198. break;
  199. case 2:
  200. ret = *(ushort *)(base0 + test->offset) == value ?
  201. 0 : -1;
  202. break;
  203. case 3:
  204. ret = *(short *)(base0 + test->offset) == value ?
  205. 0 : -1;
  206. break;
  207. case 4:
  208. ret = *(ulong *)(base0 + test->offset) == value ?
  209. 0 : -1;
  210. break;
  211. }
  212. }
  213. if (ret != 0)
  214. {
  215. post_log ("Error at load test %d !\n", i);
  216. }
  217. }
  218. if (flag)
  219. enable_interrupts();
  220. return ret;
  221. }
  222. #endif