cr.c 5.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Condition register istructions: mtcr, mfcr, mcrxr,
  11. * crand, crandc, cror, crorc, crxor,
  12. * crnand, crnor, creqv, mcrf
  13. *
  14. * The mtcrf/mfcr instructions is tested by loading different
  15. * values into the condition register (mtcrf), moving its value
  16. * to a general-purpose register (mfcr) and comparing this value
  17. * with the expected one.
  18. * The mcrxr instruction is tested by loading a fixed value
  19. * into the XER register (mtspr), moving XER value to the
  20. * condition register (mcrxr), moving it to a general-purpose
  21. * register (mfcr) and comparing the value of this register with
  22. * the expected one.
  23. * The rest of instructions is tested by loading a fixed
  24. * value into the condition register (mtcrf), executing each
  25. * instruction several times to modify all 4-bit condition
  26. * fields, moving the value of the conditional register to a
  27. * general-purpose register (mfcr) and comparing it with the
  28. * expected one.
  29. */
  30. #include <post.h>
  31. #include "cpu_asm.h"
  32. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  33. extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1);
  34. extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3);
  35. static ulong cpu_post_cr_table1[] =
  36. {
  37. 0xaaaaaaaa,
  38. 0x55555555,
  39. };
  40. static unsigned int cpu_post_cr_size1 = ARRAY_SIZE(cpu_post_cr_table1);
  41. static struct cpu_post_cr_s2 {
  42. ulong xer;
  43. ulong cr;
  44. } cpu_post_cr_table2[] =
  45. {
  46. {
  47. 0xa0000000,
  48. 1
  49. },
  50. {
  51. 0x40000000,
  52. 5
  53. },
  54. };
  55. static unsigned int cpu_post_cr_size2 = ARRAY_SIZE(cpu_post_cr_table2);
  56. static struct cpu_post_cr_s3 {
  57. ulong cr;
  58. ulong cs;
  59. ulong cd;
  60. ulong res;
  61. } cpu_post_cr_table3[] =
  62. {
  63. {
  64. 0x01234567,
  65. 0,
  66. 4,
  67. 0x01230567
  68. },
  69. {
  70. 0x01234567,
  71. 7,
  72. 0,
  73. 0x71234567
  74. },
  75. };
  76. static unsigned int cpu_post_cr_size3 = ARRAY_SIZE(cpu_post_cr_table3);
  77. static struct cpu_post_cr_s4 {
  78. ulong cmd;
  79. ulong cr;
  80. ulong op1;
  81. ulong op2;
  82. ulong op3;
  83. ulong res;
  84. } cpu_post_cr_table4[] =
  85. {
  86. {
  87. OP_CRAND,
  88. 0x0000ffff,
  89. 0,
  90. 16,
  91. 0,
  92. 0x0000ffff
  93. },
  94. {
  95. OP_CRAND,
  96. 0x0000ffff,
  97. 16,
  98. 17,
  99. 0,
  100. 0x8000ffff
  101. },
  102. {
  103. OP_CRANDC,
  104. 0x0000ffff,
  105. 0,
  106. 16,
  107. 0,
  108. 0x0000ffff
  109. },
  110. {
  111. OP_CRANDC,
  112. 0x0000ffff,
  113. 16,
  114. 0,
  115. 0,
  116. 0x8000ffff
  117. },
  118. {
  119. OP_CROR,
  120. 0x0000ffff,
  121. 0,
  122. 16,
  123. 0,
  124. 0x8000ffff
  125. },
  126. {
  127. OP_CROR,
  128. 0x0000ffff,
  129. 0,
  130. 1,
  131. 0,
  132. 0x0000ffff
  133. },
  134. {
  135. OP_CRORC,
  136. 0x0000ffff,
  137. 0,
  138. 16,
  139. 0,
  140. 0x0000ffff
  141. },
  142. {
  143. OP_CRORC,
  144. 0x0000ffff,
  145. 0,
  146. 0,
  147. 0,
  148. 0x8000ffff
  149. },
  150. {
  151. OP_CRXOR,
  152. 0x0000ffff,
  153. 0,
  154. 0,
  155. 0,
  156. 0x0000ffff
  157. },
  158. {
  159. OP_CRXOR,
  160. 0x0000ffff,
  161. 0,
  162. 16,
  163. 0,
  164. 0x8000ffff
  165. },
  166. {
  167. OP_CRNAND,
  168. 0x0000ffff,
  169. 0,
  170. 16,
  171. 0,
  172. 0x8000ffff
  173. },
  174. {
  175. OP_CRNAND,
  176. 0x0000ffff,
  177. 16,
  178. 17,
  179. 0,
  180. 0x0000ffff
  181. },
  182. {
  183. OP_CRNOR,
  184. 0x0000ffff,
  185. 0,
  186. 16,
  187. 0,
  188. 0x0000ffff
  189. },
  190. {
  191. OP_CRNOR,
  192. 0x0000ffff,
  193. 0,
  194. 1,
  195. 0,
  196. 0x8000ffff
  197. },
  198. {
  199. OP_CREQV,
  200. 0x0000ffff,
  201. 0,
  202. 0,
  203. 0,
  204. 0x8000ffff
  205. },
  206. {
  207. OP_CREQV,
  208. 0x0000ffff,
  209. 0,
  210. 16,
  211. 0,
  212. 0x0000ffff
  213. },
  214. };
  215. static unsigned int cpu_post_cr_size4 = ARRAY_SIZE(cpu_post_cr_table4);
  216. int cpu_post_test_cr (void)
  217. {
  218. int ret = 0;
  219. unsigned int i;
  220. unsigned long cr_sav;
  221. int flag = disable_interrupts();
  222. asm ( "mfcr %0" : "=r" (cr_sav) : );
  223. for (i = 0; i < cpu_post_cr_size1 && ret == 0; i++)
  224. {
  225. ulong cr = cpu_post_cr_table1[i];
  226. ulong res;
  227. unsigned long code[] =
  228. {
  229. ASM_MTCR(3),
  230. ASM_MFCR(3),
  231. ASM_BLR,
  232. };
  233. cpu_post_exec_11 (code, &res, cr);
  234. ret = res == cr ? 0 : -1;
  235. if (ret != 0)
  236. {
  237. post_log ("Error at cr1 test %d !\n", i);
  238. }
  239. }
  240. for (i = 0; i < cpu_post_cr_size2 && ret == 0; i++)
  241. {
  242. struct cpu_post_cr_s2 *test = cpu_post_cr_table2 + i;
  243. ulong res;
  244. ulong xer;
  245. unsigned long code[] =
  246. {
  247. ASM_MTXER(3),
  248. ASM_MCRXR(test->cr),
  249. ASM_MFCR(3),
  250. ASM_MFXER(4),
  251. ASM_BLR,
  252. };
  253. cpu_post_exec_21x (code, &res, &xer, test->xer);
  254. ret = xer == 0 && ((res << (4 * test->cr)) & 0xe0000000) == test->xer ?
  255. 0 : -1;
  256. if (ret != 0)
  257. {
  258. post_log ("Error at cr2 test %d !\n", i);
  259. }
  260. }
  261. for (i = 0; i < cpu_post_cr_size3 && ret == 0; i++)
  262. {
  263. struct cpu_post_cr_s3 *test = cpu_post_cr_table3 + i;
  264. ulong res;
  265. unsigned long code[] =
  266. {
  267. ASM_MTCR(3),
  268. ASM_MCRF(test->cd, test->cs),
  269. ASM_MFCR(3),
  270. ASM_BLR,
  271. };
  272. cpu_post_exec_11 (code, &res, test->cr);
  273. ret = res == test->res ? 0 : -1;
  274. if (ret != 0)
  275. {
  276. post_log ("Error at cr3 test %d !\n", i);
  277. }
  278. }
  279. for (i = 0; i < cpu_post_cr_size4 && ret == 0; i++)
  280. {
  281. struct cpu_post_cr_s4 *test = cpu_post_cr_table4 + i;
  282. ulong res;
  283. unsigned long code[] =
  284. {
  285. ASM_MTCR(3),
  286. ASM_12F(test->cmd, test->op3, test->op1, test->op2),
  287. ASM_MFCR(3),
  288. ASM_BLR,
  289. };
  290. cpu_post_exec_11 (code, &res, test->cr);
  291. ret = res == test->res ? 0 : -1;
  292. if (ret != 0)
  293. {
  294. post_log ("Error at cr4 test %d !\n", i);
  295. }
  296. }
  297. asm ( "mtcr %0" : : "r" (cr_sav));
  298. if (flag)
  299. enable_interrupts();
  300. return ret;
  301. }
  302. #endif