b.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Branch instructions: b, bl, bc
  11. *
  12. * The first 2 instructions (b, bl) are verified by jumping
  13. * to a fixed address and checking whether control was transferred
  14. * to that very point. For the bl instruction the value of the
  15. * link register is checked as well (using mfspr).
  16. * To verify the bc instruction various combinations of the BI/BO
  17. * fields, the CTR and the condition register values are
  18. * checked. The list of such combinations is pre-built and
  19. * linked in U-Boot at build time.
  20. */
  21. #include <post.h>
  22. #include "cpu_asm.h"
  23. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  24. extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1);
  25. extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
  26. ulong cr);
  27. static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi,
  28. int pjump, int decr, int link, ulong pctr, ulong cr)
  29. {
  30. int ret = 0;
  31. ulong lr = 0;
  32. ulong ctr = pctr;
  33. ulong jump;
  34. unsigned long code[] =
  35. {
  36. ASM_MTCR(6),
  37. ASM_MFLR(6),
  38. ASM_MTCTR(3),
  39. ASM_MTLR(4),
  40. ASM_LI(5, 1),
  41. ASM_3O(cmd, bo, bi, 8),
  42. ASM_LI(5, 0),
  43. ASM_MFCTR(3),
  44. ASM_MFLR(4),
  45. ASM_MTLR(6),
  46. ASM_BLR,
  47. };
  48. cpu_post_exec_31 (code, &ctr, &lr, &jump, cr);
  49. if (ret == 0)
  50. ret = pjump == jump ? 0 : -1;
  51. if (ret == 0)
  52. {
  53. if (decr)
  54. ret = pctr == ctr + 1 ? 0 : -1;
  55. else
  56. ret = pctr == ctr ? 0 : -1;
  57. }
  58. if (ret == 0)
  59. {
  60. if (link)
  61. ret = lr == (ulong) code + 24 ? 0 : -1;
  62. else
  63. ret = lr == 0 ? 0 : -1;
  64. }
  65. return ret;
  66. }
  67. int cpu_post_test_b (void)
  68. {
  69. int ret = 0;
  70. unsigned int i;
  71. int flag = disable_interrupts();
  72. if (ret == 0)
  73. {
  74. ulong code[] =
  75. {
  76. ASM_MFLR(4),
  77. ASM_MTLR(3),
  78. ASM_B(4),
  79. ASM_MFLR(3),
  80. ASM_MTLR(4),
  81. ASM_BLR,
  82. };
  83. ulong res;
  84. cpu_post_exec_11 (code, &res, 0);
  85. ret = res == 0 ? 0 : -1;
  86. if (ret != 0)
  87. {
  88. post_log ("Error at b1 test !\n");
  89. }
  90. }
  91. if (ret == 0)
  92. {
  93. ulong code[] =
  94. {
  95. ASM_MFLR(4),
  96. ASM_MTLR(3),
  97. ASM_BL(4),
  98. ASM_MFLR(3),
  99. ASM_MTLR(4),
  100. ASM_BLR,
  101. };
  102. ulong res;
  103. cpu_post_exec_11 (code, &res, 0);
  104. ret = res == (ulong)code + 12 ? 0 : -1;
  105. if (ret != 0)
  106. {
  107. post_log ("Error at b2 test !\n");
  108. }
  109. }
  110. if (ret == 0)
  111. {
  112. ulong cc, cd;
  113. int cond;
  114. ulong ctr;
  115. int link;
  116. i = 0;
  117. for (cc = 0; cc < 4 && ret == 0; cc++)
  118. {
  119. for (cd = 0; cd < 4 && ret == 0; cd++)
  120. {
  121. for (link = 0; link <= 1 && ret == 0; link++)
  122. {
  123. for (cond = 0; cond <= 1 && ret == 0; cond++)
  124. {
  125. for (ctr = 1; ctr <= 2 && ret == 0; ctr++)
  126. {
  127. int decr = cd < 2;
  128. int cr = cond ? 0x80000000 : 0x00000000;
  129. int jumpc = cc >= 2 ||
  130. (cc == 0 && !cond) ||
  131. (cc == 1 && cond);
  132. int jumpd = cd >= 2 ||
  133. (cd == 0 && ctr != 1) ||
  134. (cd == 1 && ctr == 1);
  135. int jump = jumpc && jumpd;
  136. ret = cpu_post_test_bc (link ? OP_BCL : OP_BC,
  137. (cc << 3) + (cd << 1), 0, jump, decr, link,
  138. ctr, cr);
  139. if (ret != 0)
  140. {
  141. post_log ("Error at b3 test %d !\n", i);
  142. }
  143. i++;
  144. }
  145. }
  146. }
  147. }
  148. }
  149. }
  150. if (flag)
  151. enable_interrupts();
  152. return ret;
  153. }
  154. #endif