asm.S 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
  4. */
  5. #include <config.h>
  6. #include <post.h>
  7. #include <ppc_asm.tmpl>
  8. #include <ppc_defs.h>
  9. #include <asm/cache.h>
  10. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  11. /* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
  12. .global cpu_post_exec_02
  13. cpu_post_exec_02:
  14. isync
  15. mflr r0
  16. stwu r0, -4(r1)
  17. subi r1, r1, 104
  18. stmw r6, 0(r1)
  19. mtlr r3
  20. mr r3, r4
  21. mr r4, r5
  22. blrl
  23. lmw r6, 0(r1)
  24. addi r1, r1, 104
  25. lwz r0, 0(r1)
  26. addi r1, r1, 4
  27. mtlr r0
  28. blr
  29. /* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
  30. .global cpu_post_exec_04
  31. cpu_post_exec_04:
  32. isync
  33. mflr r0
  34. stwu r0, -4(r1)
  35. subi r1, r1, 96
  36. stmw r8, 0(r1)
  37. mtlr r3
  38. mr r3, r4
  39. mr r4, r5
  40. mr r5, r6
  41. mtxer r7
  42. blrl
  43. lmw r8, 0(r1)
  44. addi r1, r1, 96
  45. lwz r0, 0(r1)
  46. addi r1, r1, 4
  47. mtlr r0
  48. blr
  49. /* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
  50. .global cpu_post_exec_12
  51. cpu_post_exec_12:
  52. isync
  53. mflr r0
  54. stwu r0, -4(r1)
  55. stwu r4, -4(r1)
  56. mtlr r3
  57. mr r3, r5
  58. mr r4, r6
  59. blrl
  60. lwz r4, 0(r1)
  61. stw r3, 0(r4)
  62. lwz r0, 4(r1)
  63. addi r1, r1, 8
  64. mtlr r0
  65. blr
  66. /* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
  67. .global cpu_post_exec_11
  68. cpu_post_exec_11:
  69. isync
  70. mflr r0
  71. stwu r0, -4(r1)
  72. stwu r4, -4(r1)
  73. mtlr r3
  74. mr r3, r5
  75. blrl
  76. lwz r4, 0(r1)
  77. stw r3, 0(r4)
  78. lwz r0, 4(r1)
  79. addi r1, r1, 8
  80. mtlr r0
  81. blr
  82. /* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
  83. .global cpu_post_exec_21
  84. cpu_post_exec_21:
  85. isync
  86. mflr r0
  87. stwu r0, -4(r1)
  88. stwu r4, -4(r1)
  89. stwu r5, -4(r1)
  90. li r0, 0
  91. mtxer r0
  92. lwz r0, 0(r4)
  93. mtcr r0
  94. mtlr r3
  95. mr r3, r6
  96. blrl
  97. mfcr r0
  98. lwz r4, 4(r1)
  99. stw r0, 0(r4)
  100. lwz r4, 0(r1)
  101. stw r3, 0(r4)
  102. lwz r0, 8(r1)
  103. addi r1, r1, 12
  104. mtlr r0
  105. blr
  106. /* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
  107. ulong op2); */
  108. .global cpu_post_exec_22
  109. cpu_post_exec_22:
  110. isync
  111. mflr r0
  112. stwu r0, -4(r1)
  113. stwu r4, -4(r1)
  114. stwu r5, -4(r1)
  115. li r0, 0
  116. mtxer r0
  117. lwz r0, 0(r4)
  118. mtcr r0
  119. mtlr r3
  120. mr r3, r6
  121. mr r4, r7
  122. blrl
  123. mfcr r0
  124. lwz r4, 4(r1)
  125. stw r0, 0(r4)
  126. lwz r4, 0(r1)
  127. stw r3, 0(r4)
  128. lwz r0, 8(r1)
  129. addi r1, r1, 12
  130. mtlr r0
  131. blr
  132. /* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
  133. .global cpu_post_exec_12w
  134. cpu_post_exec_12w:
  135. isync
  136. mflr r0
  137. stwu r0, -4(r1)
  138. stwu r4, -4(r1)
  139. mtlr r3
  140. lwz r3, 0(r4)
  141. mr r4, r5
  142. mr r5, r6
  143. blrl
  144. lwz r4, 0(r1)
  145. stw r3, 0(r4)
  146. lwz r0, 4(r1)
  147. addi r1, r1, 8
  148. mtlr r0
  149. blr
  150. /* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
  151. .global cpu_post_exec_11w
  152. cpu_post_exec_11w:
  153. isync
  154. mflr r0
  155. stwu r0, -4(r1)
  156. stwu r4, -4(r1)
  157. mtlr r3
  158. lwz r3, 0(r4)
  159. mr r4, r5
  160. blrl
  161. lwz r4, 0(r1)
  162. stw r3, 0(r4)
  163. lwz r0, 4(r1)
  164. addi r1, r1, 8
  165. mtlr r0
  166. blr
  167. /* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
  168. .global cpu_post_exec_22w
  169. cpu_post_exec_22w:
  170. isync
  171. mflr r0
  172. stwu r0, -4(r1)
  173. stwu r4, -4(r1)
  174. stwu r6, -4(r1)
  175. mtlr r3
  176. lwz r3, 0(r4)
  177. mr r4, r5
  178. blrl
  179. lwz r4, 4(r1)
  180. stw r3, 0(r4)
  181. lwz r4, 0(r1)
  182. stw r5, 0(r4)
  183. lwz r0, 8(r1)
  184. addi r1, r1, 12
  185. mtlr r0
  186. blr
  187. /* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
  188. .global cpu_post_exec_21w
  189. cpu_post_exec_21w:
  190. isync
  191. mflr r0
  192. stwu r0, -4(r1)
  193. stwu r4, -4(r1)
  194. stwu r5, -4(r1)
  195. mtlr r3
  196. lwz r3, 0(r4)
  197. blrl
  198. lwz r5, 4(r1)
  199. stw r3, 0(r5)
  200. lwz r5, 0(r1)
  201. stw r4, 0(r5)
  202. lwz r0, 8(r1)
  203. addi r1, r1, 12
  204. mtlr r0
  205. blr
  206. /* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
  207. .global cpu_post_exec_21x
  208. cpu_post_exec_21x:
  209. isync
  210. mflr r0
  211. stwu r0, -4(r1)
  212. stwu r4, -4(r1)
  213. stwu r5, -4(r1)
  214. mtlr r3
  215. mr r3, r6
  216. blrl
  217. lwz r5, 4(r1)
  218. stw r3, 0(r5)
  219. lwz r5, 0(r1)
  220. stw r4, 0(r5)
  221. lwz r0, 8(r1)
  222. addi r1, r1, 12
  223. mtlr r0
  224. blr
  225. /* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
  226. ulong cr); */
  227. .global cpu_post_exec_31
  228. cpu_post_exec_31:
  229. isync
  230. mflr r0
  231. stwu r0, -4(r1)
  232. stwu r4, -4(r1)
  233. stwu r5, -4(r1)
  234. stwu r6, -4(r1)
  235. mtlr r3
  236. lwz r3, 0(r4)
  237. lwz r4, 0(r5)
  238. mr r6, r7
  239. mfcr r7
  240. blrl
  241. mtcr r7
  242. lwz r7, 8(r1)
  243. stw r3, 0(r7)
  244. lwz r7, 4(r1)
  245. stw r4, 0(r7)
  246. lwz r7, 0(r1)
  247. stw r5, 0(r7)
  248. lwz r0, 12(r1)
  249. addi r1, r1, 16
  250. mtlr r0
  251. blr
  252. /* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */
  253. .global cpu_post_complex_1_asm
  254. cpu_post_complex_1_asm:
  255. li r9,0
  256. cmpw r9,r7
  257. bge cpu_post_complex_1_done
  258. mtctr r7
  259. cpu_post_complex_1_loop:
  260. mullw r0,r3,r4
  261. subf r0,r5,r0
  262. divw r0,r0,r6
  263. add r9,r9,r0
  264. bdnz cpu_post_complex_1_loop
  265. cpu_post_complex_1_done:
  266. mr r3,r9
  267. blr
  268. /* int cpu_post_complex_2_asm (int x, int n); */
  269. .global cpu_post_complex_2_asm
  270. cpu_post_complex_2_asm:
  271. mr. r0,r4
  272. mtctr r0
  273. mr r0,r3
  274. li r3,1
  275. li r4,1
  276. blelr
  277. cpu_post_complex_2_loop:
  278. mullw r3,r3,r0
  279. add r3,r3,r4
  280. bdnz cpu_post_complex_2_loop
  281. blr
  282. #endif