memory.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <asm/global_data.h>
  9. /* Memory test
  10. *
  11. * General observations:
  12. * o The recommended test sequence is to test the data lines: if they are
  13. * broken, nothing else will work properly. Then test the address
  14. * lines. Finally, test the cells in the memory now that the test
  15. * program knows that the address and data lines work properly.
  16. * This sequence also helps isolate and identify what is faulty.
  17. *
  18. * o For the address line test, it is a good idea to use the base
  19. * address of the lowest memory location, which causes a '1' bit to
  20. * walk through a field of zeros on the address lines and the highest
  21. * memory location, which causes a '0' bit to walk through a field of
  22. * '1's on the address line.
  23. *
  24. * o Floating buses can fool memory tests if the test routine writes
  25. * a value and then reads it back immediately. The problem is, the
  26. * write will charge the residual capacitance on the data bus so the
  27. * bus retains its state briefely. When the test program reads the
  28. * value back immediately, the capacitance of the bus can allow it
  29. * to read back what was written, even though the memory circuitry
  30. * is broken. To avoid this, the test program should write a test
  31. * pattern to the target location, write a different pattern elsewhere
  32. * to charge the residual capacitance in a differnt manner, then read
  33. * the target location back.
  34. *
  35. * o Always read the target location EXACTLY ONCE and save it in a local
  36. * variable. The problem with reading the target location more than
  37. * once is that the second and subsequent reads may work properly,
  38. * resulting in a failed test that tells the poor technician that
  39. * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
  40. * doesn't help him one bit and causes puzzled phone calls. Been there,
  41. * done that.
  42. *
  43. * Data line test:
  44. * ---------------
  45. * This tests data lines for shorts and opens by forcing adjacent data
  46. * to opposite states. Because the data lines could be routed in an
  47. * arbitrary manner the must ensure test patterns ensure that every case
  48. * is tested. By using the following series of binary patterns every
  49. * combination of adjacent bits is test regardless of routing.
  50. *
  51. * ...101010101010101010101010
  52. * ...110011001100110011001100
  53. * ...111100001111000011110000
  54. * ...111111110000000011111111
  55. *
  56. * Carrying this out, gives us six hex patterns as follows:
  57. *
  58. * 0xaaaaaaaaaaaaaaaa
  59. * 0xcccccccccccccccc
  60. * 0xf0f0f0f0f0f0f0f0
  61. * 0xff00ff00ff00ff00
  62. * 0xffff0000ffff0000
  63. * 0xffffffff00000000
  64. *
  65. * To test for short and opens to other signals on our boards, we
  66. * simply test with the 1's complemnt of the paterns as well, resulting
  67. * in twelve patterns total.
  68. *
  69. * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
  70. * written to a different address in case the data lines are floating.
  71. * Thus, if a byte lane fails, you will see part of the special
  72. * pattern in that byte lane when the test runs. For example, if the
  73. * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
  74. * (for the 'a' test pattern).
  75. *
  76. * Address line test:
  77. * ------------------
  78. * This function performs a test to verify that all the address lines
  79. * hooked up to the RAM work properly. If there is an address line
  80. * fault, it usually shows up as two different locations in the address
  81. * map (related by the faulty address line) mapping to one physical
  82. * memory storage location. The artifact that shows up is writing to
  83. * the first location "changes" the second location.
  84. *
  85. * To test all address lines, we start with the given base address and
  86. * xor the address with a '1' bit to flip one address line. For each
  87. * test, we shift the '1' bit left to test the next address line.
  88. *
  89. * In the actual code, we start with address sizeof(ulong) since our
  90. * test pattern we use is a ulong and thus, if we tried to test lower
  91. * order address bits, it wouldn't work because our pattern would
  92. * overwrite itself.
  93. *
  94. * Example for a 4 bit address space with the base at 0000:
  95. * 0000 <- base
  96. * 0001 <- test 1
  97. * 0010 <- test 2
  98. * 0100 <- test 3
  99. * 1000 <- test 4
  100. * Example for a 4 bit address space with the base at 0010:
  101. * 0010 <- base
  102. * 0011 <- test 1
  103. * 0000 <- (below the base address, skipped)
  104. * 0110 <- test 2
  105. * 1010 <- test 3
  106. *
  107. * The test locations are successively tested to make sure that they are
  108. * not "mirrored" onto the base address due to a faulty address line.
  109. * Note that the base and each test location are related by one address
  110. * line flipped. Note that the base address need not be all zeros.
  111. *
  112. * Memory tests 1-4:
  113. * -----------------
  114. * These tests verify RAM using sequential writes and reads
  115. * to/from RAM. There are several test cases that use different patterns to
  116. * verify RAM. Each test case fills a region of RAM with one pattern and
  117. * then reads the region back and compares its contents with the pattern.
  118. * The following patterns are used:
  119. *
  120. * 1a) zero pattern (0x00000000)
  121. * 1b) negative pattern (0xffffffff)
  122. * 1c) checkerboard pattern (0x55555555)
  123. * 1d) checkerboard pattern (0xaaaaaaaa)
  124. * 2) bit-flip pattern ((1 << (offset % 32))
  125. * 3) address pattern (offset)
  126. * 4) address pattern (~offset)
  127. *
  128. * Being run in normal mode, the test verifies only small 4Kb
  129. * regions of RAM around each 1Mb boundary. For example, for 64Mb
  130. * RAM the following areas are verified: 0x00000000-0x00000800,
  131. * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
  132. * 0x04000000. If the test is run in slow-test mode, it verifies
  133. * the whole RAM.
  134. */
  135. #include <post.h>
  136. #include <watchdog.h>
  137. #if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS)
  138. DECLARE_GLOBAL_DATA_PTR;
  139. /*
  140. * Define INJECT_*_ERRORS for testing error detection in the presence of
  141. * _good_ hardware.
  142. */
  143. #undef INJECT_DATA_ERRORS
  144. #undef INJECT_ADDRESS_ERRORS
  145. #ifdef INJECT_DATA_ERRORS
  146. #warning "Injecting data line errors for testing purposes"
  147. #endif
  148. #ifdef INJECT_ADDRESS_ERRORS
  149. #warning "Injecting address line errors for testing purposes"
  150. #endif
  151. /*
  152. * This function performs a double word move from the data at
  153. * the source pointer to the location at the destination pointer.
  154. * This is helpful for testing memory on processors which have a 64 bit
  155. * wide data bus.
  156. *
  157. * On those PowerPC with FPU, use assembly and a floating point move:
  158. * this does a 64 bit move.
  159. *
  160. * For other processors, let the compiler generate the best code it can.
  161. */
  162. static void move64(const unsigned long long *src, unsigned long long *dest)
  163. {
  164. *dest = *src;
  165. }
  166. /*
  167. * This is 64 bit wide test patterns. Note that they reside in ROM
  168. * (which presumably works) and the tests write them to RAM which may
  169. * not work.
  170. *
  171. * The "otherpattern" is written to drive the data bus to values other
  172. * than the test pattern. This is for detecting floating bus lines.
  173. *
  174. */
  175. const static unsigned long long pattern[] = {
  176. 0xaaaaaaaaaaaaaaaaULL,
  177. 0xccccccccccccccccULL,
  178. 0xf0f0f0f0f0f0f0f0ULL,
  179. 0xff00ff00ff00ff00ULL,
  180. 0xffff0000ffff0000ULL,
  181. 0xffffffff00000000ULL,
  182. 0x00000000ffffffffULL,
  183. 0x0000ffff0000ffffULL,
  184. 0x00ff00ff00ff00ffULL,
  185. 0x0f0f0f0f0f0f0f0fULL,
  186. 0x3333333333333333ULL,
  187. 0x5555555555555555ULL
  188. };
  189. const unsigned long long otherpattern = 0x0123456789abcdefULL;
  190. static int memory_post_dataline(unsigned long long * pmem)
  191. {
  192. unsigned long long temp64 = 0;
  193. int num_patterns = ARRAY_SIZE(pattern);
  194. int i;
  195. unsigned int hi, lo, pathi, patlo;
  196. int ret = 0;
  197. for ( i = 0; i < num_patterns; i++) {
  198. move64(&(pattern[i]), pmem++);
  199. /*
  200. * Put a different pattern on the data lines: otherwise they
  201. * may float long enough to read back what we wrote.
  202. */
  203. move64(&otherpattern, pmem--);
  204. move64(pmem, &temp64);
  205. #ifdef INJECT_DATA_ERRORS
  206. temp64 ^= 0x00008000;
  207. #endif
  208. if (temp64 != pattern[i]){
  209. pathi = (pattern[i]>>32) & 0xffffffff;
  210. patlo = pattern[i] & 0xffffffff;
  211. hi = (temp64>>32) & 0xffffffff;
  212. lo = temp64 & 0xffffffff;
  213. post_log("Memory (data line) error at %08x, "
  214. "wrote %08x%08x, read %08x%08x !\n",
  215. pmem, pathi, patlo, hi, lo);
  216. ret = -1;
  217. }
  218. }
  219. return ret;
  220. }
  221. static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
  222. {
  223. ulong *target;
  224. ulong *end;
  225. ulong readback;
  226. ulong xor;
  227. int ret = 0;
  228. end = (ulong *)((ulong)base + size); /* pointer arith! */
  229. xor = 0;
  230. for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
  231. target = (ulong *)((ulong)testaddr ^ xor);
  232. if((target >= base) && (target < end)) {
  233. *testaddr = ~*target;
  234. readback = *target;
  235. #ifdef INJECT_ADDRESS_ERRORS
  236. if(xor == 0x00008000) {
  237. readback = *testaddr;
  238. }
  239. #endif
  240. if(readback == *testaddr) {
  241. post_log("Memory (address line) error at %08x<->%08x, "
  242. "XOR value %08x !\n",
  243. testaddr, target, xor);
  244. ret = -1;
  245. }
  246. }
  247. }
  248. return ret;
  249. }
  250. static int memory_post_test1(unsigned long start,
  251. unsigned long size,
  252. unsigned long val)
  253. {
  254. unsigned long i;
  255. ulong *mem = (ulong *) start;
  256. ulong readback;
  257. int ret = 0;
  258. for (i = 0; i < size / sizeof (ulong); i++) {
  259. mem[i] = val;
  260. if (i % 1024 == 0)
  261. WATCHDOG_RESET();
  262. }
  263. for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
  264. readback = mem[i];
  265. if (readback != val) {
  266. post_log("Memory error at %08x, "
  267. "wrote %08x, read %08x !\n",
  268. mem + i, val, readback);
  269. ret = -1;
  270. break;
  271. }
  272. if (i % 1024 == 0)
  273. WATCHDOG_RESET();
  274. }
  275. return ret;
  276. }
  277. static int memory_post_test2(unsigned long start, unsigned long size)
  278. {
  279. unsigned long i;
  280. ulong *mem = (ulong *) start;
  281. ulong readback;
  282. int ret = 0;
  283. for (i = 0; i < size / sizeof (ulong); i++) {
  284. mem[i] = 1 << (i % 32);
  285. if (i % 1024 == 0)
  286. WATCHDOG_RESET();
  287. }
  288. for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
  289. readback = mem[i];
  290. if (readback != (1 << (i % 32))) {
  291. post_log("Memory error at %08x, "
  292. "wrote %08x, read %08x !\n",
  293. mem + i, 1 << (i % 32), readback);
  294. ret = -1;
  295. break;
  296. }
  297. if (i % 1024 == 0)
  298. WATCHDOG_RESET();
  299. }
  300. return ret;
  301. }
  302. static int memory_post_test3(unsigned long start, unsigned long size)
  303. {
  304. unsigned long i;
  305. ulong *mem = (ulong *) start;
  306. ulong readback;
  307. int ret = 0;
  308. for (i = 0; i < size / sizeof (ulong); i++) {
  309. mem[i] = i;
  310. if (i % 1024 == 0)
  311. WATCHDOG_RESET();
  312. }
  313. for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
  314. readback = mem[i];
  315. if (readback != i) {
  316. post_log("Memory error at %08x, "
  317. "wrote %08x, read %08x !\n",
  318. mem + i, i, readback);
  319. ret = -1;
  320. break;
  321. }
  322. if (i % 1024 == 0)
  323. WATCHDOG_RESET();
  324. }
  325. return ret;
  326. }
  327. static int memory_post_test4(unsigned long start, unsigned long size)
  328. {
  329. unsigned long i;
  330. ulong *mem = (ulong *) start;
  331. ulong readback;
  332. int ret = 0;
  333. for (i = 0; i < size / sizeof (ulong); i++) {
  334. mem[i] = ~i;
  335. if (i % 1024 == 0)
  336. WATCHDOG_RESET();
  337. }
  338. for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
  339. readback = mem[i];
  340. if (readback != ~i) {
  341. post_log("Memory error at %08x, "
  342. "wrote %08x, read %08x !\n",
  343. mem + i, ~i, readback);
  344. ret = -1;
  345. break;
  346. }
  347. if (i % 1024 == 0)
  348. WATCHDOG_RESET();
  349. }
  350. return ret;
  351. }
  352. static int memory_post_test_lines(unsigned long start, unsigned long size)
  353. {
  354. int ret = 0;
  355. ret = memory_post_dataline((unsigned long long *)start);
  356. WATCHDOG_RESET();
  357. if (!ret)
  358. ret = memory_post_addrline((ulong *)start, (ulong *)start,
  359. size);
  360. WATCHDOG_RESET();
  361. if (!ret)
  362. ret = memory_post_addrline((ulong *)(start+size-8),
  363. (ulong *)start, size);
  364. WATCHDOG_RESET();
  365. return ret;
  366. }
  367. static int memory_post_test_patterns(unsigned long start, unsigned long size)
  368. {
  369. int ret = 0;
  370. ret = memory_post_test1(start, size, 0x00000000);
  371. WATCHDOG_RESET();
  372. if (!ret)
  373. ret = memory_post_test1(start, size, 0xffffffff);
  374. WATCHDOG_RESET();
  375. if (!ret)
  376. ret = memory_post_test1(start, size, 0x55555555);
  377. WATCHDOG_RESET();
  378. if (!ret)
  379. ret = memory_post_test1(start, size, 0xaaaaaaaa);
  380. WATCHDOG_RESET();
  381. if (!ret)
  382. ret = memory_post_test2(start, size);
  383. WATCHDOG_RESET();
  384. if (!ret)
  385. ret = memory_post_test3(start, size);
  386. WATCHDOG_RESET();
  387. if (!ret)
  388. ret = memory_post_test4(start, size);
  389. WATCHDOG_RESET();
  390. return ret;
  391. }
  392. static int memory_post_test_regions(unsigned long start, unsigned long size)
  393. {
  394. unsigned long i;
  395. int ret = 0;
  396. for (i = 0; i < (size >> 20) && (!ret); i++) {
  397. if (!ret)
  398. ret = memory_post_test_patterns(start + (i << 20),
  399. 0x800);
  400. if (!ret)
  401. ret = memory_post_test_patterns(start + (i << 20) +
  402. 0xff800, 0x800);
  403. }
  404. return ret;
  405. }
  406. static int memory_post_tests(unsigned long start, unsigned long size)
  407. {
  408. int ret = 0;
  409. ret = memory_post_test_lines(start, size);
  410. if (!ret)
  411. ret = memory_post_test_patterns(start, size);
  412. return ret;
  413. }
  414. /*
  415. * !! this is only valid, if you have contiguous memory banks !!
  416. */
  417. __attribute__((weak))
  418. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  419. {
  420. struct bd_info *bd = gd->bd;
  421. *vstart = CONFIG_SYS_SDRAM_BASE;
  422. *size = (gd->ram_size >= 256 << 20 ?
  423. 256 << 20 : gd->ram_size) - (1 << 20);
  424. /* Limit area to be tested with the board info struct */
  425. if ((*vstart) + (*size) > (ulong)bd)
  426. *size = (ulong)bd - *vstart;
  427. return 0;
  428. }
  429. __attribute__((weak))
  430. int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  431. {
  432. return 1;
  433. }
  434. __attribute__((weak))
  435. int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  436. {
  437. return 0;
  438. }
  439. __attribute__((weak))
  440. void arch_memory_failure_handle(void)
  441. {
  442. return;
  443. }
  444. int memory_regions_post_test(int flags)
  445. {
  446. int ret = 0;
  447. phys_addr_t phys_offset = 0;
  448. u32 memsize, vstart;
  449. arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
  450. ret = memory_post_test_lines(vstart, memsize);
  451. if (!ret)
  452. ret = memory_post_test_regions(vstart, memsize);
  453. return ret;
  454. }
  455. int memory_post_test(int flags)
  456. {
  457. int ret = 0;
  458. phys_addr_t phys_offset = 0;
  459. u32 memsize, vstart;
  460. arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
  461. do {
  462. if (flags & POST_SLOWTEST) {
  463. ret = memory_post_tests(vstart, memsize);
  464. } else { /* POST_NORMAL */
  465. ret = memory_post_test_regions(vstart, memsize);
  466. }
  467. } while (!ret &&
  468. !arch_memory_test_advance(&vstart, &memsize, &phys_offset));
  469. arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
  470. if (ret)
  471. arch_memory_failure_handle();
  472. return ret;
  473. }
  474. #endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */