ulp_wdog.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/imx-regs.h>
  9. /*
  10. * MX7ULP WDOG Register Map
  11. */
  12. struct wdog_regs {
  13. u32 cs;
  14. u32 cnt;
  15. u32 toval;
  16. u32 win;
  17. };
  18. #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
  19. #define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
  20. #endif
  21. #define REFRESH_WORD0 0xA602 /* 1st refresh word */
  22. #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
  23. #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
  24. #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
  25. #define WDGCS_WDGE BIT(7)
  26. #define WDGCS_WDGUPDATE BIT(5)
  27. #define WDGCS_RCS BIT(10)
  28. #define WDGCS_ULK BIT(11)
  29. #define WDGCS_FLG BIT(14)
  30. #define WDG_BUS_CLK (0x0)
  31. #define WDG_LPO_CLK (0x1)
  32. #define WDG_32KHZ_CLK (0x2)
  33. #define WDG_EXT_CLK (0x3)
  34. void hw_watchdog_set_timeout(u16 val)
  35. {
  36. /* setting timeout value */
  37. struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
  38. writel(val, &wdog->toval);
  39. }
  40. void hw_watchdog_reset(void)
  41. {
  42. struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
  43. dmb();
  44. __raw_writel(REFRESH_WORD0, &wdog->cnt);
  45. __raw_writel(REFRESH_WORD1, &wdog->cnt);
  46. dmb();
  47. }
  48. void hw_watchdog_init(void)
  49. {
  50. struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
  51. dmb();
  52. __raw_writel(UNLOCK_WORD0, &wdog->cnt);
  53. __raw_writel(UNLOCK_WORD1, &wdog->cnt);
  54. dmb();
  55. /* Wait WDOG Unlock */
  56. while (!(readl(&wdog->cs) & WDGCS_ULK))
  57. ;
  58. hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
  59. writel(0, &wdog->win);
  60. /* setting 1-kHz clock source, enable counter running, and clear interrupt */
  61. writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs);
  62. /* Wait WDOG reconfiguration */
  63. while (!(readl(&wdog->cs) & WDGCS_RCS))
  64. ;
  65. hw_watchdog_reset();
  66. }
  67. void reset_cpu(void)
  68. {
  69. struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
  70. dmb();
  71. __raw_writel(UNLOCK_WORD0, &wdog->cnt);
  72. __raw_writel(UNLOCK_WORD1, &wdog->cnt);
  73. dmb();
  74. /* Wait WDOG Unlock */
  75. while (!(readl(&wdog->cs) & WDGCS_ULK))
  76. ;
  77. hw_watchdog_set_timeout(5); /* 5ms timeout */
  78. writel(0, &wdog->win);
  79. /* enable counter running */
  80. writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
  81. /* Wait WDOG reconfiguration */
  82. while (!(readl(&wdog->cs) & WDGCS_RCS))
  83. ;
  84. hw_watchdog_reset();
  85. while (1);
  86. }