omap_wdt.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * omap_wdt.c
  4. *
  5. * (C) Copyright 2013
  6. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  7. *
  8. * Based on:
  9. *
  10. * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
  11. *
  12. * commit 2d991a164a61858012651e13c59521975504e260
  13. * Author: Bill Pemberton <wfp5p@virginia.edu>
  14. * Date: Mon Nov 19 13:21:41 2012 -0500
  15. *
  16. * watchdog: remove use of __devinit
  17. *
  18. * CONFIG_HOTPLUG is going away as an option so __devinit is no longer
  19. * needed.
  20. *
  21. * Author: MontaVista Software, Inc.
  22. * <gdavis@mvista.com> or <source@mvista.com>
  23. *
  24. * History:
  25. *
  26. * 20030527: George G. Davis <gdavis@mvista.com>
  27. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  28. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  29. * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
  30. *
  31. * Copyright (c) 2004 Texas Instruments.
  32. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  33. * 2. Ported to 2.6 kernel
  34. *
  35. * Copyright (c) 2005 David Brownell
  36. * Use the driver model and standard identifiers; handle bigger timeouts.
  37. */
  38. #include <common.h>
  39. #include <log.h>
  40. #include <watchdog.h>
  41. #include <asm/arch/hardware.h>
  42. #include <asm/io.h>
  43. #include <asm/processor.h>
  44. #include <asm/arch/cpu.h>
  45. #include <wdt.h>
  46. #include <dm.h>
  47. #include <errno.h>
  48. /* Hardware timeout in seconds */
  49. #define WDT_HW_TIMEOUT 60
  50. #if !CONFIG_IS_ENABLED(WDT)
  51. static unsigned int wdt_trgr_pattern = 0x1234;
  52. void hw_watchdog_reset(void)
  53. {
  54. struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
  55. /*
  56. * Somebody just triggered watchdog reset and write to WTGR register
  57. * is in progress. It is resetting right now, no need to trigger it
  58. * again
  59. */
  60. if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
  61. return;
  62. wdt_trgr_pattern = ~wdt_trgr_pattern;
  63. writel(wdt_trgr_pattern, &wdt->wdtwtgr);
  64. /*
  65. * Don't wait for posted write to complete, i.e. don't check
  66. * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
  67. * WTGR register outside of this func, and if entering it
  68. * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
  69. * was just triggered. This prevents us from wasting time in busy
  70. * polling of WDT_WWPS_PEND_WTGR bit.
  71. */
  72. }
  73. static int omap_wdt_set_timeout(unsigned int timeout)
  74. {
  75. struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
  76. u32 pre_margin = GET_WLDR_VAL(timeout);
  77. /* just count up at 32 KHz */
  78. while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
  79. ;
  80. writel(pre_margin, &wdt->wdtwldr);
  81. while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
  82. ;
  83. return 0;
  84. }
  85. void hw_watchdog_disable(void)
  86. {
  87. struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
  88. /*
  89. * Disable watchdog
  90. */
  91. writel(0xAAAA, &wdt->wdtwspr);
  92. while (readl(&wdt->wdtwwps) != 0x0)
  93. ;
  94. writel(0x5555, &wdt->wdtwspr);
  95. while (readl(&wdt->wdtwwps) != 0x0)
  96. ;
  97. }
  98. void hw_watchdog_init(void)
  99. {
  100. struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
  101. /*
  102. * Make sure the watchdog is disabled. This is unfortunately required
  103. * because writing to various registers with the watchdog running has no
  104. * effect.
  105. */
  106. hw_watchdog_disable();
  107. /* initialize prescaler */
  108. while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
  109. ;
  110. writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr);
  111. while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
  112. ;
  113. omap_wdt_set_timeout(WDT_HW_TIMEOUT);
  114. /* Sequence to enable the watchdog */
  115. writel(0xBBBB, &wdt->wdtwspr);
  116. while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
  117. ;
  118. writel(0x4444, &wdt->wdtwspr);
  119. while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
  120. ;
  121. }
  122. void watchdog_reset(void)
  123. {
  124. hw_watchdog_reset();
  125. }
  126. #else
  127. static int omap3_wdt_reset(struct udevice *dev)
  128. {
  129. struct omap3_wdt_priv *priv = dev_get_priv(dev);
  130. /*
  131. * Somebody just triggered watchdog reset and write to WTGR register
  132. * is in progress. It is resetting right now, no need to trigger it
  133. * again
  134. */
  135. if ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
  136. return 0;
  137. priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
  138. writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
  139. /*
  140. * Don't wait for posted write to complete, i.e. don't check
  141. * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
  142. * WTGR register outside of this func, and if entering it
  143. * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
  144. * was just triggered. This prevents us from wasting time in busy
  145. * polling of WDT_WWPS_PEND_WTGR bit.
  146. */
  147. return 0;
  148. }
  149. static int omap3_wdt_stop(struct udevice *dev)
  150. {
  151. struct omap3_wdt_priv *priv = dev_get_priv(dev);
  152. /* disable watchdog */
  153. writel(0xAAAA, &priv->regs->wdtwspr);
  154. while (readl(&priv->regs->wdtwwps) != 0x0)
  155. ;
  156. writel(0x5555, &priv->regs->wdtwspr);
  157. while (readl(&priv->regs->wdtwwps) != 0x0)
  158. ;
  159. return 0;
  160. }
  161. static int omap3_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
  162. {
  163. struct omap3_wdt_priv *priv = dev_get_priv(dev);
  164. u32 pre_margin = GET_WLDR_VAL(timeout_ms / 1000);
  165. /*
  166. * Make sure the watchdog is disabled. This is unfortunately required
  167. * because writing to various registers with the watchdog running has
  168. * no effect.
  169. */
  170. omap3_wdt_stop(dev);
  171. /* initialize prescaler */
  172. while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
  173. ;
  174. writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &priv->regs->wdtwclr);
  175. while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
  176. ;
  177. /* just count up at 32 KHz */
  178. while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
  179. ;
  180. writel(pre_margin, &priv->regs->wdtwldr);
  181. while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
  182. ;
  183. /* Sequence to enable the watchdog */
  184. writel(0xBBBB, &priv->regs->wdtwspr);
  185. while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
  186. ;
  187. writel(0x4444, &priv->regs->wdtwspr);
  188. while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
  189. ;
  190. /* Trigger the watchdog to actually reload the counter. */
  191. while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
  192. ;
  193. priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
  194. writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
  195. while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
  196. ;
  197. return 0;
  198. }
  199. static int omap3_wdt_probe(struct udevice *dev)
  200. {
  201. struct omap3_wdt_priv *priv = dev_get_priv(dev);
  202. priv->regs = dev_read_addr_ptr(dev);
  203. if (!priv->regs)
  204. return -EINVAL;
  205. priv->wdt_trgr_pattern = 0x1234;
  206. debug("%s: Probing wdt%u\n", __func__, dev_seq(dev));
  207. return 0;
  208. }
  209. static const struct wdt_ops omap3_wdt_ops = {
  210. .start = omap3_wdt_start,
  211. .stop = omap3_wdt_stop,
  212. .reset = omap3_wdt_reset,
  213. };
  214. static const struct udevice_id omap3_wdt_ids[] = {
  215. { .compatible = "ti,omap3-wdt" },
  216. { }
  217. };
  218. U_BOOT_DRIVER(omap3_wdt) = {
  219. .name = "omap3_wdt",
  220. .id = UCLASS_WDT,
  221. .of_match = omap3_wdt_ids,
  222. .ops = &omap3_wdt_ops,
  223. .probe = omap3_wdt_probe,
  224. .priv_auto = sizeof(struct omap3_wdt_priv),
  225. };
  226. #endif /* !CONFIG_IS_ENABLED(WDT) */