mt7620_wdt.c 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. *
  7. * Watchdog timer for MT7620 and earlier SoCs
  8. */
  9. #include <div64.h>
  10. #include <dm.h>
  11. #include <reset.h>
  12. #include <wdt.h>
  13. #include <linux/bitops.h>
  14. #include <linux/io.h>
  15. struct mt7620_wdt {
  16. void __iomem *regs;
  17. u64 timeout;
  18. };
  19. #define TIMER_FREQ 40000000
  20. #define TIMER_MASK 0xffff
  21. #define TIMER_PRESCALE 65536
  22. #define TIMER_LOAD 0x00
  23. #define TIMER_CTL 0x08
  24. #define TIMER_ENABLE BIT(7)
  25. #define TIMER_MODE_SHIFT 4
  26. #define TIMER_MODE_WDT 3
  27. #define TIMER_PRESCALE_SHIFT 0
  28. #define TIMER_PRESCALE_65536 15
  29. static void mt7620_wdt_ping(struct mt7620_wdt *priv)
  30. {
  31. u64 val;
  32. val = (TIMER_FREQ / TIMER_PRESCALE) * priv->timeout;
  33. do_div(val, 1000);
  34. if (val > TIMER_MASK)
  35. val = TIMER_MASK;
  36. writel(val, priv->regs + TIMER_LOAD);
  37. }
  38. static int mt7620_wdt_start(struct udevice *dev, u64 ms, ulong flags)
  39. {
  40. struct mt7620_wdt *priv = dev_get_priv(dev);
  41. priv->timeout = ms;
  42. mt7620_wdt_ping(priv);
  43. writel(TIMER_ENABLE | (TIMER_MODE_WDT << TIMER_MODE_SHIFT) |
  44. (TIMER_PRESCALE_65536 << TIMER_PRESCALE_SHIFT),
  45. priv->regs + TIMER_CTL);
  46. return 0;
  47. }
  48. static int mt7620_wdt_stop(struct udevice *dev)
  49. {
  50. struct mt7620_wdt *priv = dev_get_priv(dev);
  51. mt7620_wdt_ping(priv);
  52. clrbits_32(priv->regs + TIMER_CTL, TIMER_ENABLE);
  53. return 0;
  54. }
  55. static int mt7620_wdt_reset(struct udevice *dev)
  56. {
  57. struct mt7620_wdt *priv = dev_get_priv(dev);
  58. mt7620_wdt_ping(priv);
  59. return 0;
  60. }
  61. static int mt7620_wdt_expire_now(struct udevice *dev, ulong flags)
  62. {
  63. struct mt7620_wdt *priv = dev_get_priv(dev);
  64. mt7620_wdt_start(dev, 1, flags);
  65. /*
  66. * 0 will disable the timer directly, a positive number must be used
  67. * instead. Since the timer is a countdown timer, 1 (tick) is used.
  68. *
  69. * For a timer with input clock = 40MHz, 1 timer tick is short
  70. * enough to trigger a timeout immediately.
  71. *
  72. * Restore prescale to 1, and load timer with 1 to trigger timeout.
  73. */
  74. writel(TIMER_ENABLE | (TIMER_MODE_WDT << TIMER_MODE_SHIFT),
  75. priv->regs + TIMER_CTL);
  76. writel(1, priv->regs + TIMER_LOAD);
  77. return 0;
  78. }
  79. static int mt7620_wdt_probe(struct udevice *dev)
  80. {
  81. struct mt7620_wdt *priv = dev_get_priv(dev);
  82. struct reset_ctl reset_wdt;
  83. int ret;
  84. ret = reset_get_by_index(dev, 0, &reset_wdt);
  85. if (!ret)
  86. reset_deassert(&reset_wdt);
  87. priv->regs = dev_remap_addr(dev);
  88. if (!priv->regs)
  89. return -EINVAL;
  90. mt7620_wdt_stop(dev);
  91. return 0;
  92. }
  93. static const struct wdt_ops mt7620_wdt_ops = {
  94. .start = mt7620_wdt_start,
  95. .reset = mt7620_wdt_reset,
  96. .stop = mt7620_wdt_stop,
  97. .expire_now = mt7620_wdt_expire_now,
  98. };
  99. static const struct udevice_id mt7620_wdt_ids[] = {
  100. { .compatible = "mediatek,mt7620-wdt" },
  101. {}
  102. };
  103. U_BOOT_DRIVER(mt7620_wdt) = {
  104. .name = "mt7620_wdt",
  105. .id = UCLASS_WDT,
  106. .of_match = mt7620_wdt_ids,
  107. .probe = mt7620_wdt_probe,
  108. .priv_auto = sizeof(struct mt7620_wdt),
  109. .ops = &mt7620_wdt_ops,
  110. };