booke_wdt.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Watchdog timer for PowerPC Book-E systems
  4. */
  5. #include <div64.h>
  6. #include <dm.h>
  7. #include <wdt.h>
  8. #include <asm/processor.h>
  9. #define WDTP_MASK TCR_WP(0x3f)
  10. /* For the specified period, determine the number of seconds
  11. * corresponding to the reset time. There will be a watchdog
  12. * exception at approximately 3/5 of this time.
  13. *
  14. * The formula to calculate this is given by:
  15. * 2.5 * (2^(63-period+1)) / timebase_freq
  16. *
  17. * In order to simplify things, we assume that period is
  18. * at least 1. This will still result in a very long timeout.
  19. */
  20. static unsigned long long period_to_sec(unsigned int period)
  21. {
  22. unsigned long long tmp = 1ULL << (64 - period);
  23. unsigned long tmp2 = get_tbclk();
  24. /* tmp may be a very large number and we don't want to overflow,
  25. * so divide the timebase freq instead of multiplying tmp
  26. */
  27. tmp2 = tmp2 / 5 * 2;
  28. do_div(tmp, tmp2);
  29. return tmp;
  30. }
  31. /*
  32. * This procedure will find the highest period which will give a timeout
  33. * greater than the one required. e.g. for a bus speed of 66666666 and
  34. * and a parameter of 2 secs, then this procedure will return a value of 38.
  35. */
  36. static unsigned int sec_to_period(unsigned int secs)
  37. {
  38. unsigned int period;
  39. for (period = 63; period > 0; period--) {
  40. if (period_to_sec(period) >= secs)
  41. return period;
  42. }
  43. return 0;
  44. }
  45. static int booke_wdt_reset(struct udevice *dev)
  46. {
  47. mtspr(SPRN_TSR, TSR_ENW | TSR_WIS);
  48. return 0;
  49. }
  50. static int booke_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
  51. {
  52. u32 val;
  53. unsigned int timeout = DIV_ROUND_UP(timeout_ms, 1000);
  54. /* clear status before enabling watchdog */
  55. booke_wdt_reset(dev);
  56. val = mfspr(SPRN_TCR);
  57. val &= ~WDTP_MASK;
  58. val |= (TCR_WIE | TCR_WRC(WRC_CHIP) | TCR_WP(sec_to_period(timeout)));
  59. mtspr(SPRN_TCR, val);
  60. return 0;
  61. }
  62. static int booke_wdt_stop(struct udevice *dev)
  63. {
  64. u32 val;
  65. val = mfspr(SPRN_TCR);
  66. val &= ~(TCR_WIE | WDTP_MASK);
  67. mtspr(SPRN_TCR, val);
  68. /* clear status to make sure nothing is pending */
  69. booke_wdt_reset(dev);
  70. return 0;
  71. }
  72. static const struct wdt_ops booke_wdt_ops = {
  73. .start = booke_wdt_start,
  74. .stop = booke_wdt_stop,
  75. .reset = booke_wdt_reset,
  76. };
  77. static const struct udevice_id booke_wdt_ids[] = {
  78. { .compatible = "fsl,booke-wdt" },
  79. {}
  80. };
  81. U_BOOT_DRIVER(booke_wdt) = {
  82. .name = "booke_wdt",
  83. .id = UCLASS_WDT,
  84. .of_match = booke_wdt_ids,
  85. .ops = &booke_wdt_ops,
  86. };