tegra.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <fdtdec.h>
  8. #include <log.h>
  9. #include <panel.h>
  10. #include <part.h>
  11. #include <pwm.h>
  12. #include <video.h>
  13. #include <asm/cache.h>
  14. #include <asm/global_data.h>
  15. #include <asm/system.h>
  16. #include <asm/gpio.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/funcmux.h>
  20. #include <asm/arch/pinmux.h>
  21. #include <asm/arch/pwm.h>
  22. #include <asm/arch/display.h>
  23. #include <asm/arch-tegra/timer.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. /* Information about the display controller */
  26. struct tegra_lcd_priv {
  27. int width; /* width in pixels */
  28. int height; /* height in pixels */
  29. enum video_log2_bpp log2_bpp; /* colour depth */
  30. struct display_timing timing;
  31. struct udevice *panel;
  32. struct disp_ctlr *disp; /* Display controller to use */
  33. fdt_addr_t frame_buffer; /* Address of frame buffer */
  34. unsigned pixel_clock; /* Pixel clock in Hz */
  35. };
  36. enum {
  37. /* Maximum LCD size we support */
  38. LCD_MAX_WIDTH = 1366,
  39. LCD_MAX_HEIGHT = 768,
  40. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  41. };
  42. static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
  43. {
  44. unsigned h_dda, v_dda;
  45. unsigned long val;
  46. val = readl(&dc->cmd.disp_win_header);
  47. val |= WINDOW_A_SELECT;
  48. writel(val, &dc->cmd.disp_win_header);
  49. writel(win->fmt, &dc->win.color_depth);
  50. clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
  51. BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
  52. val = win->out_x << H_POSITION_SHIFT;
  53. val |= win->out_y << V_POSITION_SHIFT;
  54. writel(val, &dc->win.pos);
  55. val = win->out_w << H_SIZE_SHIFT;
  56. val |= win->out_h << V_SIZE_SHIFT;
  57. writel(val, &dc->win.size);
  58. val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
  59. val |= win->h << V_PRESCALED_SIZE_SHIFT;
  60. writel(val, &dc->win.prescaled_size);
  61. writel(0, &dc->win.h_initial_dda);
  62. writel(0, &dc->win.v_initial_dda);
  63. h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
  64. v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
  65. val = h_dda << H_DDA_INC_SHIFT;
  66. val |= v_dda << V_DDA_INC_SHIFT;
  67. writel(val, &dc->win.dda_increment);
  68. writel(win->stride, &dc->win.line_stride);
  69. writel(0, &dc->win.buf_stride);
  70. val = WIN_ENABLE;
  71. if (win->bpp < 24)
  72. val |= COLOR_EXPAND;
  73. writel(val, &dc->win.win_opt);
  74. writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
  75. writel(win->x, &dc->winbuf.addr_h_offset);
  76. writel(win->y, &dc->winbuf.addr_v_offset);
  77. writel(0xff00, &dc->win.blend_nokey);
  78. writel(0xff00, &dc->win.blend_1win);
  79. val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
  80. val |= GENERAL_UPDATE | WIN_A_UPDATE;
  81. writel(val, &dc->cmd.state_ctrl);
  82. }
  83. static int update_display_mode(struct dc_disp_reg *disp,
  84. struct tegra_lcd_priv *priv)
  85. {
  86. struct display_timing *dt = &priv->timing;
  87. unsigned long val;
  88. unsigned long rate;
  89. unsigned long div;
  90. writel(0x0, &disp->disp_timing_opt);
  91. writel(1 | 1 << 16, &disp->ref_to_sync);
  92. writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
  93. writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
  94. &disp->back_porch);
  95. writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
  96. &disp->front_porch);
  97. writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
  98. val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
  99. val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
  100. writel(val, &disp->data_enable_opt);
  101. val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
  102. val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
  103. val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
  104. writel(val, &disp->disp_interface_ctrl);
  105. /*
  106. * The pixel clock divider is in 7.1 format (where the bottom bit
  107. * represents 0.5). Here we calculate the divider needed to get from
  108. * the display clock (typically 600MHz) to the pixel clock. We round
  109. * up or down as requried.
  110. */
  111. rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
  112. div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
  113. debug("Display clock %lu, divider %lu\n", rate, div);
  114. writel(0x00010001, &disp->shift_clk_opt);
  115. val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
  116. val |= div << SHIFT_CLK_DIVIDER_SHIFT;
  117. writel(val, &disp->disp_clk_ctrl);
  118. return 0;
  119. }
  120. /* Start up the display and turn on power to PWMs */
  121. static void basic_init(struct dc_cmd_reg *cmd)
  122. {
  123. u32 val;
  124. writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
  125. writel(0x0000011a, &cmd->cont_syncpt_vsync);
  126. writel(0x00000000, &cmd->int_type);
  127. writel(0x00000000, &cmd->int_polarity);
  128. writel(0x00000000, &cmd->int_mask);
  129. writel(0x00000000, &cmd->int_enb);
  130. val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
  131. val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
  132. val |= PM1_ENABLE;
  133. writel(val, &cmd->disp_pow_ctrl);
  134. val = readl(&cmd->disp_cmd);
  135. val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
  136. writel(val, &cmd->disp_cmd);
  137. }
  138. static void basic_init_timer(struct dc_disp_reg *disp)
  139. {
  140. writel(0x00000020, &disp->mem_high_pri);
  141. writel(0x00000001, &disp->mem_high_pri_timer);
  142. }
  143. static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
  144. 0x00000000,
  145. 0x00000000,
  146. 0x00000000,
  147. 0x00000000,
  148. };
  149. static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
  150. 0x00000000,
  151. 0x01000000,
  152. 0x00000000,
  153. 0x00000000,
  154. };
  155. static const u32 rgb_data_tab[PIN_REG_COUNT] = {
  156. 0x00000000,
  157. 0x00000000,
  158. 0x00000000,
  159. 0x00000000,
  160. };
  161. static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
  162. 0x00000000,
  163. 0x00000000,
  164. 0x00000000,
  165. 0x00000000,
  166. 0x00210222,
  167. 0x00002200,
  168. 0x00020000,
  169. };
  170. static void rgb_enable(struct dc_com_reg *com)
  171. {
  172. int i;
  173. for (i = 0; i < PIN_REG_COUNT; i++) {
  174. writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
  175. writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
  176. writel(rgb_data_tab[i], &com->pin_output_data[i]);
  177. }
  178. for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
  179. writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
  180. }
  181. static int setup_window(struct disp_ctl_win *win,
  182. struct tegra_lcd_priv *priv)
  183. {
  184. win->x = 0;
  185. win->y = 0;
  186. win->w = priv->width;
  187. win->h = priv->height;
  188. win->out_x = 0;
  189. win->out_y = 0;
  190. win->out_w = priv->width;
  191. win->out_h = priv->height;
  192. win->phys_addr = priv->frame_buffer;
  193. win->stride = priv->width * (1 << priv->log2_bpp) / 8;
  194. debug("%s: depth = %d\n", __func__, priv->log2_bpp);
  195. switch (priv->log2_bpp) {
  196. case VIDEO_BPP32:
  197. win->fmt = COLOR_DEPTH_R8G8B8A8;
  198. win->bpp = 32;
  199. break;
  200. case VIDEO_BPP16:
  201. win->fmt = COLOR_DEPTH_B5G6R5;
  202. win->bpp = 16;
  203. break;
  204. default:
  205. debug("Unsupported LCD bit depth");
  206. return -1;
  207. }
  208. return 0;
  209. }
  210. /**
  211. * Register a new display based on device tree configuration.
  212. *
  213. * The frame buffer can be positioned by U-Boot or overridden by the fdt.
  214. * You should pass in the U-Boot address here, and check the contents of
  215. * struct tegra_lcd_priv to see what was actually chosen.
  216. *
  217. * @param blob Device tree blob
  218. * @param priv Driver's private data
  219. * @param default_lcd_base Default address of LCD frame buffer
  220. * @return 0 if ok, -1 on error (unsupported bits per pixel)
  221. */
  222. static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
  223. void *default_lcd_base)
  224. {
  225. struct disp_ctl_win window;
  226. struct dc_ctlr *dc;
  227. priv->frame_buffer = (u32)default_lcd_base;
  228. dc = (struct dc_ctlr *)priv->disp;
  229. /*
  230. * A header file for clock constants was NAKed upstream.
  231. * TODO: Put this into the FDT and fdt_lcd struct when we have clock
  232. * support there
  233. */
  234. clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
  235. 144 * 1000000);
  236. clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
  237. 600 * 1000000);
  238. basic_init(&dc->cmd);
  239. basic_init_timer(&dc->disp);
  240. rgb_enable(&dc->com);
  241. if (priv->pixel_clock)
  242. update_display_mode(&dc->disp, priv);
  243. if (setup_window(&window, priv))
  244. return -1;
  245. update_window(dc, &window);
  246. return 0;
  247. }
  248. static int tegra_lcd_probe(struct udevice *dev)
  249. {
  250. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  251. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  252. struct tegra_lcd_priv *priv = dev_get_priv(dev);
  253. const void *blob = gd->fdt_blob;
  254. int ret;
  255. /* Initialize the Tegra display controller */
  256. funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
  257. if (tegra_display_probe(blob, priv, (void *)plat->base)) {
  258. printf("%s: Failed to probe display driver\n", __func__);
  259. return -1;
  260. }
  261. pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
  262. pinmux_tristate_disable(PMUX_PINGRP_GPU);
  263. ret = panel_enable_backlight(priv->panel);
  264. if (ret) {
  265. debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
  266. return ret;
  267. }
  268. mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
  269. DCACHE_WRITETHROUGH);
  270. /* Enable flushing after LCD writes if requested */
  271. video_set_flush_dcache(dev, true);
  272. uc_priv->xsize = priv->width;
  273. uc_priv->ysize = priv->height;
  274. uc_priv->bpix = priv->log2_bpp;
  275. debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
  276. plat->size);
  277. return 0;
  278. }
  279. static int tegra_lcd_of_to_plat(struct udevice *dev)
  280. {
  281. struct tegra_lcd_priv *priv = dev_get_priv(dev);
  282. const void *blob = gd->fdt_blob;
  283. struct display_timing *timing;
  284. int node = dev_of_offset(dev);
  285. int panel_node;
  286. int rgb;
  287. int ret;
  288. priv->disp = dev_read_addr_ptr(dev);
  289. if (!priv->disp) {
  290. debug("%s: No display controller address\n", __func__);
  291. return -EINVAL;
  292. }
  293. rgb = fdt_subnode_offset(blob, node, "rgb");
  294. if (rgb < 0) {
  295. debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
  296. __func__, dev->name, rgb);
  297. return -EINVAL;
  298. }
  299. ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
  300. if (ret) {
  301. debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
  302. __func__, dev->name, ret);
  303. return -EINVAL;
  304. }
  305. timing = &priv->timing;
  306. priv->width = timing->hactive.typ;
  307. priv->height = timing->vactive.typ;
  308. priv->pixel_clock = timing->pixelclock.typ;
  309. priv->log2_bpp = VIDEO_BPP16;
  310. /*
  311. * Sadly the panel phandle is in an rgb subnode so we cannot use
  312. * uclass_get_device_by_phandle().
  313. */
  314. panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
  315. if (panel_node < 0) {
  316. debug("%s: Cannot find panel information\n", __func__);
  317. return -EINVAL;
  318. }
  319. ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
  320. &priv->panel);
  321. if (ret) {
  322. debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
  323. dev->name, ret);
  324. return ret;
  325. }
  326. return 0;
  327. }
  328. static int tegra_lcd_bind(struct udevice *dev)
  329. {
  330. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  331. const void *blob = gd->fdt_blob;
  332. int node = dev_of_offset(dev);
  333. int rgb;
  334. rgb = fdt_subnode_offset(blob, node, "rgb");
  335. if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
  336. return -ENODEV;
  337. plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  338. (1 << LCD_MAX_LOG2_BPP) / 8;
  339. return 0;
  340. }
  341. static const struct video_ops tegra_lcd_ops = {
  342. };
  343. static const struct udevice_id tegra_lcd_ids[] = {
  344. { .compatible = "nvidia,tegra20-dc" },
  345. { }
  346. };
  347. U_BOOT_DRIVER(tegra_lcd) = {
  348. .name = "tegra_lcd",
  349. .id = UCLASS_VIDEO,
  350. .of_match = tegra_lcd_ids,
  351. .ops = &tegra_lcd_ops,
  352. .bind = tegra_lcd_bind,
  353. .probe = tegra_lcd_probe,
  354. .of_to_plat = tegra_lcd_of_to_plat,
  355. .priv_auto = sizeof(struct tegra_lcd_priv),
  356. };