tda19988.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 Liviu Dudau <liviu@dudau.co.uk>
  4. *
  5. * Based on the Linux driver, (C) 2012 Texas Instruments
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <display.h>
  10. #include <i2c.h>
  11. #include <linux/bitops.h>
  12. #include <linux/delay.h>
  13. /*
  14. * TDA19988 uses paged registers. We encode the page# in the upper
  15. * bits of the register#. It also means that reads/writes to a register
  16. * have to ensure that the register's page is selected as the current
  17. * page.
  18. */
  19. #define REG(page, addr) (((page) << 8) | (addr))
  20. #define REG2ADDR(reg) ((reg) & 0xff)
  21. #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
  22. /* register for setting current page */
  23. #define REG_CURRENT_PAGE 0xff
  24. /* Page 00h: General Control */
  25. #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
  26. #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
  27. #define MAIN_CNTRL0_SR BIT(0)
  28. #define MAIN_CNTRL0_DECS BIT(1)
  29. #define MAIN_CNTRL0_DEHS BIT(2)
  30. #define MAIN_CNTRL0_CECS BIT(3)
  31. #define MAIN_CNTRL0_CEHS BIT(4)
  32. #define MAIN_CNTRL0_SCALER BIT(7)
  33. #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
  34. #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
  35. #define SOFTRESET_AUDIO BIT(0)
  36. #define SOFTRESET_I2C_MASTER BIT(1)
  37. #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
  38. #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
  39. #define I2C_MASTER_DIS_MM BIT(0)
  40. #define I2C_MASTER_DIS_FILT BIT(1)
  41. #define I2C_MASTER_APP_STRT_LAT BIT(2)
  42. #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
  43. #define FEAT_POWERDOWN_PREFILT BIT(0)
  44. #define FEAT_POWERDOWN_CSC BIT(1)
  45. #define FEAT_POWERDOWN_SPDIF BIT(3)
  46. #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
  47. #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
  48. #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
  49. #define INT_FLAGS_2_EDID_BLK_RD BIT(1)
  50. #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
  51. #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
  52. #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
  53. #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
  54. #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
  55. #define VIP_CNTRL_0_MIRR_A BIT(7)
  56. #define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
  57. #define VIP_CNTRL_0_MIRR_B BIT(3)
  58. #define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
  59. #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
  60. #define VIP_CNTRL_1_MIRR_C BIT(7)
  61. #define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
  62. #define VIP_CNTRL_1_MIRR_D BIT(3)
  63. #define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
  64. #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
  65. #define VIP_CNTRL_2_MIRR_E BIT(7)
  66. #define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
  67. #define VIP_CNTRL_2_MIRR_F BIT(3)
  68. #define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
  69. #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
  70. #define VIP_CNTRL_3_X_TGL BIT(0)
  71. #define VIP_CNTRL_3_H_TGL BIT(1)
  72. #define VIP_CNTRL_3_V_TGL BIT(2)
  73. #define VIP_CNTRL_3_EMB BIT(3)
  74. #define VIP_CNTRL_3_SYNC_DE BIT(4)
  75. #define VIP_CNTRL_3_SYNC_HS BIT(5)
  76. #define VIP_CNTRL_3_DE_INT BIT(6)
  77. #define VIP_CNTRL_3_EDGE BIT(7)
  78. #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
  79. #define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
  80. #define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
  81. #define VIP_CNTRL_4_CCIR656 BIT(4)
  82. #define VIP_CNTRL_4_656_ALT BIT(5)
  83. #define VIP_CNTRL_4_TST_656 BIT(6)
  84. #define VIP_CNTRL_4_TST_PAT BIT(7)
  85. #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
  86. #define VIP_CNTRL_5_CKCASE BIT(0)
  87. #define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
  88. #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
  89. #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
  90. #define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
  91. #define MAT_CONTRL_MAT_BP BIT(2)
  92. #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
  93. #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
  94. #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
  95. #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
  96. #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
  97. #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
  98. #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
  99. #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
  100. #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
  101. #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
  102. #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
  103. #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
  104. #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
  105. #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
  106. #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
  107. #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
  108. #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
  109. #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
  110. #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
  111. #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
  112. #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
  113. #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
  114. #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
  115. #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
  116. #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
  117. #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
  118. #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
  119. #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
  120. #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
  121. #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
  122. #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
  123. #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
  124. #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
  125. #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
  126. #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
  127. #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
  128. #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
  129. #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
  130. #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
  131. #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
  132. #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
  133. #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
  134. #define TBG_CNTRL_0_TOP_TGL BIT(0)
  135. #define TBG_CNTRL_0_TOP_SEL BIT(1)
  136. #define TBG_CNTRL_0_DE_EXT BIT(2)
  137. #define TBG_CNTRL_0_TOP_EXT BIT(3)
  138. #define TBG_CNTRL_0_FRAME_DIS BIT(5)
  139. #define TBG_CNTRL_0_SYNC_MTHD BIT(6)
  140. #define TBG_CNTRL_0_SYNC_ONCE BIT(7)
  141. #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
  142. #define TBG_CNTRL_1_H_TGL BIT(0)
  143. #define TBG_CNTRL_1_V_TGL BIT(1)
  144. #define TBG_CNTRL_1_TGL_EN BIT(2)
  145. #define TBG_CNTRL_1_X_EXT BIT(3)
  146. #define TBG_CNTRL_1_H_EXT BIT(4)
  147. #define TBG_CNTRL_1_V_EXT BIT(5)
  148. #define TBG_CNTRL_1_DWIN_DIS BIT(6)
  149. #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
  150. #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
  151. #define HVF_CNTRL_0_SM BIT(7)
  152. #define HVF_CNTRL_0_RWB BIT(6)
  153. #define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
  154. #define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
  155. #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
  156. #define HVF_CNTRL_1_FOR BIT(0)
  157. #define HVF_CNTRL_1_YUVBLK BIT(1)
  158. #define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
  159. #define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
  160. #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
  161. #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
  162. #define AIP_CLKSEL_AIP_SPDIF (0 << 3)
  163. #define AIP_CLKSEL_AIP_I2S BIT(3)
  164. #define AIP_CLKSEL_FS_ACLK (0 << 0)
  165. #define AIP_CLKSEL_FS_MCLK BIT(0)
  166. /* Page 02h: PLL settings */
  167. #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
  168. #define PLL_SERIAL_1_SRL_FDN BIT(0)
  169. #define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
  170. #define PLL_SERIAL_1_SRL_MAN_IZ BIT(6)
  171. #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
  172. #define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
  173. #define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
  174. #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
  175. #define PLL_SERIAL_3_SRL_CCIR BIT(0)
  176. #define PLL_SERIAL_3_SRL_DE BIT(2)
  177. #define PLL_SERIAL_3_SRL_PXIN_SEL BIT(4)
  178. #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
  179. #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
  180. #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
  181. #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
  182. #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
  183. #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
  184. #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
  185. #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
  186. #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
  187. #define AUDIO_DIV_SERCLK_1 0
  188. #define AUDIO_DIV_SERCLK_2 1
  189. #define AUDIO_DIV_SERCLK_4 2
  190. #define AUDIO_DIV_SERCLK_8 3
  191. #define AUDIO_DIV_SERCLK_16 4
  192. #define AUDIO_DIV_SERCLK_32 5
  193. #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
  194. #define SEL_CLK_SEL_CLK1 BIT(0)
  195. #define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
  196. #define SEL_CLK_ENA_SC_CLK BIT(3)
  197. #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
  198. /* Page 09h: EDID Control */
  199. #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
  200. /* next 127 successive registers are the EDID block */
  201. #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
  202. #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
  203. #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
  204. #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
  205. #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
  206. /* Page 11h: audio settings and content info packets */
  207. #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
  208. #define AIP_CNTRL_0_RST_FIFO BIT(0)
  209. #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
  210. #define ENC_CNTRL_RST_ENC BIT(0)
  211. #define ENC_CNTRL_RST_SEL BIT(1)
  212. #define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
  213. /* Page 12h: HDCP and OTP */
  214. #define REG_TX3 REG(0x12, 0x9a) /* read/write */
  215. #define REG_TX4 REG(0x12, 0x9b) /* read/write */
  216. #define TX4_PD_RAM BIT(1)
  217. #define REG_TX33 REG(0x12, 0xb8) /* read/write */
  218. #define TX33_HDMI BIT(1)
  219. /* CEC registers, not paged */
  220. #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
  221. #define CEC_FRO_IM_CLK_CTRL_GHOST_DIS BIT(7)
  222. #define CEC_FRO_IM_CLK_CTRL_ENA_OTP BIT(6)
  223. #define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL BIT(1)
  224. #define CEC_FRO_IM_CLK_CTRL_FRO_DIV BIT(0)
  225. #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
  226. #define REG_CEC_RXSHPDINT 0xfd /* read */
  227. #define CEC_RXSHPDINT_RXSENS BIT(0)
  228. #define CEC_RXSHPDINT_HPD BIT(1)
  229. #define TDA19988_CEC_ENAMODS 0xff /* read/write */
  230. #define CEC_ENAMODS_EN_RXSENS BIT(2)
  231. #define CEC_ENAMODS_EN_HDMI BIT(1)
  232. #define CEC_ENAMODS_EN_CEC BIT(0)
  233. /* Device versions */
  234. #define TDA9989N2 0x0101
  235. #define TDA19989 0x0201
  236. #define TDA19989N2 0x0202
  237. #define TDA19988 0x0301
  238. struct tda19988_priv {
  239. struct udevice *chip;
  240. struct udevice *cec_chip;
  241. u16 revision;
  242. u8 current_page;
  243. };
  244. static void tda19988_register_set(struct tda19988_priv *priv, u16 reg, u8 val)
  245. {
  246. u8 old_val, page = REG2PAGE(reg);
  247. if (priv->current_page != page) {
  248. dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
  249. priv->current_page = page;
  250. }
  251. old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
  252. old_val |= val;
  253. dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val);
  254. }
  255. static void tda19988_register_clear(struct tda19988_priv *priv, u16 reg, u8 val)
  256. {
  257. u8 old_val, page = REG2PAGE(reg);
  258. if (priv->current_page != page) {
  259. dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
  260. priv->current_page = page;
  261. }
  262. old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
  263. old_val &= ~val;
  264. dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val);
  265. }
  266. static void tda19988_register_write(struct tda19988_priv *priv, u16 reg, u8 val)
  267. {
  268. u8 page = REG2PAGE(reg);
  269. if (priv->current_page != page) {
  270. dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
  271. priv->current_page = page;
  272. }
  273. dm_i2c_reg_write(priv->chip, REG2ADDR(reg), val);
  274. }
  275. static int tda19988_register_read(struct tda19988_priv *priv, u16 reg)
  276. {
  277. u8 page = REG2PAGE(reg);
  278. if (priv->current_page != page) {
  279. dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
  280. priv->current_page = page;
  281. }
  282. return dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
  283. }
  284. static void tda19988_register_write16(struct tda19988_priv *priv,
  285. u16 reg, u16 val)
  286. {
  287. u8 buf[] = { val >> 8, val }, page = REG2PAGE(reg);
  288. if (priv->current_page != page) {
  289. dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
  290. priv->current_page = page;
  291. }
  292. dm_i2c_write(priv->chip, REG2ADDR(reg), buf, 2);
  293. }
  294. static int tda19988_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  295. {
  296. struct tda19988_priv *priv = dev_get_priv(dev);
  297. int i, val = 0, offset = 0;
  298. /*
  299. * The TDA998x has a problem when trying to read the EDID close to a
  300. * HPD assertion: it needs a delay of 100ms to avoid timing out while
  301. * trying to read EDID data.
  302. */
  303. mdelay(120);
  304. if (priv->revision == TDA19988)
  305. tda19988_register_clear(priv, REG_TX4, TX4_PD_RAM);
  306. while (offset < buf_size) {
  307. tda19988_register_write(priv, REG_DDC_ADDR, 0xa0);
  308. tda19988_register_write(priv, REG_DDC_OFFS, offset);
  309. tda19988_register_write(priv, REG_DDC_SEGM_ADDR, 0x60);
  310. tda19988_register_write(priv, REG_DDC_SEGM, 0);
  311. /* enable reading EDID */
  312. tda19988_register_write(priv, REG_EDID_CTRL, 1);
  313. /* flags must be cleared by software */
  314. tda19988_register_write(priv, REG_EDID_CTRL, 0);
  315. /* wait for block read to complete */
  316. for (i = 300; i > 0; i--) {
  317. mdelay(1);
  318. val = tda19988_register_read(priv, REG_INT_FLAGS_2);
  319. if (val < 0)
  320. return val;
  321. if (val & INT_FLAGS_2_EDID_BLK_RD)
  322. break;
  323. }
  324. if (i == 0)
  325. return -ETIMEDOUT;
  326. priv->current_page = REG2PAGE(REG_EDID_DATA_0);
  327. dm_i2c_reg_write(priv->chip,
  328. REG_CURRENT_PAGE, REG2PAGE(REG_EDID_DATA_0));
  329. val = dm_i2c_read(priv->chip,
  330. REG2ADDR(REG_EDID_DATA_0), buf + offset, 128);
  331. offset += 128;
  332. }
  333. if (priv->revision == TDA19988)
  334. tda19988_register_set(priv, REG_TX4, TX4_PD_RAM);
  335. return offset;
  336. }
  337. static int tda19988_enable(struct udevice *dev, int panel_bpp,
  338. const struct display_timing *timing)
  339. {
  340. struct tda19988_priv *priv = dev_get_priv(dev);
  341. u8 div = 148500000 / timing->pixelclock.typ, reg;
  342. u16 line_clocks, lines;
  343. if (dev != 0) {
  344. div--;
  345. if (div > 3)
  346. div = 3;
  347. }
  348. /* first disable the video ports */
  349. tda19988_register_write(priv, REG_ENA_VP_0, 0);
  350. tda19988_register_write(priv, REG_ENA_VP_1, 0);
  351. tda19988_register_write(priv, REG_ENA_VP_2, 0);
  352. /* shutdown audio */
  353. tda19988_register_write(priv, REG_ENA_AP, 0);
  354. line_clocks = timing->hsync_len.typ + timing->hback_porch.typ +
  355. timing->hactive.typ + timing->hfront_porch.typ;
  356. lines = timing->vsync_len.typ + timing->vback_porch.typ +
  357. timing->vactive.typ + timing->vfront_porch.typ;
  358. /* mute the audio FIFO */
  359. tda19988_register_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
  360. /* HDMI HDCP: off */
  361. tda19988_register_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
  362. tda19988_register_clear(priv, REG_TX33, TX33_HDMI);
  363. tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
  364. /* no pre-filter or interpolator */
  365. tda19988_register_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
  366. HVF_CNTRL_0_INTPOL(0));
  367. tda19988_register_set(priv, REG_FEAT_POWERDOWN,
  368. FEAT_POWERDOWN_PREFILT);
  369. tda19988_register_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
  370. tda19988_register_write(priv, REG_VIP_CNTRL_4,
  371. VIP_CNTRL_4_BLANKIT(0) | VIP_CNTRL_4_BLC(0) |
  372. VIP_CNTRL_4_TST_PAT);
  373. tda19988_register_clear(priv, REG_PLL_SERIAL_1,
  374. PLL_SERIAL_1_SRL_MAN_IZ);
  375. tda19988_register_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
  376. PLL_SERIAL_3_SRL_DE);
  377. tda19988_register_write(priv, REG_SERIALIZER, 0);
  378. tda19988_register_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
  379. tda19988_register_write(priv, REG_RPT_CNTRL, 0);
  380. tda19988_register_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
  381. SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
  382. tda19988_register_write(priv, REG_PLL_SERIAL_2,
  383. PLL_SERIAL_2_SRL_NOSC(div) |
  384. PLL_SERIAL_2_SRL_PR(0));
  385. /* set color matrix bypass flag: */
  386. tda19988_register_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
  387. MAT_CONTRL_MAT_SC(1));
  388. tda19988_register_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
  389. /* set BIAS tmds value: */
  390. tda19988_register_write(priv, REG_ANA_GENERAL, 0x09);
  391. /*
  392. * Sync on rising HSYNC/VSYNC
  393. */
  394. reg = VIP_CNTRL_3_SYNC_HS;
  395. /*
  396. * TDA19988 requires high-active sync at input stage,
  397. * so invert low-active sync provided by master encoder here
  398. */
  399. if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
  400. reg |= VIP_CNTRL_3_H_TGL;
  401. if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
  402. reg |= VIP_CNTRL_3_V_TGL;
  403. tda19988_register_write(priv, REG_VIP_CNTRL_3, reg);
  404. tda19988_register_write(priv, REG_VIDFORMAT, 0x00);
  405. tda19988_register_write16(priv, REG_REFPIX_MSB,
  406. timing->hfront_porch.typ + 3);
  407. tda19988_register_write16(priv, REG_REFLINE_MSB,
  408. timing->vfront_porch.typ + 1);
  409. tda19988_register_write16(priv, REG_NPIX_MSB, line_clocks);
  410. tda19988_register_write16(priv, REG_NLINE_MSB, lines);
  411. tda19988_register_write16(priv, REG_VS_LINE_STRT_1_MSB,
  412. timing->vfront_porch.typ);
  413. tda19988_register_write16(priv, REG_VS_PIX_STRT_1_MSB,
  414. timing->hfront_porch.typ);
  415. tda19988_register_write16(priv, REG_VS_LINE_END_1_MSB,
  416. timing->vfront_porch.typ +
  417. timing->vsync_len.typ);
  418. tda19988_register_write16(priv, REG_VS_PIX_END_1_MSB,
  419. timing->hfront_porch.typ);
  420. tda19988_register_write16(priv, REG_VS_LINE_STRT_2_MSB, 0);
  421. tda19988_register_write16(priv, REG_VS_PIX_STRT_2_MSB, 0);
  422. tda19988_register_write16(priv, REG_VS_LINE_END_2_MSB, 0);
  423. tda19988_register_write16(priv, REG_VS_PIX_END_2_MSB, 0);
  424. tda19988_register_write16(priv, REG_HS_PIX_START_MSB,
  425. timing->hfront_porch.typ);
  426. tda19988_register_write16(priv, REG_HS_PIX_STOP_MSB,
  427. timing->hfront_porch.typ +
  428. timing->hsync_len.typ);
  429. tda19988_register_write16(priv, REG_VWIN_START_1_MSB,
  430. lines - timing->vactive.typ - 1);
  431. tda19988_register_write16(priv, REG_VWIN_END_1_MSB, lines - 1);
  432. tda19988_register_write16(priv, REG_VWIN_START_2_MSB, 0);
  433. tda19988_register_write16(priv, REG_VWIN_END_2_MSB, 0);
  434. tda19988_register_write16(priv, REG_DE_START_MSB,
  435. line_clocks - timing->hactive.typ);
  436. tda19988_register_write16(priv, REG_DE_STOP_MSB, line_clocks);
  437. if (priv->revision == TDA19988) {
  438. /* let incoming pixels fill the active space (if any) */
  439. tda19988_register_write(priv, REG_ENABLE_SPACE, 0x00);
  440. }
  441. /*
  442. * Always generate sync polarity relative to input sync and
  443. * revert input stage toggled sync at output stage
  444. */
  445. reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
  446. if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
  447. reg |= TBG_CNTRL_1_H_TGL;
  448. if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
  449. reg |= TBG_CNTRL_1_V_TGL;
  450. tda19988_register_write(priv, REG_TBG_CNTRL_1, reg);
  451. /* must be last register set: */
  452. tda19988_register_write(priv, REG_TBG_CNTRL_0, 0);
  453. /* turn on HDMI HDCP */
  454. reg &= ~TBG_CNTRL_1_DWIN_DIS;
  455. tda19988_register_write(priv, REG_TBG_CNTRL_1, reg);
  456. tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
  457. tda19988_register_set(priv, REG_TX33, TX33_HDMI);
  458. mdelay(400);
  459. /* enable video ports */
  460. tda19988_register_write(priv, REG_ENA_VP_0, 0xff);
  461. tda19988_register_write(priv, REG_ENA_VP_1, 0xff);
  462. tda19988_register_write(priv, REG_ENA_VP_2, 0xff);
  463. /* set muxing after enabling ports: */
  464. tda19988_register_write(priv, REG_VIP_CNTRL_0,
  465. VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3));
  466. tda19988_register_write(priv, REG_VIP_CNTRL_1,
  467. VIP_CNTRL_1_SWAP_C(4) | VIP_CNTRL_1_SWAP_D(5));
  468. tda19988_register_write(priv, REG_VIP_CNTRL_2,
  469. VIP_CNTRL_2_SWAP_E(0) | VIP_CNTRL_2_SWAP_F(1));
  470. return 0;
  471. }
  472. struct dm_display_ops tda19988_ops = {
  473. .read_edid = tda19988_read_edid,
  474. .enable = tda19988_enable,
  475. };
  476. static const struct udevice_id tda19988_ids[] = {
  477. { .compatible = "nxp,tda998x" },
  478. { }
  479. };
  480. static int tda19988_probe(struct udevice *dev)
  481. {
  482. u8 cec_addr, chip_addr, rev_lo, rev_hi;
  483. int err;
  484. struct tda19988_priv *priv = dev_get_priv(dev);
  485. chip_addr = dev_read_addr(dev);
  486. /* CEC I2C address is using TDA19988 I2C address configuration pins */
  487. cec_addr = 0x34 + (chip_addr & 0x03);
  488. err = i2c_get_chip_for_busnum(0, cec_addr, 1, &priv->cec_chip);
  489. if (err) {
  490. printf("cec i2c_get_chip_for_busnum returned %d\n", err);
  491. return err;
  492. }
  493. err = i2c_get_chip_for_busnum(0, chip_addr, 1, &priv->chip);
  494. if (err) {
  495. printf("i2c_get_chip_for_busnum returned %d\n", err);
  496. return err;
  497. }
  498. priv->current_page = 0xff;
  499. /* wake up device */
  500. dm_i2c_reg_write(priv->cec_chip, TDA19988_CEC_ENAMODS,
  501. CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
  502. /* reset audio and I2C master */
  503. tda19988_register_write(priv, REG_SOFTRESET,
  504. SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
  505. mdelay(50);
  506. tda19988_register_write(priv, REG_SOFTRESET, 0);
  507. mdelay(50);
  508. /* reset transmitter */
  509. tda19988_register_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
  510. tda19988_register_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
  511. /* PLL registers common configuration */
  512. tda19988_register_write(priv, REG_PLL_SERIAL_1, 0x00);
  513. tda19988_register_write(priv, REG_PLL_SERIAL_2,
  514. PLL_SERIAL_2_SRL_NOSC(1));
  515. tda19988_register_write(priv, REG_PLL_SERIAL_3, 0x00);
  516. tda19988_register_write(priv, REG_SERIALIZER, 0x00);
  517. tda19988_register_write(priv, REG_BUFFER_OUT, 0x00);
  518. tda19988_register_write(priv, REG_PLL_SCG1, 0x00);
  519. tda19988_register_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
  520. tda19988_register_write(priv, REG_SEL_CLK,
  521. SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
  522. tda19988_register_write(priv, REG_PLL_SCGN1, 0xfa);
  523. tda19988_register_write(priv, REG_PLL_SCGN2, 0x00);
  524. tda19988_register_write(priv, REG_PLL_SCGR1, 0x5b);
  525. tda19988_register_write(priv, REG_PLL_SCGR2, 0x00);
  526. tda19988_register_write(priv, REG_PLL_SCG2, 0x10);
  527. /* Write the default value MUX register */
  528. tda19988_register_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
  529. /* read version */
  530. rev_lo = dm_i2c_reg_read(priv->chip, REG_VERSION_LSB);
  531. rev_hi = dm_i2c_reg_read(priv->chip, REG_VERSION_MSB);
  532. /* mask off feature bits */
  533. priv->revision = ((rev_hi << 8) | rev_lo) & ~0x30;
  534. printf("HDMI: ");
  535. switch (priv->revision) {
  536. case TDA9989N2:
  537. printf("TDA9989 n2\n");
  538. break;
  539. case TDA19989:
  540. printf("TDA19989\n");
  541. break;
  542. case TDA19989N2:
  543. printf("TDA19989 n2\n");
  544. break;
  545. case TDA19988:
  546. printf("TDA19988\n");
  547. break;
  548. default:
  549. printf("unknown TDA device: 0x%04x\n", priv->revision);
  550. return -ENXIO;
  551. }
  552. /* after reset, enable DDC */
  553. tda19988_register_write(priv, REG_DDC_DISABLE, 0x00);
  554. /* set clock on DDC channel */
  555. tda19988_register_write(priv, REG_TX3, 39);
  556. /* if necessary, disable multi-master */
  557. if (priv->revision == TDA19989)
  558. tda19988_register_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
  559. dm_i2c_reg_write(priv->cec_chip, REG_CEC_FRO_IM_CLK_CTRL,
  560. CEC_FRO_IM_CLK_CTRL_GHOST_DIS |
  561. CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
  562. /* ensure interrupts are disabled */
  563. dm_i2c_reg_write(priv->cec_chip, REG_CEC_RXSHPDINTENA, 0);
  564. /* clear pending interrupts */
  565. dm_i2c_reg_read(priv->cec_chip, REG_CEC_RXSHPDINT);
  566. tda19988_register_read(priv, REG_INT_FLAGS_0);
  567. tda19988_register_read(priv, REG_INT_FLAGS_1);
  568. tda19988_register_read(priv, REG_INT_FLAGS_2);
  569. /* enable EDID read irq */
  570. tda19988_register_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
  571. return 0;
  572. }
  573. U_BOOT_DRIVER(tda19988) = {
  574. .name = "tda19988",
  575. .id = UCLASS_DISPLAY,
  576. .of_match = tda19988_ids,
  577. .ops = &tda19988_ops,
  578. .probe = tda19988_probe,
  579. .priv_auto = sizeof(struct tda19988_priv),
  580. };