scf0403_lcd.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * scf0403.c -- support for DataImage SCF0403 LCD
  4. *
  5. * Copyright (c) 2013 Adapted from Linux driver:
  6. * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved.
  7. * Copyright (c) 2012 CompuLab, Ltd
  8. * Dmitry Lifshitz <lifshitz@compulab.co.il>
  9. * Ilya Ledvich <ilya@compulab.co.il>
  10. * Inspired by Alberto Panizzo <maramaopercheseimorto@gmail.com> &
  11. * Marek Vasut work in l4f00242t03.c
  12. *
  13. * U-Boot port: Nikita Kiryanov <nikita@compulab.co.il>
  14. */
  15. #include <common.h>
  16. #include <malloc.h>
  17. #include <asm/gpio.h>
  18. #include <spi.h>
  19. #include <linux/delay.h>
  20. struct scf0403_cmd {
  21. u16 cmd;
  22. u16 *params;
  23. int count;
  24. };
  25. struct scf0403_initseq_entry {
  26. struct scf0403_cmd cmd;
  27. int delay_ms;
  28. };
  29. struct scf0403_priv {
  30. struct spi_slave *spi;
  31. unsigned int reset_gpio;
  32. u32 rddid;
  33. struct scf0403_initseq_entry *init_seq;
  34. int seq_size;
  35. };
  36. struct scf0403_priv priv;
  37. #define SCF0403852GGU04_ID 0x000080
  38. /* SCF0403526GGU20 model commands parameters */
  39. static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06};
  40. static u16 spiinttype_params_sn20[] = {0x60};
  41. static u16 bc_params_sn20[] = {
  42. 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B,
  43. 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01,
  44. 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40,
  45. };
  46. static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67};
  47. static u16 be_params_sn20[] = {
  48. 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22,
  49. };
  50. static u16 vcom_params_sn20[] = {0x74};
  51. static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00};
  52. static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00};
  53. static u16 lvglvolt_params_sn20[] = {0x08};
  54. static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20};
  55. static u16 dispfunc_params_sn20[] = {0xa0};
  56. static u16 dvddvolt_params_sn20[] = {0x74};
  57. static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00};
  58. static u16 panelres_params_sn20[] = {0x82};
  59. static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13};
  60. static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28};
  61. static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20};
  62. static u16 memaccess_params_sn20[] = {0x00};
  63. static u16 pixfmt_params_sn20[] = {0x66};
  64. static u16 pgamma_params_sn20[] = {
  65. 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04,
  66. 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10,
  67. };
  68. static u16 ngamma_params_sn20[] = {
  69. 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03,
  70. 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00,
  71. };
  72. static u16 tearing_params_sn20[] = {0x00};
  73. /* SCF0403852GGU04 model commands parameters */
  74. static u16 memaccess_params_sn04[] = {0x08};
  75. static u16 pixfmt_params_sn04[] = {0x66};
  76. static u16 modectl_params_sn04[] = {0x01};
  77. static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04};
  78. static u16 vcom_params_sn04[] = {0x00, 0x6A};
  79. static u16 pgamma_params_sn04[] = {
  80. 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c,
  81. 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f,
  82. };
  83. static u16 ngamma_params_sn04[] = {
  84. 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05,
  85. 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00,
  86. };
  87. static u16 dispinv_params_sn04[] = {0x02};
  88. /* Common commands */
  89. static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0};
  90. static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0};
  91. /* SCF0403852GGU04 init sequence */
  92. static struct scf0403_initseq_entry scf0403_initseq_sn04[] = {
  93. {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0},
  94. {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0},
  95. {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0},
  96. {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0},
  97. {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0},
  98. {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20},
  99. {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0},
  100. {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100},
  101. };
  102. /* SCF0403526GGU20 init sequence */
  103. static struct scf0403_initseq_entry scf0403_initseq_sn20[] = {
  104. {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0},
  105. {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0},
  106. {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0},
  107. {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0},
  108. {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0},
  109. {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0},
  110. {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0},
  111. {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0},
  112. {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0},
  113. {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0},
  114. {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0},
  115. {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0},
  116. {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0},
  117. {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0},
  118. {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0},
  119. {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0},
  120. {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0},
  121. {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0},
  122. {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0},
  123. {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0},
  124. {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0},
  125. {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0},
  126. };
  127. static void scf0403_gpio_reset(unsigned int gpio)
  128. {
  129. if (!gpio_is_valid(gpio))
  130. return;
  131. gpio_set_value(gpio, 1);
  132. mdelay(100);
  133. gpio_set_value(gpio, 0);
  134. mdelay(40);
  135. gpio_set_value(gpio, 1);
  136. mdelay(100);
  137. }
  138. static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid)
  139. {
  140. int error = 0;
  141. u8 ids_buf = 0x00;
  142. u16 dummy_buf = 0x00;
  143. u16 cmd = 0x04;
  144. error = spi_set_wordlen(spi, 9);
  145. if (error)
  146. return error;
  147. /* Here 9 bits required to transmit a command */
  148. error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE);
  149. if (error)
  150. return error;
  151. /*
  152. * Here 8 + 1 bits required to arrange extra clock cycle
  153. * before the first data bit.
  154. * According to the datasheet - first parameter is the dummy data.
  155. */
  156. error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE);
  157. if (error)
  158. return error;
  159. error = spi_set_wordlen(spi, 8);
  160. if (error)
  161. return error;
  162. /* Read rest of the data */
  163. error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE);
  164. if (error)
  165. return error;
  166. *rddid = ids_buf;
  167. return 0;
  168. }
  169. static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd)
  170. {
  171. int i, error;
  172. u32 command = cmd->cmd;
  173. u32 msg;
  174. error = spi_set_wordlen(spi, 9);
  175. if (error)
  176. return error;
  177. error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE);
  178. if (error)
  179. return error;
  180. for (i = 0; i < cmd->count; i++) {
  181. msg = (cmd->params[i] | 0x100);
  182. error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE);
  183. if (error)
  184. return error;
  185. }
  186. return 0;
  187. }
  188. static void scf0403_lcd_init(struct scf0403_priv *priv)
  189. {
  190. int i;
  191. /* reset LCD */
  192. scf0403_gpio_reset(priv->reset_gpio);
  193. for (i = 0; i < priv->seq_size; i++) {
  194. if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0)
  195. puts("SPI transfer failed\n");
  196. mdelay(priv->init_seq[i].delay_ms);
  197. }
  198. }
  199. static int scf0403_request_reset_gpio(unsigned gpio)
  200. {
  201. int err = gpio_request(gpio, "lcd reset");
  202. if (err)
  203. return err;
  204. err = gpio_direction_output(gpio, 0);
  205. if (err)
  206. gpio_free(gpio);
  207. return err;
  208. }
  209. int scf0403_init(int reset_gpio)
  210. {
  211. int error;
  212. if (gpio_is_valid(reset_gpio)) {
  213. error = scf0403_request_reset_gpio(reset_gpio);
  214. if (error) {
  215. printf("Failed requesting reset GPIO%d: %d\n",
  216. reset_gpio, error);
  217. return error;
  218. }
  219. }
  220. priv.reset_gpio = reset_gpio;
  221. priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0);
  222. error = spi_claim_bus(priv.spi);
  223. if (error)
  224. goto bus_claim_fail;
  225. /* reset LCD */
  226. scf0403_gpio_reset(reset_gpio);
  227. error = scf0403_spi_read_rddid(priv.spi, &priv.rddid);
  228. if (error) {
  229. puts("IDs read failed\n");
  230. goto readid_fail;
  231. }
  232. if (priv.rddid == SCF0403852GGU04_ID) {
  233. priv.init_seq = scf0403_initseq_sn04;
  234. priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04);
  235. } else {
  236. priv.init_seq = scf0403_initseq_sn20;
  237. priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20);
  238. }
  239. scf0403_lcd_init(&priv);
  240. /* Start operation */
  241. scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison);
  242. mdelay(100);
  243. scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout);
  244. spi_release_bus(priv.spi);
  245. return 0;
  246. readid_fail:
  247. spi_release_bus(priv.spi);
  248. bus_claim_fail:
  249. if (gpio_is_valid(priv.reset_gpio))
  250. gpio_free(priv.reset_gpio);
  251. return error;
  252. }