raydium-rm68200.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
  4. * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  5. * Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
  6. *
  7. * This rm68200 panel driver is inspired from the Linux Kernel driver
  8. * drivers/gpu/drm/panel/panel-raydium-rm68200.c.
  9. */
  10. #include <common.h>
  11. #include <backlight.h>
  12. #include <dm.h>
  13. #include <mipi_dsi.h>
  14. #include <panel.h>
  15. #include <asm/gpio.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/delay.h>
  18. #include <power/regulator.h>
  19. /*** Manufacturer Command Set ***/
  20. #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
  21. #define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */
  22. #define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
  23. #define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
  24. #define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
  25. #define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
  26. /* CMD2 P0 commands (Display Options and Power) */
  27. #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
  28. #define MCS_SGOPCTR 0x16 /* Source Bias Current */
  29. #define MCS_SDCTR 0x1A /* Source Output Delay Time */
  30. #define MCS_INVCTR 0x1B /* Inversion Type */
  31. #define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
  32. #define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */
  33. #define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */
  34. #define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
  35. #define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
  36. #define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
  37. #define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
  38. #define MCS_SETVGN 0x52 /* VG M/S N Control */
  39. #define MCS_SETVGP 0x54 /* VG M/S P Control */
  40. #define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */
  41. /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
  42. #define GOA_VSTV1 0x00
  43. #define GOA_VSTV2 0x07
  44. #define GOA_VCLK1 0x0E
  45. #define GOA_VCLK2 0x17
  46. #define GOA_VCLK_OPT1 0x20
  47. #define GOA_BICLK1 0x2A
  48. #define GOA_BICLK2 0x37
  49. #define GOA_BICLK3 0x44
  50. #define GOA_BICLK4 0x4F
  51. #define GOA_BICLK_OPT1 0x5B
  52. #define GOA_BICLK_OPT2 0x60
  53. #define MCS_GOA_GPO1 0x6D
  54. #define MCS_GOA_GPO2 0x71
  55. #define MCS_GOA_EQ 0x74
  56. #define MCS_GOA_CLK_GALLON 0x7C
  57. #define MCS_GOA_FS_SEL0 0x7E
  58. #define MCS_GOA_FS_SEL1 0x87
  59. #define MCS_GOA_FS_SEL2 0x91
  60. #define MCS_GOA_FS_SEL3 0x9B
  61. #define MCS_GOA_BS_SEL0 0xAC
  62. #define MCS_GOA_BS_SEL1 0xB5
  63. #define MCS_GOA_BS_SEL2 0xBF
  64. #define MCS_GOA_BS_SEL3 0xC9
  65. #define MCS_GOA_BS_SEL4 0xD3
  66. /* CMD2 P3 commands (Gamma) */
  67. #define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */
  68. #define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */
  69. struct rm68200_panel_priv {
  70. struct udevice *reg;
  71. struct udevice *backlight;
  72. struct gpio_desc reset;
  73. };
  74. static const struct display_timing default_timing = {
  75. .pixelclock.typ = 54000000,
  76. .hactive.typ = 720,
  77. .hfront_porch.typ = 48,
  78. .hback_porch.typ = 48,
  79. .hsync_len.typ = 9,
  80. .vactive.typ = 1280,
  81. .vfront_porch.typ = 12,
  82. .vback_porch.typ = 12,
  83. .vsync_len.typ = 5,
  84. };
  85. static void rm68200_dcs_write_buf(struct udevice *dev, const void *data,
  86. size_t len)
  87. {
  88. struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
  89. struct mipi_dsi_device *device = plat->device;
  90. int err;
  91. err = mipi_dsi_dcs_write_buffer(device, data, len);
  92. if (err < 0)
  93. dev_err(dev, "MIPI DSI DCS write buffer failed: %d\n", err);
  94. }
  95. static void rm68200_dcs_write_cmd(struct udevice *dev, u8 cmd, u8 value)
  96. {
  97. struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
  98. struct mipi_dsi_device *device = plat->device;
  99. int err;
  100. err = mipi_dsi_dcs_write(device, cmd, &value, 1);
  101. if (err < 0)
  102. dev_err(dev, "MIPI DSI DCS write failed: %d\n", err);
  103. }
  104. #define dcs_write_seq(ctx, seq...) \
  105. ({ \
  106. static const u8 d[] = { seq }; \
  107. \
  108. rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
  109. })
  110. /*
  111. * This panel is not able to auto-increment all cmd addresses so for some of
  112. * them, we need to send them one by one...
  113. */
  114. #define dcs_write_cmd_seq(ctx, cmd, seq...) \
  115. ({ \
  116. static const u8 d[] = { seq }; \
  117. unsigned int i; \
  118. \
  119. for (i = 0; i < ARRAY_SIZE(d) ; i++) \
  120. rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \
  121. })
  122. static void rm68200_init_sequence(struct udevice *dev)
  123. {
  124. /* Enter CMD2 with page 0 */
  125. dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P0);
  126. dcs_write_cmd_seq(dev, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
  127. dcs_write_seq(dev, MCS_BT2CTR, 0xE5);
  128. dcs_write_seq(dev, MCS_SETAVDD, 0x0A);
  129. dcs_write_seq(dev, MCS_SETAVEE, 0x0A);
  130. dcs_write_seq(dev, MCS_SGOPCTR, 0x52);
  131. dcs_write_seq(dev, MCS_BT3CTR, 0x53);
  132. dcs_write_seq(dev, MCS_BT4CTR, 0x5A);
  133. dcs_write_seq(dev, MCS_INVCTR, 0x00);
  134. dcs_write_seq(dev, MCS_STBCTR, 0x0A);
  135. dcs_write_seq(dev, MCS_SDCTR, 0x06);
  136. dcs_write_seq(dev, MCS_VCMCTR, 0x56);
  137. dcs_write_seq(dev, MCS_SETVGN, 0xA0, 0x00);
  138. dcs_write_seq(dev, MCS_SETVGP, 0xA0, 0x00);
  139. dcs_write_seq(dev, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
  140. dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P2);
  141. dcs_write_seq(dev, GOA_VSTV1, 0x05);
  142. dcs_write_seq(dev, 0x02, 0x0B);
  143. dcs_write_seq(dev, 0x03, 0x0F);
  144. dcs_write_seq(dev, 0x04, 0x7D, 0x00, 0x50);
  145. dcs_write_cmd_seq(dev, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
  146. 0x50);
  147. dcs_write_cmd_seq(dev, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
  148. 0x00, 0x85, 0x08);
  149. dcs_write_cmd_seq(dev, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
  150. 0x00, 0x85, 0x08);
  151. dcs_write_seq(dev, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  152. 0x00, 0x00, 0x00, 0x00);
  153. dcs_write_cmd_seq(dev, GOA_BICLK1, 0x07, 0x08);
  154. dcs_write_seq(dev, 0x2D, 0x01);
  155. dcs_write_seq(dev, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
  156. 0x00);
  157. dcs_write_cmd_seq(dev, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
  158. dcs_write_seq(dev, 0x3D, 0x40);
  159. dcs_write_seq(dev, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
  160. dcs_write_seq(dev, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  161. 0x00, 0x00, 0x00, 0x00, 0x00);
  162. dcs_write_seq(dev, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  163. 0x00, 0x00);
  164. dcs_write_seq(dev, 0x58, 0x00, 0x00, 0x00);
  165. dcs_write_seq(dev, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
  166. dcs_write_seq(dev, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  167. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
  168. dcs_write_seq(dev, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
  169. dcs_write_seq(dev, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
  170. dcs_write_seq(dev, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
  171. 0x00, 0x00);
  172. dcs_write_seq(dev, MCS_GOA_CLK_GALLON, 0x00, 0x00);
  173. dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
  174. 0x16, 0x12, 0x08, 0x3F);
  175. dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
  176. 0x0A, 0x0E, 0x3F, 0x3F, 0x00);
  177. dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
  178. 0x05, 0x01, 0x3F, 0x3F, 0x0F);
  179. dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
  180. 0x3F);
  181. dcs_write_cmd_seq(dev, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
  182. dcs_write_cmd_seq(dev, 0xA9, 0x07, 0x03, 0x3F);
  183. dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
  184. 0x15, 0x11, 0x0F, 0x3F);
  185. dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
  186. 0x0D, 0x09, 0x3F, 0x3F, 0x07);
  187. dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
  188. 0x02, 0x06, 0x3F, 0x3F, 0x08);
  189. dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
  190. 0x3F, 0x3F, 0x0E, 0x10, 0x14);
  191. dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
  192. dcs_write_seq(dev, 0xDC, 0x02);
  193. dcs_write_seq(dev, 0xDE, 0x12);
  194. dcs_write_seq(dev, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
  195. dcs_write_seq(dev, 0x01, 0x75);
  196. dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P3);
  197. dcs_write_cmd_seq(dev, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
  198. 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
  199. 0x12, 0x0C, 0x00);
  200. dcs_write_cmd_seq(dev, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
  201. 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
  202. 0x12, 0x0C, 0x00);
  203. /* Exit CMD2 */
  204. dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
  205. }
  206. static int rm68200_panel_enable_backlight(struct udevice *dev)
  207. {
  208. struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
  209. struct mipi_dsi_device *device = plat->device;
  210. struct rm68200_panel_priv *priv = dev_get_priv(dev);
  211. int ret;
  212. ret = mipi_dsi_attach(device);
  213. if (ret < 0)
  214. return ret;
  215. rm68200_init_sequence(dev);
  216. ret = mipi_dsi_dcs_exit_sleep_mode(device);
  217. if (ret)
  218. return ret;
  219. mdelay(125);
  220. ret = mipi_dsi_dcs_set_display_on(device);
  221. if (ret)
  222. return ret;
  223. mdelay(20);
  224. ret = backlight_enable(priv->backlight);
  225. if (ret)
  226. return ret;
  227. return 0;
  228. }
  229. static int rm68200_panel_get_display_timing(struct udevice *dev,
  230. struct display_timing *timings)
  231. {
  232. memcpy(timings, &default_timing, sizeof(*timings));
  233. return 0;
  234. }
  235. static int rm68200_panel_of_to_plat(struct udevice *dev)
  236. {
  237. struct rm68200_panel_priv *priv = dev_get_priv(dev);
  238. int ret;
  239. if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
  240. ret = device_get_supply_regulator(dev, "power-supply",
  241. &priv->reg);
  242. if (ret && ret != -ENOENT) {
  243. dev_err(dev, "Warning: cannot get power supply\n");
  244. return ret;
  245. }
  246. }
  247. ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
  248. GPIOD_IS_OUT);
  249. if (ret) {
  250. dev_err(dev, "Warning: cannot get reset GPIO\n");
  251. if (ret != -ENOENT)
  252. return ret;
  253. }
  254. ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
  255. "backlight", &priv->backlight);
  256. if (ret) {
  257. dev_err(dev, "Cannot get backlight: ret=%d\n", ret);
  258. return ret;
  259. }
  260. return 0;
  261. }
  262. static int rm68200_panel_probe(struct udevice *dev)
  263. {
  264. struct rm68200_panel_priv *priv = dev_get_priv(dev);
  265. struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
  266. int ret;
  267. if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
  268. ret = regulator_set_enable(priv->reg, true);
  269. if (ret)
  270. return ret;
  271. }
  272. /* reset panel */
  273. dm_gpio_set_value(&priv->reset, true);
  274. mdelay(1);
  275. dm_gpio_set_value(&priv->reset, false);
  276. mdelay(10);
  277. /* fill characteristics of DSI data link */
  278. plat->lanes = 2;
  279. plat->format = MIPI_DSI_FMT_RGB888;
  280. plat->mode_flags = MIPI_DSI_MODE_VIDEO |
  281. MIPI_DSI_MODE_VIDEO_BURST |
  282. MIPI_DSI_MODE_LPM;
  283. return 0;
  284. }
  285. static const struct panel_ops rm68200_panel_ops = {
  286. .enable_backlight = rm68200_panel_enable_backlight,
  287. .get_display_timing = rm68200_panel_get_display_timing,
  288. };
  289. static const struct udevice_id rm68200_panel_ids[] = {
  290. { .compatible = "raydium,rm68200" },
  291. { }
  292. };
  293. U_BOOT_DRIVER(rm68200_panel) = {
  294. .name = "rm68200_panel",
  295. .id = UCLASS_PANEL,
  296. .of_match = rm68200_panel_ids,
  297. .ops = &rm68200_panel_ops,
  298. .of_to_plat = rm68200_panel_of_to_plat,
  299. .probe = rm68200_panel_probe,
  300. .plat_auto = sizeof(struct mipi_dsi_panel_plat),
  301. .priv_auto = sizeof(struct rm68200_panel_priv),
  302. };