pxa_lcd.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PXA LCD Controller
  4. *
  5. * (C) Copyright 2001-2002
  6. * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
  7. */
  8. /************************************************************************/
  9. /* ** HEADER FILES */
  10. /************************************************************************/
  11. #include <common.h>
  12. #include <log.h>
  13. #include <asm/arch/pxa-regs.h>
  14. #include <asm/io.h>
  15. #include <lcd.h>
  16. #include <linux/types.h>
  17. #include <stdarg.h>
  18. #include <stdio_dev.h>
  19. /* #define DEBUG */
  20. #ifdef CONFIG_LCD
  21. /*----------------------------------------------------------------------*/
  22. /*
  23. * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
  24. * your display.
  25. */
  26. #ifdef CONFIG_PXA_VGA
  27. /* LCD outputs connected to a video DAC */
  28. # define LCD_BPP LCD_COLOR8
  29. /* you have to set lccr0 and lccr3 (including pcd) */
  30. # define REG_LCCR0 0x003008f8
  31. # define REG_LCCR3 0x0300FF01
  32. /* 640x480x16 @ 61 Hz */
  33. vidinfo_t panel_info = {
  34. .vl_col = 640,
  35. .vl_row = 480,
  36. .vl_width = 640,
  37. .vl_height = 480,
  38. .vl_clkp = CONFIG_SYS_HIGH,
  39. .vl_oep = CONFIG_SYS_HIGH,
  40. .vl_hsp = CONFIG_SYS_HIGH,
  41. .vl_vsp = CONFIG_SYS_HIGH,
  42. .vl_dp = CONFIG_SYS_HIGH,
  43. .vl_bpix = LCD_BPP,
  44. .vl_lbw = 0,
  45. .vl_splt = 0,
  46. .vl_clor = 0,
  47. .vl_tft = 1,
  48. .vl_hpw = 40,
  49. .vl_blw = 56,
  50. .vl_elw = 56,
  51. .vl_vpw = 20,
  52. .vl_bfw = 8,
  53. .vl_efw = 8,
  54. };
  55. #endif /* CONFIG_PXA_VIDEO */
  56. /*----------------------------------------------------------------------*/
  57. #ifdef CONFIG_SHARP_LM8V31
  58. # define LCD_BPP LCD_COLOR8
  59. # define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
  60. /* you have to set lccr0 and lccr3 (including pcd) */
  61. # define REG_LCCR0 0x0030087C
  62. # define REG_LCCR3 0x0340FF08
  63. vidinfo_t panel_info = {
  64. .vl_col = 640,
  65. .vl_row = 480,
  66. .vl_width = 157,
  67. .vl_height = 118,
  68. .vl_clkp = CONFIG_SYS_HIGH,
  69. .vl_oep = CONFIG_SYS_HIGH,
  70. .vl_hsp = CONFIG_SYS_HIGH,
  71. .vl_vsp = CONFIG_SYS_HIGH,
  72. .vl_dp = CONFIG_SYS_HIGH,
  73. .vl_bpix = LCD_BPP,
  74. .vl_lbw = 0,
  75. .vl_splt = 1,
  76. .vl_clor = 1,
  77. .vl_tft = 0,
  78. .vl_hpw = 1,
  79. .vl_blw = 3,
  80. .vl_elw = 3,
  81. .vl_vpw = 1,
  82. .vl_bfw = 0,
  83. .vl_efw = 0,
  84. };
  85. #endif /* CONFIG_SHARP_LM8V31 */
  86. /*----------------------------------------------------------------------*/
  87. #ifdef CONFIG_VOIPAC_LCD
  88. # define LCD_BPP LCD_COLOR8
  89. # define LCD_INVERT_COLORS
  90. /* you have to set lccr0 and lccr3 (including pcd) */
  91. # define REG_LCCR0 0x043008f8
  92. # define REG_LCCR3 0x0340FF08
  93. vidinfo_t panel_info = {
  94. .vl_col = 640,
  95. .vl_row = 480,
  96. .vl_width = 157,
  97. .vl_height = 118,
  98. .vl_clkp = CONFIG_SYS_HIGH,
  99. .vl_oep = CONFIG_SYS_HIGH,
  100. .vl_hsp = CONFIG_SYS_HIGH,
  101. .vl_vsp = CONFIG_SYS_HIGH,
  102. .vl_dp = CONFIG_SYS_HIGH,
  103. .vl_bpix = LCD_BPP,
  104. .vl_lbw = 0,
  105. .vl_splt = 1,
  106. .vl_clor = 1,
  107. .vl_tft = 1,
  108. .vl_hpw = 32,
  109. .vl_blw = 144,
  110. .vl_elw = 32,
  111. .vl_vpw = 2,
  112. .vl_bfw = 13,
  113. .vl_efw = 30,
  114. };
  115. #endif /* CONFIG_VOIPAC_LCD */
  116. /*----------------------------------------------------------------------*/
  117. #ifdef CONFIG_HITACHI_SX14
  118. /* Hitachi SX14Q004-ZZA color STN LCD */
  119. #define LCD_BPP LCD_COLOR8
  120. /* you have to set lccr0 and lccr3 (including pcd) */
  121. #define REG_LCCR0 0x00301079
  122. #define REG_LCCR3 0x0340FF20
  123. vidinfo_t panel_info = {
  124. .vl_col = 320,
  125. .vl_row = 240,
  126. .vl_width = 167,
  127. .vl_height = 109,
  128. .vl_clkp = CONFIG_SYS_HIGH,
  129. .vl_oep = CONFIG_SYS_HIGH,
  130. .vl_hsp = CONFIG_SYS_HIGH,
  131. .vl_vsp = CONFIG_SYS_HIGH,
  132. .vl_dp = CONFIG_SYS_HIGH,
  133. .vl_bpix = LCD_BPP,
  134. .vl_lbw = 1,
  135. .vl_splt = 0,
  136. .vl_clor = 1,
  137. .vl_tft = 0,
  138. .vl_hpw = 1,
  139. .vl_blw = 1,
  140. .vl_elw = 1,
  141. .vl_vpw = 7,
  142. .vl_bfw = 0,
  143. .vl_efw = 0,
  144. };
  145. #endif /* CONFIG_HITACHI_SX14 */
  146. /*----------------------------------------------------------------------*/
  147. #ifdef CONFIG_LMS283GF05
  148. # define LCD_BPP LCD_COLOR8
  149. /*# define LCD_INVERT_COLORS*/
  150. /* you have to set lccr0 and lccr3 (including pcd) */
  151. # define REG_LCCR0 0x043008f8
  152. # define REG_LCCR3 0x03b00009
  153. vidinfo_t panel_info = {
  154. .vl_col = 240,
  155. .vl_row = 320,
  156. .vl_rot = 3,
  157. .vl_width = 240,
  158. .vl_height = 320,
  159. .vl_clkp = CONFIG_SYS_HIGH,
  160. .vl_oep = CONFIG_SYS_LOW,
  161. .vl_hsp = CONFIG_SYS_LOW,
  162. .vl_vsp = CONFIG_SYS_LOW,
  163. .vl_dp = CONFIG_SYS_HIGH,
  164. .vl_bpix = LCD_BPP,
  165. .vl_lbw = 0,
  166. .vl_splt = 1,
  167. .vl_clor = 1,
  168. .vl_tft = 1,
  169. .vl_hpw = 4,
  170. .vl_blw = 4,
  171. .vl_elw = 8,
  172. .vl_vpw = 4,
  173. .vl_bfw = 4,
  174. .vl_efw = 8,
  175. };
  176. #endif /* CONFIG_LMS283GF05 */
  177. /*----------------------------------------------------------------------*/
  178. #ifdef CONFIG_ACX517AKN
  179. # define LCD_BPP LCD_COLOR8
  180. /* you have to set lccr0 and lccr3 (including pcd) */
  181. # define REG_LCCR0 0x003008f9
  182. # define REG_LCCR3 0x03700006
  183. vidinfo_t panel_info = {
  184. .vl_col = 320,
  185. .vl_row = 320,
  186. .vl_width = 320,
  187. .vl_height = 320,
  188. .vl_clkp = CONFIG_SYS_HIGH,
  189. .vl_oep = CONFIG_SYS_LOW,
  190. .vl_hsp = CONFIG_SYS_LOW,
  191. .vl_vsp = CONFIG_SYS_LOW,
  192. .vl_dp = CONFIG_SYS_HIGH,
  193. .vl_bpix = LCD_BPP,
  194. .vl_lbw = 0,
  195. .vl_splt = 1,
  196. .vl_clor = 1,
  197. .vl_tft = 1,
  198. .vl_hpw = 0x04,
  199. .vl_blw = 0x1c,
  200. .vl_elw = 0x08,
  201. .vl_vpw = 0x01,
  202. .vl_bfw = 0x07,
  203. .vl_efw = 0x08,
  204. };
  205. #endif /* CONFIG_ACX517AKN */
  206. #ifdef CONFIG_ACX544AKN
  207. # define LCD_BPP LCD_COLOR16
  208. /* you have to set lccr0 and lccr3 (including pcd) */
  209. # define REG_LCCR0 0x003008f9
  210. # define REG_LCCR3 0x04700007 /* 16bpp */
  211. vidinfo_t panel_info = {
  212. .vl_col = 320,
  213. .vl_row = 320,
  214. .vl_width = 320,
  215. .vl_height = 320,
  216. .vl_clkp = CONFIG_SYS_LOW,
  217. .vl_oep = CONFIG_SYS_LOW,
  218. .vl_hsp = CONFIG_SYS_LOW,
  219. .vl_vsp = CONFIG_SYS_LOW,
  220. .vl_dp = CONFIG_SYS_LOW,
  221. .vl_bpix = LCD_BPP,
  222. .vl_lbw = 0,
  223. .vl_splt = 0,
  224. .vl_clor = 1,
  225. .vl_tft = 1,
  226. .vl_hpw = 0x05,
  227. .vl_blw = 0x13,
  228. .vl_elw = 0x08,
  229. .vl_vpw = 0x02,
  230. .vl_bfw = 0x07,
  231. .vl_efw = 0x05,
  232. };
  233. #endif /* CONFIG_ACX544AKN */
  234. /*----------------------------------------------------------------------*/
  235. #ifdef CONFIG_LQ038J7DH53
  236. # define LCD_BPP LCD_COLOR8
  237. /* you have to set lccr0 and lccr3 (including pcd) */
  238. # define REG_LCCR0 0x003008f9
  239. # define REG_LCCR3 0x03700004
  240. vidinfo_t panel_info = {
  241. .vl_col = 320,
  242. .vl_row = 480,
  243. .vl_width = 320,
  244. .vl_height = 480,
  245. .vl_clkp = CONFIG_SYS_HIGH,
  246. .vl_oep = CONFIG_SYS_LOW,
  247. .vl_hsp = CONFIG_SYS_LOW,
  248. .vl_vsp = CONFIG_SYS_LOW,
  249. .vl_dp = CONFIG_SYS_HIGH,
  250. .vl_bpix = LCD_BPP,
  251. .vl_lbw = 0,
  252. .vl_splt = 1,
  253. .vl_clor = 1,
  254. .vl_tft = 1,
  255. .vl_hpw = 0x04,
  256. .vl_blw = 0x20,
  257. .vl_elw = 0x01,
  258. .vl_vpw = 0x01,
  259. .vl_bfw = 0x04,
  260. .vl_efw = 0x01,
  261. };
  262. #endif /* CONFIG_ACX517AKN */
  263. /*----------------------------------------------------------------------*/
  264. #ifdef CONFIG_LITTLETON_LCD
  265. # define LCD_BPP LCD_COLOR8
  266. /* you have to set lccr0 and lccr3 (including pcd) */
  267. # define REG_LCCR0 0x003008f8
  268. # define REG_LCCR3 0x0300FF04
  269. vidinfo_t panel_info = {
  270. .vl_col = 480,
  271. .vl_row = 640,
  272. .vl_width = 480,
  273. .vl_height = 640,
  274. .vl_clkp = CONFIG_SYS_HIGH,
  275. .vl_oep = CONFIG_SYS_HIGH,
  276. .vl_hsp = CONFIG_SYS_HIGH,
  277. .vl_vsp = CONFIG_SYS_HIGH,
  278. .vl_dp = CONFIG_SYS_HIGH,
  279. .vl_bpix = LCD_BPP,
  280. .vl_lbw = 0,
  281. .vl_splt = 0,
  282. .vl_clor = 0,
  283. .vl_tft = 1,
  284. .vl_hpw = 9,
  285. .vl_blw = 8,
  286. .vl_elw = 24,
  287. .vl_vpw = 2,
  288. .vl_bfw = 2,
  289. .vl_efw = 4,
  290. };
  291. #endif /* CONFIG_LITTLETON_LCD */
  292. /*----------------------------------------------------------------------*/
  293. static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
  294. static void pxafb_setup_gpio (vidinfo_t *vid);
  295. static void pxafb_enable_controller (vidinfo_t *vid);
  296. static int pxafb_init (vidinfo_t *vid);
  297. /************************************************************************/
  298. /* --------------- PXA chipset specific functions ------------------- */
  299. /************************************************************************/
  300. ushort *configuration_get_cmap(void)
  301. {
  302. struct pxafb_info *fbi = &panel_info.pxa;
  303. return (ushort *)fbi->palette;
  304. }
  305. void lcd_ctrl_init (void *lcdbase)
  306. {
  307. pxafb_init_mem(lcdbase, &panel_info);
  308. pxafb_init(&panel_info);
  309. pxafb_setup_gpio(&panel_info);
  310. pxafb_enable_controller(&panel_info);
  311. }
  312. /*----------------------------------------------------------------------*/
  313. #if LCD_BPP == LCD_COLOR8
  314. void
  315. lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
  316. {
  317. struct pxafb_info *fbi = &panel_info.pxa;
  318. unsigned short *palette = (unsigned short *)fbi->palette;
  319. u_int val;
  320. if (regno < fbi->palette_size) {
  321. val = ((red << 8) & 0xf800);
  322. val |= ((green << 4) & 0x07e0);
  323. val |= (blue & 0x001f);
  324. #ifdef LCD_INVERT_COLORS
  325. palette[regno] = ~val;
  326. #else
  327. palette[regno] = val;
  328. #endif
  329. }
  330. debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
  331. regno, &palette[regno],
  332. red, green, blue,
  333. palette[regno]);
  334. }
  335. #endif /* LCD_COLOR8 */
  336. /*----------------------------------------------------------------------*/
  337. __weak void lcd_enable(void)
  338. {
  339. }
  340. /************************************************************************/
  341. /* ** PXA255 specific routines */
  342. /************************************************************************/
  343. /*
  344. * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
  345. * descriptors and palette areas.
  346. */
  347. ulong calc_fbsize (void)
  348. {
  349. ulong size;
  350. int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
  351. size = line_length * panel_info.vl_row;
  352. size += PAGE_SIZE;
  353. return size;
  354. }
  355. static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
  356. {
  357. u_long palette_mem_size;
  358. struct pxafb_info *fbi = &vid->pxa;
  359. int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
  360. fbi->screen = (u_long)lcdbase;
  361. fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
  362. palette_mem_size = fbi->palette_size * sizeof(u16);
  363. debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
  364. /* locate palette and descs at end of page following fb */
  365. fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
  366. return 0;
  367. }
  368. #ifdef CONFIG_CPU_MONAHANS
  369. static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
  370. #else
  371. static void pxafb_setup_gpio (vidinfo_t *vid)
  372. {
  373. u_long lccr0;
  374. /*
  375. * setup is based on type of panel supported
  376. */
  377. lccr0 = vid->pxa.reg_lccr0;
  378. /* 4 bit interface */
  379. if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
  380. {
  381. debug("Setting GPIO for 4 bit data\n");
  382. /* bits 58-61 */
  383. writel(readl(GPDR1) | (0xf << 26), GPDR1);
  384. writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
  385. GAFR1_U);
  386. /* bits 74-77 */
  387. writel(readl(GPDR2) | (0xf << 10), GPDR2);
  388. writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
  389. GAFR2_L);
  390. }
  391. /* 8 bit interface */
  392. else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
  393. (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
  394. {
  395. debug("Setting GPIO for 8 bit data\n");
  396. /* bits 58-65 */
  397. writel(readl(GPDR1) | (0x3f << 26), GPDR1);
  398. writel(readl(GPDR2) | (0x3), GPDR2);
  399. writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
  400. GAFR1_U);
  401. writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
  402. /* bits 74-77 */
  403. writel(readl(GPDR2) | (0xf << 10), GPDR2);
  404. writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
  405. GAFR2_L);
  406. }
  407. /* 16 bit interface */
  408. else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
  409. {
  410. debug("Setting GPIO for 16 bit data\n");
  411. /* bits 58-77 */
  412. writel(readl(GPDR1) | (0x3f << 26), GPDR1);
  413. writel(readl(GPDR2) | 0x00003fff, GPDR2);
  414. writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
  415. GAFR1_U);
  416. writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
  417. }
  418. else
  419. {
  420. printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
  421. }
  422. }
  423. #endif
  424. static void pxafb_enable_controller (vidinfo_t *vid)
  425. {
  426. debug("Enabling LCD controller\n");
  427. /* Sequence from 11.7.10 */
  428. writel(vid->pxa.reg_lccr3, LCCR3);
  429. writel(vid->pxa.reg_lccr2, LCCR2);
  430. writel(vid->pxa.reg_lccr1, LCCR1);
  431. writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
  432. writel(vid->pxa.fdadr0, FDADR0);
  433. writel(vid->pxa.fdadr1, FDADR1);
  434. writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
  435. #ifdef CONFIG_CPU_MONAHANS
  436. writel(readl(CKENA) | CKENA_1_LCD, CKENA);
  437. #else
  438. writel(readl(CKEN) | CKEN16_LCD, CKEN);
  439. #endif
  440. debug("FDADR0 = 0x%08x\n", readl(FDADR0));
  441. debug("FDADR1 = 0x%08x\n", readl(FDADR1));
  442. debug("LCCR0 = 0x%08x\n", readl(LCCR0));
  443. debug("LCCR1 = 0x%08x\n", readl(LCCR1));
  444. debug("LCCR2 = 0x%08x\n", readl(LCCR2));
  445. debug("LCCR3 = 0x%08x\n", readl(LCCR3));
  446. }
  447. static int pxafb_init (vidinfo_t *vid)
  448. {
  449. struct pxafb_info *fbi = &vid->pxa;
  450. debug("Configuring PXA LCD\n");
  451. fbi->reg_lccr0 = REG_LCCR0;
  452. fbi->reg_lccr3 = REG_LCCR3;
  453. debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
  454. vid->vl_col, vid->vl_hpw,
  455. vid->vl_blw, vid->vl_elw);
  456. debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
  457. vid->vl_row, vid->vl_vpw,
  458. vid->vl_bfw, vid->vl_efw);
  459. fbi->reg_lccr1 =
  460. LCCR1_DisWdth(vid->vl_col) +
  461. LCCR1_HorSnchWdth(vid->vl_hpw) +
  462. LCCR1_BegLnDel(vid->vl_blw) +
  463. LCCR1_EndLnDel(vid->vl_elw);
  464. fbi->reg_lccr2 =
  465. LCCR2_DisHght(vid->vl_row) +
  466. LCCR2_VrtSnchWdth(vid->vl_vpw) +
  467. LCCR2_BegFrmDel(vid->vl_bfw) +
  468. LCCR2_EndFrmDel(vid->vl_efw);
  469. fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
  470. fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
  471. | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
  472. /* setup dma descriptors */
  473. fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
  474. fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
  475. fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
  476. #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
  477. (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
  478. (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
  479. /* populate descriptors */
  480. fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
  481. fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
  482. fbi->dmadesc_fblow->fidr = 0;
  483. fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
  484. fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
  485. fbi->dmadesc_fbhigh->fsadr = fbi->screen;
  486. fbi->dmadesc_fbhigh->fidr = 0;
  487. fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
  488. fbi->dmadesc_palette->fsadr = fbi->palette;
  489. fbi->dmadesc_palette->fidr = 0;
  490. fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
  491. if( NBITS(vid->vl_bpix) < 12)
  492. {
  493. /* assume any mode with <12 bpp is palette driven */
  494. fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
  495. fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
  496. /* flips back and forth between pal and fbhigh */
  497. fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
  498. }
  499. else
  500. {
  501. /* palette shouldn't be loaded in true-color mode */
  502. fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
  503. fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
  504. }
  505. debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
  506. debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
  507. debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
  508. debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
  509. debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
  510. debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
  511. debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
  512. debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
  513. debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
  514. debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
  515. debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
  516. debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
  517. return 0;
  518. }
  519. /************************************************************************/
  520. /************************************************************************/
  521. #endif /* CONFIG_LCD */