omap3_dss.c 6.0 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments, <www.ti.com>
  4. * Syed Mohammed Khasim <khasim@ti.com>
  5. *
  6. * Referred to Linux Kernel DSS driver files for OMAP3 by
  7. * Tomi Valkeinen from drivers/video/omap2/dss/
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation's version 2 and any
  15. * later version the License.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <common.h>
  28. #include <asm/io.h>
  29. #include <asm/arch/dss.h>
  30. #include <video_fb.h>
  31. /* Configure VENC for a given Mode (NTSC / PAL) */
  32. void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
  33. u32 height, u32 width)
  34. {
  35. struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE;
  36. struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
  37. struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
  38. writel(venc_cfg->status, &venc->status);
  39. writel(venc_cfg->f_control, &venc->f_control);
  40. writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl);
  41. writel(venc_cfg->sync_ctrl, &venc->sync_ctrl);
  42. writel(venc_cfg->llen, &venc->llen);
  43. writel(venc_cfg->flens, &venc->flens);
  44. writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl);
  45. writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr);
  46. writel(venc_cfg->c_phase, &venc->c_phase);
  47. writel(venc_cfg->gain_u, &venc->gain_u);
  48. writel(venc_cfg->gain_v, &venc->gain_v);
  49. writel(venc_cfg->gain_y, &venc->gain_y);
  50. writel(venc_cfg->black_level, &venc->black_level);
  51. writel(venc_cfg->blank_level, &venc->blank_level);
  52. writel(venc_cfg->x_color, &venc->x_color);
  53. writel(venc_cfg->m_control, &venc->m_control);
  54. writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data);
  55. writel(venc_cfg->s_carr, &venc->s_carr);
  56. writel(venc_cfg->line21, &venc->line21);
  57. writel(venc_cfg->ln_sel, &venc->ln_sel);
  58. writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl);
  59. writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger);
  60. writel(venc_cfg->savid__eavid, &venc->savid__eavid);
  61. writel(venc_cfg->flen__fal, &venc->flen__fal);
  62. writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
  63. writel(venc_cfg->hs_int_start_stop_x, &venc->hs_int_start_stop_x);
  64. writel(venc_cfg->hs_ext_start_stop_x, &venc->hs_ext_start_stop_x);
  65. writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
  66. writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
  67. &venc->vs_int_stop_x__vs_int_start_y);
  68. writel(venc_cfg->vs_int_stop_y__vs_ext_start_x,
  69. &venc->vs_int_stop_y__vs_ext_start_x);
  70. writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y,
  71. &venc->vs_ext_stop_x__vs_ext_start_y);
  72. writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y);
  73. writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x);
  74. writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y);
  75. writel(venc_cfg->fid_int_start_x__fid_int_start_y,
  76. &venc->fid_int_start_x__fid_int_start_y);
  77. writel(venc_cfg->fid_int_offset_y__fid_ext_start_x,
  78. &venc->fid_int_offset_y__fid_ext_start_x);
  79. writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y,
  80. &venc->fid_ext_start_y__fid_ext_offset_y);
  81. writel(venc_cfg->tvdetgp_int_start_stop_x,
  82. &venc->tvdetgp_int_start_stop_x);
  83. writel(venc_cfg->tvdetgp_int_start_stop_y,
  84. &venc->tvdetgp_int_start_stop_y);
  85. writel(venc_cfg->gen_ctrl, &venc->gen_ctrl);
  86. writel(venc_cfg->output_control, &venc->output_control);
  87. writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
  88. /* Configure DSS for VENC Settings */
  89. writel(VENC_CLK_ENABLE | DAC_DEMEN | DAC_POWERDN | VENC_OUT_SEL,
  90. &dss->control);
  91. /* Configure height and width for Digital out */
  92. writel(height << DIG_LPP_SHIFT | width, &dispc->size_dig);
  93. }
  94. /* Configure Panel Specific Parameters */
  95. void omap3_dss_panel_config(const struct panel_config *panel_cfg)
  96. {
  97. struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
  98. struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
  99. writel(DSS_SOFTRESET, &dss->sysconfig);
  100. while (!(readl(&dss->sysstatus) & DSS_RESETDONE))
  101. ;
  102. writel(panel_cfg->timing_h, &dispc->timing_h);
  103. writel(panel_cfg->timing_v, &dispc->timing_v);
  104. writel(panel_cfg->pol_freq, &dispc->pol_freq);
  105. writel(panel_cfg->divisor, &dispc->divisor);
  106. writel(panel_cfg->lcd_size, &dispc->size_lcd);
  107. writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config);
  108. writel(panel_cfg->panel_type << TFTSTN_SHIFT |
  109. panel_cfg->data_lines << DATALINES_SHIFT, &dispc->control);
  110. writel(panel_cfg->panel_color, &dispc->default_color0);
  111. writel((u32) panel_cfg->frame_buffer, &dispc->gfx_ba0);
  112. if (!panel_cfg->frame_buffer)
  113. return;
  114. writel(panel_cfg->gfx_format | GFX_ENABLE, &dispc->gfx_attributes);
  115. writel(1, &dispc->gfx_row_inc);
  116. writel(1, &dispc->gfx_pixel_inc);
  117. writel(panel_cfg->lcd_size, &dispc->gfx_size);
  118. }
  119. /* Enable LCD and DIGITAL OUT in DSS */
  120. void omap3_dss_enable(void)
  121. {
  122. struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
  123. u32 l;
  124. l = readl(&dispc->control);
  125. l |= LCD_ENABLE | GO_LCD | DIG_ENABLE | GO_DIG | GP_OUT0 | GP_OUT1;
  126. writel(l, &dispc->control);
  127. }
  128. #ifdef CONFIG_CFB_CONSOLE
  129. int __board_video_init(void)
  130. {
  131. return -1;
  132. }
  133. int board_video_init(void)
  134. __attribute__((weak, alias("__board_video_init")));
  135. void *video_hw_init(void)
  136. {
  137. static GraphicDevice dssfb;
  138. GraphicDevice *pGD = &dssfb;
  139. struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
  140. if (board_video_init() || !readl(&dispc->gfx_ba0))
  141. return NULL;
  142. pGD->winSizeX = (readl(&dispc->size_lcd) & 0x7FF) + 1;
  143. pGD->winSizeY = ((readl(&dispc->size_lcd) >> 16) & 0x7FF) + 1;
  144. pGD->gdfBytesPP = 4;
  145. pGD->gdfIndex = GDF_32BIT_X888RGB;
  146. pGD->frameAdrs = readl(&dispc->gfx_ba0);
  147. return pGD;
  148. }
  149. #endif