s5pxx18_dp_mipi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Nexell Co., Ltd.
  4. *
  5. * Author: junghyun, kim <jhkim@nexell.co.kr>
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <asm/arch/nexell.h>
  11. #include <asm/arch/tieoff.h>
  12. #include <asm/arch/reset.h>
  13. #include <asm/arch/display.h>
  14. #include "soc/s5pxx18_soc_mipi.h"
  15. #include "soc/s5pxx18_soc_disptop.h"
  16. #include "soc/s5pxx18_soc_disptop_clk.h"
  17. #define PLLPMS_1000MHZ 0x33E8
  18. #define BANDCTL_1000MHZ 0xF
  19. #define PLLPMS_960MHZ 0x2280
  20. #define BANDCTL_960MHZ 0xF
  21. #define PLLPMS_900MHZ 0x2258
  22. #define BANDCTL_900MHZ 0xE
  23. #define PLLPMS_840MHZ 0x2230
  24. #define BANDCTL_840MHZ 0xD
  25. #define PLLPMS_750MHZ 0x43E8
  26. #define BANDCTL_750MHZ 0xC
  27. #define PLLPMS_660MHZ 0x21B8
  28. #define BANDCTL_660MHZ 0xB
  29. #define PLLPMS_600MHZ 0x2190
  30. #define BANDCTL_600MHZ 0xA
  31. #define PLLPMS_540MHZ 0x2168
  32. #define BANDCTL_540MHZ 0x9
  33. #define PLLPMS_512MHZ 0x03200
  34. #define BANDCTL_512MHZ 0x9
  35. #define PLLPMS_480MHZ 0x2281
  36. #define BANDCTL_480MHZ 0x8
  37. #define PLLPMS_420MHZ 0x2231
  38. #define BANDCTL_420MHZ 0x7
  39. #define PLLPMS_402MHZ 0x2219
  40. #define BANDCTL_402MHZ 0x7
  41. #define PLLPMS_330MHZ 0x21B9
  42. #define BANDCTL_330MHZ 0x6
  43. #define PLLPMS_300MHZ 0x2191
  44. #define BANDCTL_300MHZ 0x5
  45. #define PLLPMS_210MHZ 0x2232
  46. #define BANDCTL_210MHZ 0x4
  47. #define PLLPMS_180MHZ 0x21E2
  48. #define BANDCTL_180MHZ 0x3
  49. #define PLLPMS_150MHZ 0x2192
  50. #define BANDCTL_150MHZ 0x2
  51. #define PLLPMS_100MHZ 0x3323
  52. #define BANDCTL_100MHZ 0x1
  53. #define PLLPMS_80MHZ 0x3283
  54. #define BANDCTL_80MHZ 0x0
  55. #define MIPI_INDEX 0
  56. #define MIPI_EXC_PRE_VALUE 1
  57. #define MIPI_DSI_IRQ_MASK 29
  58. #define __io_address(a) (void *)(uintptr_t)(a)
  59. struct mipi_xfer_msg {
  60. u8 id, data[2];
  61. u16 flags;
  62. const u8 *tx_buf;
  63. u16 tx_len;
  64. u8 *rx_buf;
  65. u16 rx_len;
  66. };
  67. static void mipi_reset(void)
  68. {
  69. /* tieoff */
  70. nx_tieoff_set(NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3);
  71. nx_tieoff_set(NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3);
  72. /* reset */
  73. nx_rstcon_setrst(RESET_ID_MIPI, RSTCON_ASSERT);
  74. nx_rstcon_setrst(RESET_ID_MIPI_DSI, RSTCON_ASSERT);
  75. nx_rstcon_setrst(RESET_ID_MIPI_CSI, RSTCON_ASSERT);
  76. nx_rstcon_setrst(RESET_ID_MIPI_PHY_S, RSTCON_ASSERT);
  77. nx_rstcon_setrst(RESET_ID_MIPI_PHY_M, RSTCON_ASSERT);
  78. nx_rstcon_setrst(RESET_ID_MIPI, RSTCON_NEGATE);
  79. nx_rstcon_setrst(RESET_ID_MIPI_DSI, RSTCON_NEGATE);
  80. nx_rstcon_setrst(RESET_ID_MIPI_PHY_S, RSTCON_NEGATE);
  81. nx_rstcon_setrst(RESET_ID_MIPI_PHY_M, RSTCON_NEGATE);
  82. }
  83. static void mipi_init(void)
  84. {
  85. int clkid = DP_CLOCK_MIPI;
  86. void *base;
  87. /*
  88. * neet to reset before open
  89. */
  90. mipi_reset();
  91. base = __io_address(nx_disp_top_clkgen_get_physical_address(clkid));
  92. nx_disp_top_clkgen_set_base_address(clkid, base);
  93. nx_disp_top_clkgen_set_clock_pclk_mode(clkid, nx_pclkmode_always);
  94. base = __io_address(nx_mipi_get_physical_address(0));
  95. nx_mipi_set_base_address(0, base);
  96. }
  97. static int mipi_get_phy_pll(int bitrate, unsigned int *pllpms,
  98. unsigned int *bandctl)
  99. {
  100. unsigned int pms, ctl;
  101. switch (bitrate) {
  102. case 1000:
  103. pms = PLLPMS_1000MHZ;
  104. ctl = BANDCTL_1000MHZ;
  105. break;
  106. case 960:
  107. pms = PLLPMS_960MHZ;
  108. ctl = BANDCTL_960MHZ;
  109. break;
  110. case 900:
  111. pms = PLLPMS_900MHZ;
  112. ctl = BANDCTL_900MHZ;
  113. break;
  114. case 840:
  115. pms = PLLPMS_840MHZ;
  116. ctl = BANDCTL_840MHZ;
  117. break;
  118. case 750:
  119. pms = PLLPMS_750MHZ;
  120. ctl = BANDCTL_750MHZ;
  121. break;
  122. case 660:
  123. pms = PLLPMS_660MHZ;
  124. ctl = BANDCTL_660MHZ;
  125. break;
  126. case 600:
  127. pms = PLLPMS_600MHZ;
  128. ctl = BANDCTL_600MHZ;
  129. break;
  130. case 540:
  131. pms = PLLPMS_540MHZ;
  132. ctl = BANDCTL_540MHZ;
  133. break;
  134. case 512:
  135. pms = PLLPMS_512MHZ;
  136. ctl = BANDCTL_512MHZ;
  137. break;
  138. case 480:
  139. pms = PLLPMS_480MHZ;
  140. ctl = BANDCTL_480MHZ;
  141. break;
  142. case 420:
  143. pms = PLLPMS_420MHZ;
  144. ctl = BANDCTL_420MHZ;
  145. break;
  146. case 402:
  147. pms = PLLPMS_402MHZ;
  148. ctl = BANDCTL_402MHZ;
  149. break;
  150. case 330:
  151. pms = PLLPMS_330MHZ;
  152. ctl = BANDCTL_330MHZ;
  153. break;
  154. case 300:
  155. pms = PLLPMS_300MHZ;
  156. ctl = BANDCTL_300MHZ;
  157. break;
  158. case 210:
  159. pms = PLLPMS_210MHZ;
  160. ctl = BANDCTL_210MHZ;
  161. break;
  162. case 180:
  163. pms = PLLPMS_180MHZ;
  164. ctl = BANDCTL_180MHZ;
  165. break;
  166. case 150:
  167. pms = PLLPMS_150MHZ;
  168. ctl = BANDCTL_150MHZ;
  169. break;
  170. case 100:
  171. pms = PLLPMS_100MHZ;
  172. ctl = BANDCTL_100MHZ;
  173. break;
  174. case 80:
  175. pms = PLLPMS_80MHZ;
  176. ctl = BANDCTL_80MHZ;
  177. break;
  178. default:
  179. return -EINVAL;
  180. }
  181. *pllpms = pms;
  182. *bandctl = ctl;
  183. return 0;
  184. }
  185. static int mipi_prepare(int module, int input,
  186. struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
  187. struct dp_mipi_dev *mipi)
  188. {
  189. int index = MIPI_INDEX;
  190. u32 esc_pre_value = MIPI_EXC_PRE_VALUE;
  191. int lpm = mipi->lpm_trans;
  192. int ret = 0;
  193. ret = mipi_get_phy_pll(mipi->hs_bitrate,
  194. &mipi->hs_pllpms, &mipi->hs_bandctl);
  195. if (ret < 0)
  196. return ret;
  197. ret = mipi_get_phy_pll(mipi->lp_bitrate,
  198. &mipi->lp_pllpms, &mipi->lp_bandctl);
  199. if (ret < 0)
  200. return ret;
  201. debug("%s: mipi lp:%dmhz:0x%x:0x%x, hs:%dmhz:0x%x:0x%x, %s trans\n",
  202. __func__, mipi->lp_bitrate, mipi->lp_pllpms, mipi->lp_bandctl,
  203. mipi->hs_bitrate, mipi->hs_pllpms, mipi->hs_bandctl,
  204. lpm ? "low" : "high");
  205. if (lpm)
  206. nx_mipi_dsi_set_pll(index, 1, 0xFFFFFFFF,
  207. mipi->lp_pllpms, mipi->lp_bandctl, 0, 0);
  208. else
  209. nx_mipi_dsi_set_pll(index, 1, 0xFFFFFFFF,
  210. mipi->hs_pllpms, mipi->hs_bandctl, 0, 0);
  211. #ifdef CONFIG_ARCH_S5P4418
  212. /*
  213. * disable the escape clock generating prescaler
  214. * before soft reset.
  215. */
  216. nx_mipi_dsi_set_clock(index, 0, 0, 1, 1, 1, 0, 0, 0, 0, 10);
  217. mdelay(1);
  218. #endif
  219. nx_mipi_dsi_software_reset(index);
  220. nx_mipi_dsi_set_clock(index, 0, 0, 1, 1, 1, 0, 0, 0, 1, esc_pre_value);
  221. nx_mipi_dsi_set_phy(index, 0, 1, 1, 0, 0, 0, 0, 0);
  222. if (lpm)
  223. nx_mipi_dsi_set_escape_lp(index, nx_mipi_dsi_lpmode_lp,
  224. nx_mipi_dsi_lpmode_lp);
  225. else
  226. nx_mipi_dsi_set_escape_lp(index, nx_mipi_dsi_lpmode_hs,
  227. nx_mipi_dsi_lpmode_hs);
  228. mdelay(20);
  229. return 0;
  230. }
  231. static int mipi_enable(int module, int input,
  232. struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
  233. struct dp_mipi_dev *mipi)
  234. {
  235. struct mipi_dsi_device *dsi = &mipi->dsi;
  236. int clkid = DP_CLOCK_MIPI;
  237. int index = MIPI_INDEX;
  238. int width = sync->h_active_len;
  239. int height = sync->v_active_len;
  240. int HFP = sync->h_front_porch;
  241. int HBP = sync->h_back_porch;
  242. int HS = sync->h_sync_width;
  243. int VFP = sync->v_front_porch;
  244. int VBP = sync->v_back_porch;
  245. int VS = sync->v_sync_width;
  246. int en_prescaler = 1;
  247. u32 esc_pre_value = MIPI_EXC_PRE_VALUE;
  248. int txhsclock = 1;
  249. int lpm = mipi->lpm_trans;
  250. bool command_mode = mipi->command_mode;
  251. enum nx_mipi_dsi_format dsi_format;
  252. int data_len = dsi->lanes - 1;
  253. bool burst = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? true : false;
  254. bool eot_enable = dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET ?
  255. false : true;
  256. /*
  257. * disable the escape clock generating prescaler
  258. * before soft reset.
  259. */
  260. #ifdef CONFIG_ARCH_S5P4418
  261. en_prescaler = 0;
  262. #endif
  263. debug("%s: mode:%s, lanes.%d\n", __func__,
  264. command_mode ? "command" : "video", data_len + 1);
  265. if (lpm)
  266. nx_mipi_dsi_set_escape_lp(index,
  267. nx_mipi_dsi_lpmode_hs,
  268. nx_mipi_dsi_lpmode_hs);
  269. nx_mipi_dsi_set_pll(index, 1, 0xFFFFFFFF,
  270. mipi->hs_pllpms, mipi->hs_bandctl, 0, 0);
  271. mdelay(1);
  272. nx_mipi_dsi_set_clock(index, 0, 0, 1, 1, 1, 0, 0, 0, en_prescaler, 10);
  273. mdelay(1);
  274. nx_mipi_dsi_software_reset(index);
  275. nx_mipi_dsi_set_clock(index, txhsclock, 0, 1,
  276. 1, 1, 0, 0, 0, 1, esc_pre_value);
  277. switch (data_len) {
  278. case 0: /* 1 lane */
  279. nx_mipi_dsi_set_phy(index, data_len, 1, 1, 0, 0, 0, 0, 0);
  280. break;
  281. case 1: /* 2 lane */
  282. nx_mipi_dsi_set_phy(index, data_len, 1, 1, 1, 0, 0, 0, 0);
  283. break;
  284. case 2: /* 3 lane */
  285. nx_mipi_dsi_set_phy(index, data_len, 1, 1, 1, 1, 0, 0, 0);
  286. break;
  287. case 3: /* 3 lane */
  288. nx_mipi_dsi_set_phy(index, data_len, 1, 1, 1, 1, 1, 0, 0);
  289. break;
  290. default:
  291. printf("%s: not support data lanes %d\n",
  292. __func__, data_len + 1);
  293. return -EINVAL;
  294. }
  295. switch (dsi->format) {
  296. case MIPI_DSI_FMT_RGB565:
  297. dsi_format = nx_mipi_dsi_format_rgb565;
  298. break;
  299. case MIPI_DSI_FMT_RGB666:
  300. dsi_format = nx_mipi_dsi_format_rgb666;
  301. break;
  302. case MIPI_DSI_FMT_RGB666_PACKED:
  303. dsi_format = nx_mipi_dsi_format_rgb666_packed;
  304. break;
  305. case MIPI_DSI_FMT_RGB888:
  306. dsi_format = nx_mipi_dsi_format_rgb888;
  307. break;
  308. default:
  309. printf("%s: not support format %d\n", __func__, dsi->format);
  310. return -EINVAL;
  311. }
  312. nx_mipi_dsi_set_config_video_mode(index, 1, 0, burst,
  313. nx_mipi_dsi_syncmode_event,
  314. eot_enable, 1, 1, 1, 1, 0, dsi_format,
  315. HFP, HBP, HS, VFP, VBP, VS, 0);
  316. nx_mipi_dsi_set_size(index, width, height);
  317. /* set mux */
  318. nx_disp_top_set_mipimux(1, module);
  319. /* 0 is spdif, 1 is mipi vclk */
  320. nx_disp_top_clkgen_set_clock_source(clkid, 1, ctrl->clk_src_lv0);
  321. nx_disp_top_clkgen_set_clock_divisor(clkid, 1,
  322. ctrl->clk_div_lv1 *
  323. ctrl->clk_div_lv0);
  324. /* SPDIF and MIPI */
  325. nx_disp_top_clkgen_set_clock_divisor_enable(clkid, 1);
  326. /* START: CLKGEN, MIPI is started in setup function */
  327. nx_disp_top_clkgen_set_clock_divisor_enable(clkid, true);
  328. nx_mipi_dsi_set_enable(index, true);
  329. return 0;
  330. }
  331. static int nx_mipi_transfer_tx(struct mipi_dsi_device *dsi,
  332. struct mipi_xfer_msg *xfer)
  333. {
  334. const u8 *txb;
  335. int size, index = 0;
  336. u32 data;
  337. if (xfer->tx_len > DSI_TX_FIFO_SIZE)
  338. printf("warn: tx %d size over fifo %d\n",
  339. (int)xfer->tx_len, DSI_TX_FIFO_SIZE);
  340. /* write payload */
  341. size = xfer->tx_len;
  342. txb = xfer->tx_buf;
  343. while (size >= 4) {
  344. data = (txb[3] << 24) | (txb[2] << 16) |
  345. (txb[1] << 8) | (txb[0]);
  346. nx_mipi_dsi_write_payload(index, data);
  347. txb += 4, size -= 4;
  348. data = 0;
  349. }
  350. switch (size) {
  351. case 3:
  352. data |= txb[2] << 16;
  353. case 2:
  354. data |= txb[1] << 8;
  355. case 1:
  356. data |= txb[0];
  357. nx_mipi_dsi_write_payload(index, data);
  358. break;
  359. case 0:
  360. break; /* no payload */
  361. }
  362. /* write packet hdr */
  363. data = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->id;
  364. nx_mipi_dsi_write_pkheader(index, data);
  365. return 0;
  366. }
  367. static int nx_mipi_transfer_done(struct mipi_dsi_device *dsi)
  368. {
  369. int index = 0, count = 100;
  370. u32 value;
  371. do {
  372. mdelay(1);
  373. value = nx_mipi_dsi_read_fifo_status(index);
  374. if (((1 << 22) & value))
  375. break;
  376. } while (count-- > 0);
  377. if (count < 0)
  378. return -EINVAL;
  379. return 0;
  380. }
  381. static int nx_mipi_transfer_rx(struct mipi_dsi_device *dsi,
  382. struct mipi_xfer_msg *xfer)
  383. {
  384. u8 *rxb = xfer->rx_buf;
  385. int index = 0, rx_len = 0;
  386. u32 data, count = 0;
  387. u16 size;
  388. int err = -EINVAL;
  389. nx_mipi_dsi_clear_interrupt_pending(index, 18);
  390. while (1) {
  391. /* Completes receiving data. */
  392. if (nx_mipi_dsi_get_interrupt_pending(index, 18))
  393. break;
  394. mdelay(1);
  395. if (count > 500) {
  396. printf("%s: error recevice data\n", __func__);
  397. err = -EINVAL;
  398. goto clear_fifo;
  399. } else {
  400. count++;
  401. }
  402. }
  403. data = nx_mipi_dsi_read_fifo(index);
  404. switch (data & 0x3f) {
  405. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
  406. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
  407. if (xfer->rx_len >= 2) {
  408. rxb[1] = data >> 16;
  409. rx_len++;
  410. }
  411. /* Fall through */
  412. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
  413. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
  414. rxb[0] = data >> 8;
  415. rx_len++;
  416. xfer->rx_len = rx_len;
  417. err = rx_len;
  418. goto clear_fifo;
  419. case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
  420. printf("DSI Error Report: 0x%04x\n", (data >> 8) & 0xffff);
  421. err = rx_len;
  422. goto clear_fifo;
  423. }
  424. size = (data >> 8) & 0xffff;
  425. if (size > xfer->rx_len)
  426. size = xfer->rx_len;
  427. else if (size < xfer->rx_len)
  428. xfer->rx_len = size;
  429. size = xfer->rx_len - rx_len;
  430. rx_len += size;
  431. /* Receive payload */
  432. while (size >= 4) {
  433. data = nx_mipi_dsi_read_fifo(index);
  434. rxb[0] = (data >> 0) & 0xff;
  435. rxb[1] = (data >> 8) & 0xff;
  436. rxb[2] = (data >> 16) & 0xff;
  437. rxb[3] = (data >> 24) & 0xff;
  438. rxb += 4, size -= 4;
  439. }
  440. if (size) {
  441. data = nx_mipi_dsi_read_fifo(index);
  442. switch (size) {
  443. case 3:
  444. rxb[2] = (data >> 16) & 0xff;
  445. case 2:
  446. rxb[1] = (data >> 8) & 0xff;
  447. case 1:
  448. rxb[0] = data & 0xff;
  449. }
  450. }
  451. if (rx_len == xfer->rx_len)
  452. err = rx_len;
  453. clear_fifo:
  454. size = DSI_RX_FIFO_SIZE / 4;
  455. do {
  456. data = nx_mipi_dsi_read_fifo(index);
  457. if (data == DSI_RX_FIFO_EMPTY)
  458. break;
  459. } while (--size);
  460. return err;
  461. }
  462. #define IS_SHORT(t) (9 > ((t) & 0x0f))
  463. static int nx_mipi_transfer(struct mipi_dsi_device *dsi,
  464. const struct mipi_dsi_msg *msg)
  465. {
  466. struct mipi_xfer_msg xfer;
  467. int err;
  468. if (!msg->tx_len)
  469. return -EINVAL;
  470. /* set id */
  471. xfer.id = msg->type | (msg->channel << 6);
  472. /* short type msg */
  473. if (IS_SHORT(msg->type)) {
  474. const char *txb = msg->tx_buf;
  475. if (msg->tx_len > 2)
  476. return -EINVAL;
  477. xfer.tx_len = 0; /* no payload */
  478. xfer.data[0] = txb[0];
  479. xfer.data[1] = (msg->tx_len == 2) ? txb[1] : 0;
  480. xfer.tx_buf = NULL;
  481. } else {
  482. xfer.tx_len = msg->tx_len;
  483. xfer.data[0] = msg->tx_len & 0xff;
  484. xfer.data[1] = msg->tx_len >> 8;
  485. xfer.tx_buf = msg->tx_buf;
  486. }
  487. xfer.rx_len = msg->rx_len;
  488. xfer.rx_buf = msg->rx_buf;
  489. xfer.flags = msg->flags;
  490. err = nx_mipi_transfer_tx(dsi, &xfer);
  491. if (xfer.rx_len)
  492. err = nx_mipi_transfer_rx(dsi, &xfer);
  493. nx_mipi_transfer_done(dsi);
  494. return err;
  495. }
  496. static ssize_t nx_mipi_write_buffer(struct mipi_dsi_device *dsi,
  497. const void *data, size_t len)
  498. {
  499. struct mipi_dsi_msg msg = {
  500. .channel = dsi->channel,
  501. .tx_buf = data,
  502. .tx_len = len
  503. };
  504. switch (len) {
  505. case 0:
  506. return -EINVAL;
  507. case 1:
  508. msg.type = MIPI_DSI_DCS_SHORT_WRITE;
  509. break;
  510. case 2:
  511. msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
  512. break;
  513. default:
  514. msg.type = MIPI_DSI_DCS_LONG_WRITE;
  515. break;
  516. }
  517. if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
  518. msg.flags |= MIPI_DSI_MSG_USE_LPM;
  519. return nx_mipi_transfer(dsi, &msg);
  520. }
  521. __weak int nx_mipi_dsi_lcd_bind(struct mipi_dsi_device *dsi)
  522. {
  523. return 0;
  524. }
  525. /*
  526. * disply
  527. * MIPI DSI Setting
  528. * (1) Initiallize MIPI(DSIM,DPHY,PLL)
  529. * (2) Initiallize LCD
  530. * (3) ReInitiallize MIPI(DSIM only)
  531. * (4) Turn on display(MLC,DPC,...)
  532. */
  533. void nx_mipi_display(int module,
  534. struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
  535. struct dp_plane_top *top, struct dp_plane_info *planes,
  536. struct dp_mipi_dev *dev)
  537. {
  538. struct dp_plane_info *plane = planes;
  539. struct mipi_dsi_device *dsi = &dev->dsi;
  540. int input = module == 0 ? DP_DEVICE_DP0 : DP_DEVICE_DP1;
  541. int count = top->plane_num;
  542. int i = 0, ret;
  543. printf("MIPI: dp.%d\n", module);
  544. /* map mipi-dsi write callback func */
  545. dsi->write_buffer = nx_mipi_write_buffer;
  546. ret = nx_mipi_dsi_lcd_bind(dsi);
  547. if (ret) {
  548. printf("Error: bind mipi-dsi lcd driver !\n");
  549. return;
  550. }
  551. dp_control_init(module);
  552. dp_plane_init(module);
  553. mipi_init();
  554. /* set plane */
  555. dp_plane_screen_setup(module, top);
  556. for (i = 0; count > i; i++, plane++) {
  557. if (!plane->enable)
  558. continue;
  559. dp_plane_layer_setup(module, plane);
  560. dp_plane_layer_enable(module, plane, 1);
  561. }
  562. dp_plane_screen_enable(module, 1);
  563. /* set mipi */
  564. mipi_prepare(module, input, sync, ctrl, dev);
  565. if (dsi->ops && dsi->ops->prepare)
  566. dsi->ops->prepare(dsi);
  567. if (dsi->ops && dsi->ops->enable)
  568. dsi->ops->enable(dsi);
  569. mipi_enable(module, input, sync, ctrl, dev);
  570. /* set dp control */
  571. dp_control_setup(module, sync, ctrl);
  572. dp_control_enable(module, 1);
  573. }