s5pxx18_dp_lvds.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Nexell Co., Ltd.
  4. *
  5. * Author: junghyun, kim <jhkim@nexell.co.kr>
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <asm/arch/nexell.h>
  11. #include <asm/arch/reset.h>
  12. #include <asm/arch/display.h>
  13. #include "soc/s5pxx18_soc_lvds.h"
  14. #include "soc/s5pxx18_soc_disptop.h"
  15. #include "soc/s5pxx18_soc_disptop_clk.h"
  16. #define __io_address(a) (void *)(uintptr_t)(a)
  17. static void lvds_phy_reset(void)
  18. {
  19. nx_rstcon_setrst(RESET_ID_LVDS, RSTCON_ASSERT);
  20. nx_rstcon_setrst(RESET_ID_LVDS, RSTCON_NEGATE);
  21. }
  22. static void lvds_init(void)
  23. {
  24. int clkid = DP_CLOCK_LVDS;
  25. int index = 0;
  26. void *base;
  27. base = __io_address(nx_disp_top_clkgen_get_physical_address(clkid));
  28. nx_disp_top_clkgen_set_base_address(clkid, base);
  29. nx_lvds_initialize();
  30. for (index = 0; nx_lvds_get_number_of_module() > index; index++)
  31. nx_lvds_set_base_address(index,
  32. (void *)__io_address(nx_lvds_get_physical_address(index)));
  33. nx_disp_top_clkgen_set_clock_pclk_mode(clkid, nx_pclkmode_always);
  34. }
  35. static void lvds_enable(int enable)
  36. {
  37. int clkid = DP_CLOCK_LVDS;
  38. int on = (enable ? 1 : 0);
  39. nx_disp_top_clkgen_set_clock_divisor_enable(clkid, on);
  40. }
  41. static int lvds_setup(int module, int input,
  42. struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
  43. struct dp_lvds_dev *dev)
  44. {
  45. unsigned int val;
  46. int clkid = DP_CLOCK_LVDS;
  47. enum dp_lvds_format format = DP_LVDS_FORMAT_JEIDA;
  48. u32 voltage = DEF_VOLTAGE_LEVEL;
  49. if (dev) {
  50. format = dev->lvds_format;
  51. voltage = dev->voltage_level;
  52. }
  53. printf("LVDS: ");
  54. printf("%s, ", format == DP_LVDS_FORMAT_VESA ? "VESA" :
  55. format == DP_LVDS_FORMAT_JEIDA ? "JEIDA" : "LOC");
  56. printf("voltage LV:0x%x\n", voltage);
  57. /*
  58. *-------- predefined type.
  59. * only change iTA to iTE in VESA mode
  60. * wire [34:0] loc_VideoIn =
  61. * {4'hf, 4'h0, i_VDEN, i_VSYNC, i_HSYNC, i_VD[23:0] };
  62. */
  63. u32 VSYNC = 25;
  64. u32 HSYNC = 24;
  65. u32 VDEN = 26; /* bit position */
  66. u32 ONE = 34;
  67. u32 ZERO = 27;
  68. /*====================================================
  69. * current not use location mode
  70. *====================================================
  71. */
  72. u32 LOC_A[7] = {ONE, ONE, ONE, ONE, ONE, ONE, ONE};
  73. u32 LOC_B[7] = {ONE, ONE, ONE, ONE, ONE, ONE, ONE};
  74. u32 LOC_C[7] = {VDEN, VSYNC, HSYNC, ONE, HSYNC, VSYNC, VDEN};
  75. u32 LOC_D[7] = {ZERO, ZERO, ZERO, ZERO, ZERO, ZERO, ZERO};
  76. u32 LOC_E[7] = {ZERO, ZERO, ZERO, ZERO, ZERO, ZERO, ZERO};
  77. switch (input) {
  78. case DP_DEVICE_DP0:
  79. input = 0;
  80. break;
  81. case DP_DEVICE_DP1:
  82. input = 1;
  83. break;
  84. case DP_DEVICE_RESCONV:
  85. input = 2;
  86. break;
  87. default:
  88. return -EINVAL;
  89. }
  90. /*
  91. * select TOP MUX
  92. */
  93. nx_disp_top_clkgen_set_clock_divisor_enable(clkid, 0);
  94. nx_disp_top_clkgen_set_clock_source(clkid, 0, ctrl->clk_src_lv0);
  95. nx_disp_top_clkgen_set_clock_divisor(clkid, 0, ctrl->clk_div_lv0);
  96. nx_disp_top_clkgen_set_clock_source(clkid, 1, ctrl->clk_src_lv1);
  97. nx_disp_top_clkgen_set_clock_divisor(clkid, 1, ctrl->clk_div_lv1);
  98. /*
  99. * LVDS Control Pin Setting
  100. */
  101. val = (0 << 30) | /* CPU_I_VBLK_FLAG_SEL */
  102. (0 << 29) | /* CPU_I_BVLK_FLAG */
  103. (1 << 28) | /* SKINI_BST */
  104. (1 << 27) | /* DLYS_BST */
  105. (0 << 26) | /* I_AUTO_SEL */
  106. (format << 19) | /* JEiDA data packing */
  107. (0x1B << 13) | /* I_LOCK_PPM_SET, PPM setting for PLL lock */
  108. (0x638 << 1); /* I_DESKEW_CNT_SEL, period of de-skew region */
  109. nx_lvds_set_lvdsctrl0(0, val);
  110. val = (0 << 28) | /* I_ATE_MODE, function mode */
  111. (0 << 27) | /* I_TEST_CON_MODE, DA (test ctrl mode) */
  112. (0 << 24) | /* I_TX4010X_DUMMY */
  113. (0 << 15) | /* SKCCK 0 */
  114. (0 << 12) | /* SKC4 (TX output skew control pin at ODD ch4) */
  115. (0 << 9) | /* SKC3 (TX output skew control pin at ODD ch3) */
  116. (0 << 6) | /* SKC2 (TX output skew control pin at ODD ch2) */
  117. (0 << 3) | /* SKC1 (TX output skew control pin at ODD ch1) */
  118. (0 << 0); /* SKC0 (TX output skew control pin at ODD ch0) */
  119. nx_lvds_set_lvdsctrl1(0, val);
  120. val = (0 << 15) | /* CK_POL_SEL, Input clock, bypass */
  121. (0 << 14) | /* VSEL, VCO Freq. range. 0: Low(40MHz~90MHz),
  122. * 1: High(90MHz~160MHz) */
  123. (0x1 << 12) | /* S (Post-scaler) */
  124. (0xA << 6) | /* M (Main divider) */
  125. (0xA << 0); /* P (Pre-divider) */
  126. nx_lvds_set_lvdsctrl2(0, val);
  127. val = (0x03 << 6) | /* SK_BIAS, Bias current ctrl pin */
  128. (0 << 5) | /* SKEWINI, skew selection pin, 0: bypass,
  129. * 1: skew enable */
  130. (0 << 4) | /* SKEW_EN_H, skew block power down, 0: power down,
  131. * 1: operating */
  132. (1 << 3) | /* CNTB_TDLY, delay control pin */
  133. (0 << 2) | /* SEL_DATABF, input clock 1/2 division cont. pin */
  134. (0x3 << 0); /* SKEW_REG_CUR, regulator bias current selection
  135. * in SKEW block */
  136. nx_lvds_set_lvdsctrl3(0, val);
  137. val = (0 << 28) | /* FLT_CNT, filter control pin for PLL */
  138. (0 << 27) | /* VOD_ONLY_CNT, the pre-emphasis's pre-diriver
  139. * control pin (VOD only) */
  140. (0 << 26) | /* CNNCT_MODE_SEL, connectivity mode selection,
  141. * 0:TX operating, 1:con check */
  142. (0 << 24) | /* CNNCT_CNT, connectivity ctrl pin,
  143. * 0: tx operating, 1: con check */
  144. (0 << 23) | /* VOD_HIGH_S, VOD control pin, 1: Vod only */
  145. (0 << 22) | /* SRC_TRH, source termination resistor sel. pin */
  146. (voltage << 14) |
  147. (0x01 << 6) | /* CNT_PEN_H, TX driver pre-emphasis level cont. */
  148. (0x4 << 3) | /* FC_CODE, vos control pin */
  149. (0 << 2) | /* OUTCON, TX Driver state selectioin pin, 0:Hi-z,
  150. * 1:Low */
  151. (0 << 1) | /* LOCK_CNT, Lock signal selection pin, enable */
  152. (0 << 0); /* AUTO_DSK_SEL, auto deskew sel. pin, normal */
  153. nx_lvds_set_lvdsctrl4(0, val);
  154. val = (0 << 24) | /* I_BIST_RESETB */
  155. (0 << 23) | /* I_BIST_EN */
  156. (0 << 21) | /* I_BIST_PAT_SEL */
  157. (0 << 14) | /* I_BIST_USER_PATTERN */
  158. (0 << 13) | /* I_BIST_FORCE_ERROR */
  159. (0 << 7) | /* I_BIST_SKEW_CTRL */
  160. (0 << 5) | /* I_BIST_CLK_INV */
  161. (0 << 3) | /* I_BIST_DATA_INV */
  162. (0 << 0); /* I_BIST_CH_SEL */
  163. nx_lvds_set_lvdstmode0(0, val);
  164. /* user do not need to modify this codes. */
  165. val = (LOC_A[4] << 24) | (LOC_A[3] << 18) | (LOC_A[2] << 12) |
  166. (LOC_A[1] << 6) | (LOC_A[0] << 0);
  167. nx_lvds_set_lvdsloc0(0, val);
  168. val = (LOC_B[2] << 24) | (LOC_B[1] << 18) | (LOC_B[0] << 12) |
  169. (LOC_A[6] << 6) | (LOC_A[5] << 0);
  170. nx_lvds_set_lvdsloc1(0, val);
  171. val = (LOC_C[0] << 24) | (LOC_B[6] << 18) | (LOC_B[5] << 12) |
  172. (LOC_B[4] << 6) | (LOC_B[3] << 0);
  173. nx_lvds_set_lvdsloc2(0, val);
  174. val = (LOC_C[5] << 24) | (LOC_C[4] << 18) | (LOC_C[3] << 12) |
  175. (LOC_C[2] << 6) | (LOC_C[1] << 0);
  176. nx_lvds_set_lvdsloc3(0, val);
  177. val = (LOC_D[3] << 24) | (LOC_D[2] << 18) | (LOC_D[1] << 12) |
  178. (LOC_D[0] << 6) | (LOC_C[6] << 0);
  179. nx_lvds_set_lvdsloc4(0, val);
  180. val = (LOC_E[1] << 24) | (LOC_E[0] << 18) | (LOC_D[6] << 12) |
  181. (LOC_D[5] << 6) | (LOC_D[4] << 0);
  182. nx_lvds_set_lvdsloc5(0, val);
  183. val = (LOC_E[6] << 24) | (LOC_E[5] << 18) | (LOC_E[4] << 12) |
  184. (LOC_E[3] << 6) | (LOC_E[2] << 0);
  185. nx_lvds_set_lvdsloc6(0, val);
  186. nx_lvds_set_lvdslocmask0(0, 0xffffffff);
  187. nx_lvds_set_lvdslocmask1(0, 0xffffffff);
  188. nx_lvds_set_lvdslocpol0(0, (0 << 19) | (0 << 18));
  189. /*
  190. * select TOP MUX
  191. */
  192. nx_disp_top_set_lvdsmux(1, input);
  193. /*
  194. * LVDS PHY Reset, make sure last.
  195. */
  196. lvds_phy_reset();
  197. return 0;
  198. }
  199. void nx_lvds_display(int module,
  200. struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
  201. struct dp_plane_top *top, struct dp_plane_info *planes,
  202. struct dp_lvds_dev *dev)
  203. {
  204. struct dp_plane_info *plane = planes;
  205. int input = module == 0 ? DP_DEVICE_DP0 : DP_DEVICE_DP1;
  206. int count = top->plane_num;
  207. int i = 0;
  208. printf("LVDS: dp.%d\n", module);
  209. dp_control_init(module);
  210. dp_plane_init(module);
  211. lvds_init();
  212. /* set plane */
  213. dp_plane_screen_setup(module, top);
  214. for (i = 0; count > i; i++, plane++) {
  215. if (!plane->enable)
  216. continue;
  217. dp_plane_layer_setup(module, plane);
  218. dp_plane_layer_enable(module, plane, 1);
  219. }
  220. dp_plane_screen_enable(module, 1);
  221. /* set lvds */
  222. lvds_setup(module, input, sync, ctrl, dev);
  223. lvds_enable(1);
  224. /* set dp control */
  225. dp_control_setup(module, sync, ctrl);
  226. dp_control_enable(module, 1);
  227. }