s5pxx18_dp.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Nexell Co., Ltd.
  4. *
  5. * Author: junghyun, kim <jhkim@nexell.co.kr>
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <log.h>
  11. #include <asm/arch/reset.h>
  12. #include <asm/arch/nexell.h>
  13. #include <asm/arch/display.h>
  14. #include "soc/s5pxx18_soc_disptop.h"
  15. #include "soc/s5pxx18_soc_dpc.h"
  16. #include "soc/s5pxx18_soc_mlc.h"
  17. #define MLC_LAYER_RGB_0 0 /* number of RGB layer 0 */
  18. #define MLC_LAYER_RGB_1 1 /* number of RGB layer 1 */
  19. #define MLC_LAYER_VIDEO 3 /* number of Video layer: 3 = VIDEO */
  20. #define __io_address(a) (void *)(uintptr_t)(a)
  21. void dp_control_init(int module)
  22. {
  23. void *base;
  24. /* top */
  25. base = __io_address(nx_disp_top_get_physical_address());
  26. nx_disp_top_set_base_address(base);
  27. /* control */
  28. base = __io_address(nx_dpc_get_physical_address(module));
  29. nx_dpc_set_base_address(module, base);
  30. /* top controller */
  31. nx_rstcon_setrst(RESET_ID_DISP_TOP, RSTCON_ASSERT);
  32. nx_rstcon_setrst(RESET_ID_DISP_TOP, RSTCON_NEGATE);
  33. /* display controller */
  34. nx_rstcon_setrst(RESET_ID_DISPLAY, RSTCON_ASSERT);
  35. nx_rstcon_setrst(RESET_ID_DISPLAY, RSTCON_NEGATE);
  36. nx_dpc_set_clock_pclk_mode(module, nx_pclkmode_always);
  37. }
  38. int dp_control_setup(int module,
  39. struct dp_sync_info *sync, struct dp_ctrl_info *ctrl)
  40. {
  41. unsigned int out_format;
  42. unsigned int delay_mask;
  43. int rgb_pvd = 0, hsync_cp1 = 7, vsync_fram = 7, de_cp2 = 7;
  44. int v_vso = 1, v_veo = 1, e_vso = 1, e_veo = 1;
  45. int interlace = 0;
  46. int invert_field;
  47. int swap_rb;
  48. unsigned int yc_order;
  49. int vck_select;
  50. int vclk_invert;
  51. int emb_sync;
  52. enum nx_dpc_dither r_dither, g_dither, b_dither;
  53. int rgb_mode = 0;
  54. if (NULL == sync || NULL == ctrl) {
  55. debug("error, dp.%d not set sync or pad clock info !!!\n",
  56. module);
  57. return -EINVAL;
  58. }
  59. out_format = ctrl->out_format;
  60. delay_mask = ctrl->delay_mask;
  61. interlace = sync->interlace;
  62. invert_field = ctrl->invert_field;
  63. swap_rb = ctrl->swap_RB;
  64. yc_order = ctrl->yc_order;
  65. vck_select = ctrl->vck_select;
  66. vclk_invert = ctrl->clk_inv_lv0 | ctrl->clk_inv_lv1;
  67. emb_sync = (out_format == DPC_FORMAT_CCIR656 ? 1 : 0);
  68. /* set delay mask */
  69. if (delay_mask & DP_SYNC_DELAY_RGB_PVD)
  70. rgb_pvd = ctrl->d_rgb_pvd;
  71. if (delay_mask & DP_SYNC_DELAY_HSYNC_CP1)
  72. hsync_cp1 = ctrl->d_hsync_cp1;
  73. if (delay_mask & DP_SYNC_DELAY_VSYNC_FRAM)
  74. vsync_fram = ctrl->d_vsync_fram;
  75. if (delay_mask & DP_SYNC_DELAY_DE_CP)
  76. de_cp2 = ctrl->d_de_cp2;
  77. if (ctrl->vs_start_offset != 0 ||
  78. ctrl->vs_end_offset != 0 ||
  79. ctrl->ev_start_offset != 0 || ctrl->ev_end_offset != 0) {
  80. v_vso = ctrl->vs_start_offset;
  81. v_veo = ctrl->vs_end_offset;
  82. e_vso = ctrl->ev_start_offset;
  83. e_veo = ctrl->ev_end_offset;
  84. }
  85. if (nx_dpc_format_rgb555 == out_format ||
  86. nx_dpc_format_mrgb555a == out_format ||
  87. nx_dpc_format_mrgb555b == out_format) {
  88. r_dither = nx_dpc_dither_5bit;
  89. g_dither = nx_dpc_dither_5bit;
  90. b_dither = nx_dpc_dither_5bit;
  91. rgb_mode = 1;
  92. } else if (nx_dpc_format_rgb565 == out_format ||
  93. nx_dpc_format_mrgb565 == out_format) {
  94. r_dither = nx_dpc_dither_5bit;
  95. b_dither = nx_dpc_dither_5bit;
  96. g_dither = nx_dpc_dither_6bit, rgb_mode = 1;
  97. } else if ((nx_dpc_format_rgb666 == out_format) ||
  98. (nx_dpc_format_mrgb666 == out_format)) {
  99. r_dither = nx_dpc_dither_6bit;
  100. g_dither = nx_dpc_dither_6bit;
  101. b_dither = nx_dpc_dither_6bit;
  102. rgb_mode = 1;
  103. } else {
  104. r_dither = nx_dpc_dither_bypass;
  105. g_dither = nx_dpc_dither_bypass;
  106. b_dither = nx_dpc_dither_bypass;
  107. rgb_mode = 1;
  108. }
  109. /* CLKGEN0/1 */
  110. nx_dpc_set_clock_source(module, 0, ctrl->clk_src_lv0 == 3 ?
  111. 6 : ctrl->clk_src_lv0);
  112. nx_dpc_set_clock_divisor(module, 0, ctrl->clk_div_lv0);
  113. nx_dpc_set_clock_source(module, 1, ctrl->clk_src_lv1);
  114. nx_dpc_set_clock_divisor(module, 1, ctrl->clk_div_lv1);
  115. nx_dpc_set_clock_out_delay(module, 0, ctrl->clk_delay_lv0);
  116. nx_dpc_set_clock_out_delay(module, 1, ctrl->clk_delay_lv1);
  117. /* LCD out */
  118. nx_dpc_set_mode(module, out_format, interlace, invert_field,
  119. rgb_mode, swap_rb, yc_order, emb_sync, emb_sync,
  120. vck_select, vclk_invert, 0);
  121. nx_dpc_set_hsync(module, sync->h_active_len, sync->h_sync_width,
  122. sync->h_front_porch, sync->h_back_porch,
  123. sync->h_sync_invert);
  124. nx_dpc_set_vsync(module, sync->v_active_len, sync->v_sync_width,
  125. sync->v_front_porch, sync->v_back_porch,
  126. sync->v_sync_invert, sync->v_active_len,
  127. sync->v_sync_width, sync->v_front_porch,
  128. sync->v_back_porch);
  129. nx_dpc_set_vsync_offset(module, v_vso, v_veo, e_vso, e_veo);
  130. nx_dpc_set_delay(module, rgb_pvd, hsync_cp1, vsync_fram, de_cp2);
  131. nx_dpc_set_dither(module, r_dither, g_dither, b_dither);
  132. if (IS_ENABLED(CONFIG_MACH_S5P6818)) {
  133. /* Set TFT_CLKCTRL (offset : 1030h)
  134. * Field name : DPC0_CLKCTRL, DPC1_CLKCRL
  135. * Default value : clk_inv_lv0/1 = 0 : PADCLK_InvCLK
  136. * Invert case : clk_inv_lv0/1 = 1 : PADCLK_CLK
  137. */
  138. if (module == 0 && ctrl->clk_inv_lv0)
  139. nx_disp_top_set_padclock(padmux_primary_mlc,
  140. padclk_clk);
  141. if (module == 1 && ctrl->clk_inv_lv1)
  142. nx_disp_top_set_padclock(padmux_secondary_mlc,
  143. padclk_clk);
  144. }
  145. debug("%s: dp.%d x:%4d, hf:%3d, hb:%3d, hs:%3d, hi=%d\n",
  146. __func__, module, sync->h_active_len, sync->h_front_porch,
  147. sync->h_back_porch, sync->h_sync_width, sync->h_sync_invert);
  148. debug("%s: dp.%d y:%4d, vf:%3d, vb:%3d, vs:%3d, vi=%d\n",
  149. __func__, module, sync->v_active_len, sync->v_front_porch,
  150. sync->v_back_porch, sync->v_sync_width, sync->h_sync_invert);
  151. debug("%s: dp.%d ck.0:%d:%d:%d, ck.1:%d:%d:%d\n",
  152. __func__, module,
  153. ctrl->clk_src_lv0, ctrl->clk_div_lv0, ctrl->clk_inv_lv0,
  154. ctrl->clk_src_lv1, ctrl->clk_div_lv1, ctrl->clk_inv_lv1);
  155. debug("%s: dp.%d vs:%d, ve:%d, es:%d, ee:%d\n",
  156. __func__, module, v_vso, v_veo, e_vso, e_veo);
  157. debug("%s: dp.%d delay RGB:%d, hs:%d, vs:%d, de:%d, fmt:0x%x\n",
  158. __func__, module, rgb_pvd, hsync_cp1, vsync_fram, de_cp2,
  159. out_format);
  160. return 0;
  161. }
  162. void dp_control_enable(int module, int on)
  163. {
  164. debug("%s: dp.%d top %s\n", __func__, module, on ? "ON" : "OFF");
  165. nx_dpc_set_dpc_enable(module, on);
  166. nx_dpc_set_clock_divisor_enable(module, on);
  167. }
  168. void dp_plane_init(int module)
  169. {
  170. void *base = __io_address(nx_mlc_get_physical_address(module));
  171. nx_mlc_set_base_address(module, base);
  172. nx_mlc_set_clock_pclk_mode(module, nx_pclkmode_always);
  173. nx_mlc_set_clock_bclk_mode(module, nx_bclkmode_always);
  174. }
  175. int dp_plane_screen_setup(int module, struct dp_plane_top *top)
  176. {
  177. int width = top->screen_width;
  178. int height = top->screen_height;
  179. int interlace = top->interlace;
  180. int video_prior = top->video_prior;
  181. unsigned int bg_color = top->back_color;
  182. /* MLC TOP layer */
  183. nx_mlc_set_screen_size(module, width, height);
  184. nx_mlc_set_layer_priority(module, video_prior);
  185. nx_mlc_set_background(module, bg_color);
  186. nx_mlc_set_field_enable(module, interlace);
  187. nx_mlc_set_rgblayer_gama_table_power_mode(module, 0, 0, 0);
  188. nx_mlc_set_rgblayer_gama_table_sleep_mode(module, 1, 1, 1);
  189. nx_mlc_set_rgblayer_gamma_enable(module, 0);
  190. nx_mlc_set_dither_enable_when_using_gamma(module, 0);
  191. nx_mlc_set_gamma_priority(module, 0);
  192. nx_mlc_set_top_power_mode(module, 1);
  193. nx_mlc_set_top_sleep_mode(module, 0);
  194. debug("%s: dp.%d screen %dx%d, %s, priority:%d, bg:0x%x\n",
  195. __func__, module, width, height,
  196. interlace ? "Interlace" : "Progressive",
  197. video_prior, bg_color);
  198. return 0;
  199. }
  200. void dp_plane_screen_enable(int module, int on)
  201. {
  202. /* enable top screen */
  203. nx_mlc_set_mlc_enable(module, on);
  204. nx_mlc_set_top_dirty_flag(module);
  205. debug("%s: dp.%d top %s\n", __func__, module, on ? "ON" : "OFF");
  206. }
  207. int dp_plane_layer_setup(int module, struct dp_plane_info *plane)
  208. {
  209. int sx = plane->left;
  210. int sy = plane->top;
  211. int ex = sx + plane->width - 1;
  212. int ey = sy + plane->height - 1;
  213. int pixel_byte = plane->pixel_byte;
  214. int mem_lock_size = 16; /* fix mem lock size */
  215. int layer = plane->layer;
  216. unsigned int format = plane->format;
  217. if (!plane->enable)
  218. return -EINVAL;
  219. /* MLC layer */
  220. nx_mlc_set_lock_size(module, layer, mem_lock_size);
  221. nx_mlc_set_alpha_blending(module, layer, 0, 15);
  222. nx_mlc_set_transparency(module, layer, 0, 0);
  223. nx_mlc_set_color_inversion(module, layer, 0, 0);
  224. nx_mlc_set_rgblayer_invalid_position(module, layer, 0, 0, 0, 0, 0, 0);
  225. nx_mlc_set_rgblayer_invalid_position(module, layer, 1, 0, 0, 0, 0, 0);
  226. nx_mlc_set_format_rgb(module, layer, format);
  227. nx_mlc_set_position(module, layer, sx, sy, ex, ey);
  228. nx_mlc_set_rgblayer_stride(module, layer, pixel_byte,
  229. plane->width * pixel_byte);
  230. nx_mlc_set_rgblayer_address(module, layer, plane->fb_base);
  231. debug("%s: dp.%d.%d %d * %d, %dbpp, fmt:0x%x\n",
  232. __func__, module, layer, plane->width, plane->height,
  233. pixel_byte * 8, format);
  234. debug("%s: b:0x%x, l:%d, t:%d, r:%d, b:%d, hs:%d, vs:%d\n",
  235. __func__, plane->fb_base, sx, sy, ex, ey,
  236. plane->width * pixel_byte, pixel_byte);
  237. return 0;
  238. }
  239. int dp_plane_set_enable(int module, int layer, int on)
  240. {
  241. int hl, hc;
  242. int vl, vc;
  243. debug("%s: dp.%d.%d %s:%s\n",
  244. __func__, module, layer,
  245. layer == MLC_LAYER_VIDEO ? "Video" : "RGB",
  246. on ? "ON" : "OFF");
  247. if (layer != MLC_LAYER_VIDEO) {
  248. nx_mlc_set_layer_enable(module, layer, on);
  249. nx_mlc_set_dirty_flag(module, layer);
  250. return 0;
  251. }
  252. /* video layer */
  253. if (on) {
  254. nx_mlc_set_video_layer_line_buffer_power_mode(module, 1);
  255. nx_mlc_set_video_layer_line_buffer_sleep_mode(module, 0);
  256. nx_mlc_set_layer_enable(module, layer, 1);
  257. nx_mlc_set_dirty_flag(module, layer);
  258. } else {
  259. nx_mlc_set_layer_enable(module, layer, 0);
  260. nx_mlc_set_dirty_flag(module, layer);
  261. nx_mlc_get_video_layer_scale_filter(module,
  262. &hl, &hc, &vl, &vc);
  263. if (hl || hc || vl || vc)
  264. nx_mlc_set_video_layer_scale_filter(module, 0, 0, 0, 0);
  265. nx_mlc_set_video_layer_line_buffer_power_mode(module, 0);
  266. nx_mlc_set_video_layer_line_buffer_sleep_mode(module, 1);
  267. nx_mlc_set_dirty_flag(module, layer);
  268. }
  269. return 0;
  270. }
  271. void dp_plane_layer_enable(int module,
  272. struct dp_plane_info *plane, int on)
  273. {
  274. dp_plane_set_enable(module, plane->layer, on);
  275. }
  276. int dp_plane_set_address(int module, int layer, unsigned int address)
  277. {
  278. nx_mlc_set_rgblayer_address(module, layer, address);
  279. nx_mlc_set_dirty_flag(module, layer);
  280. return 0;
  281. }
  282. int dp_plane_wait_vsync(int module, int layer, int fps)
  283. {
  284. int cnt = 0;
  285. if (fps == 0)
  286. return (int)nx_mlc_get_dirty_flag(module, layer);
  287. while (fps > cnt++) {
  288. while (nx_mlc_get_dirty_flag(module, layer))
  289. ;
  290. nx_mlc_set_dirty_flag(module, layer);
  291. }
  292. return 0;
  293. }