mxsfb.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX23/i.MX28 LCDIF driver
  4. *
  5. * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <env.h>
  11. #include <log.h>
  12. #include <asm/cache.h>
  13. #include <dm/device_compat.h>
  14. #include <linux/delay.h>
  15. #include <linux/errno.h>
  16. #include <malloc.h>
  17. #include <video.h>
  18. #include <video_fb.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/imx-regs.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/global_data.h>
  23. #include <asm/mach-imx/dma.h>
  24. #include <asm/io.h>
  25. #include "videomodes.h"
  26. #define PS2KHZ(ps) (1000000000UL / (ps))
  27. #define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
  28. #define BITS_PP 18
  29. #define BYTES_PP 4
  30. struct mxs_dma_desc desc;
  31. /**
  32. * mxsfb_system_setup() - Fine-tune LCDIF configuration
  33. *
  34. * This function is used to adjust the LCDIF configuration. This is usually
  35. * needed when driving the controller in System-Mode to operate an 8080 or
  36. * 6800 connected SmartLCD.
  37. */
  38. __weak void mxsfb_system_setup(void)
  39. {
  40. }
  41. /*
  42. * ARIES M28EVK:
  43. * setenv videomode
  44. * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  45. * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  46. *
  47. * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  48. * setenv videomode
  49. * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  50. * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  51. */
  52. static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
  53. struct display_timing *timings, int bpp)
  54. {
  55. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  56. const enum display_flags flags = timings->flags;
  57. uint32_t word_len = 0, bus_width = 0;
  58. uint8_t valid_data = 0;
  59. uint32_t vdctrl0;
  60. #if CONFIG_IS_ENABLED(CLK)
  61. struct clk clk;
  62. int ret;
  63. ret = clk_get_by_name(dev, "pix", &clk);
  64. if (ret) {
  65. dev_err(dev, "Failed to get mxs pix clk: %d\n", ret);
  66. return;
  67. }
  68. ret = clk_set_rate(&clk, timings->pixelclock.typ);
  69. if (ret < 0) {
  70. dev_err(dev, "Failed to set mxs pix clk: %d\n", ret);
  71. return;
  72. }
  73. ret = clk_enable(&clk);
  74. if (ret < 0) {
  75. dev_err(dev, "Failed to enable mxs pix clk: %d\n", ret);
  76. return;
  77. }
  78. ret = clk_get_by_name(dev, "axi", &clk);
  79. if (!ret) {
  80. debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
  81. } else {
  82. ret = clk_enable(&clk);
  83. if (ret < 0) {
  84. dev_err(dev, "Failed to enable mxs axi clk: %d\n", ret);
  85. return;
  86. }
  87. }
  88. ret = clk_get_by_name(dev, "disp_axi", &clk);
  89. if (!ret) {
  90. debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__, ret);
  91. } else {
  92. ret = clk_enable(&clk);
  93. if (ret < 0) {
  94. dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n", ret);
  95. return;
  96. }
  97. }
  98. #else
  99. /* Kick in the LCDIF clock */
  100. mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
  101. #endif
  102. /* Restart the LCDIF block */
  103. mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  104. switch (bpp) {
  105. case 24:
  106. word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  107. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
  108. valid_data = 0x7;
  109. break;
  110. case 18:
  111. word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  112. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
  113. valid_data = 0x7;
  114. break;
  115. case 16:
  116. word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
  117. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
  118. valid_data = 0xf;
  119. break;
  120. case 8:
  121. word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
  122. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
  123. valid_data = 0xf;
  124. break;
  125. }
  126. writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
  127. LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
  128. &regs->hw_lcdif_ctrl);
  129. writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
  130. &regs->hw_lcdif_ctrl1);
  131. mxsfb_system_setup();
  132. writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
  133. timings->hactive.typ, &regs->hw_lcdif_transfer_count);
  134. vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
  135. LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
  136. LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
  137. timings->vsync_len.typ;
  138. if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
  139. vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
  140. if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
  141. vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
  142. if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
  143. vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
  144. if(flags & DISPLAY_FLAGS_DE_HIGH)
  145. vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
  146. writel(vdctrl0, &regs->hw_lcdif_vdctrl0);
  147. writel(timings->vback_porch.typ + timings->vfront_porch.typ +
  148. timings->vsync_len.typ + timings->vactive.typ,
  149. &regs->hw_lcdif_vdctrl1);
  150. writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
  151. (timings->hback_porch.typ + timings->hfront_porch.typ +
  152. timings->hsync_len.typ + timings->hactive.typ),
  153. &regs->hw_lcdif_vdctrl2);
  154. writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
  155. LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
  156. (timings->vback_porch.typ + timings->vsync_len.typ),
  157. &regs->hw_lcdif_vdctrl3);
  158. writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
  159. &regs->hw_lcdif_vdctrl4);
  160. writel(fb_addr, &regs->hw_lcdif_cur_buf);
  161. writel(fb_addr, &regs->hw_lcdif_next_buf);
  162. /* Flush FIFO first */
  163. writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
  164. #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
  165. /* Sync signals ON */
  166. setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
  167. #endif
  168. /* FIFO cleared */
  169. writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
  170. /* RUN! */
  171. writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
  172. }
  173. static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
  174. int bpp, u32 fb)
  175. {
  176. /* Start framebuffer */
  177. mxs_lcd_init(dev, fb, timings, bpp);
  178. #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
  179. /*
  180. * If the LCD runs in system mode, the LCD refresh has to be triggered
  181. * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
  182. * having to set this bit manually after every single change in the
  183. * framebuffer memory, we set up specially crafted circular DMA, which
  184. * sets the RUN bit, then waits until it gets cleared and repeats this
  185. * infinitelly. This way, we get smooth continuous updates of the LCD.
  186. */
  187. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  188. memset(&desc, 0, sizeof(struct mxs_dma_desc));
  189. desc.address = (dma_addr_t)&desc;
  190. desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  191. MXS_DMA_DESC_WAIT4END |
  192. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  193. desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
  194. desc.cmd.next = (uint32_t)&desc.cmd;
  195. /* Execute the DMA chain. */
  196. mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
  197. #endif
  198. return 0;
  199. }
  200. static int mxs_remove_common(u32 fb)
  201. {
  202. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  203. int timeout = 1000000;
  204. if (!fb)
  205. return -EINVAL;
  206. writel(fb, &regs->hw_lcdif_cur_buf_reg);
  207. writel(fb, &regs->hw_lcdif_next_buf_reg);
  208. writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
  209. while (--timeout) {
  210. if (readl(&regs->hw_lcdif_ctrl1_reg) &
  211. LCDIF_CTRL1_VSYNC_EDGE_IRQ)
  212. break;
  213. udelay(1);
  214. }
  215. mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
  216. return 0;
  217. }
  218. #ifndef CONFIG_DM_VIDEO
  219. static GraphicDevice panel;
  220. void lcdif_power_down(void)
  221. {
  222. mxs_remove_common(panel.frameAdrs);
  223. }
  224. void *video_hw_init(void)
  225. {
  226. int bpp = -1;
  227. int ret = 0;
  228. char *penv;
  229. void *fb = NULL;
  230. struct ctfb_res_modes mode;
  231. struct display_timing timings;
  232. puts("Video: ");
  233. /* Suck display configuration from "videomode" variable */
  234. penv = env_get("videomode");
  235. if (!penv) {
  236. puts("MXSFB: 'videomode' variable not set!\n");
  237. return NULL;
  238. }
  239. bpp = video_get_params(&mode, penv);
  240. /* fill in Graphic device struct */
  241. sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
  242. panel.winSizeX = mode.xres;
  243. panel.winSizeY = mode.yres;
  244. panel.plnSizeX = mode.xres;
  245. panel.plnSizeY = mode.yres;
  246. switch (bpp) {
  247. case 24:
  248. case 18:
  249. panel.gdfBytesPP = 4;
  250. panel.gdfIndex = GDF_32BIT_X888RGB;
  251. break;
  252. case 16:
  253. panel.gdfBytesPP = 2;
  254. panel.gdfIndex = GDF_16BIT_565RGB;
  255. break;
  256. case 8:
  257. panel.gdfBytesPP = 1;
  258. panel.gdfIndex = GDF__8BIT_INDEX;
  259. break;
  260. default:
  261. printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
  262. return NULL;
  263. }
  264. panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
  265. /* Allocate framebuffer */
  266. fb = memalign(ARCH_DMA_MINALIGN,
  267. roundup(panel.memSize, ARCH_DMA_MINALIGN));
  268. if (!fb) {
  269. printf("MXSFB: Error allocating framebuffer!\n");
  270. return NULL;
  271. }
  272. /* Wipe framebuffer */
  273. memset(fb, 0, panel.memSize);
  274. panel.frameAdrs = (u32)fb;
  275. printf("%s\n", panel.modeIdent);
  276. video_ctfb_mode_to_display_timing(&mode, &timings);
  277. ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
  278. if (ret)
  279. goto dealloc_fb;
  280. return (void *)&panel;
  281. dealloc_fb:
  282. free(fb);
  283. return NULL;
  284. }
  285. #else /* ifndef CONFIG_DM_VIDEO */
  286. static int mxs_of_get_timings(struct udevice *dev,
  287. struct display_timing *timings,
  288. u32 *bpp)
  289. {
  290. int ret = 0;
  291. u32 display_phandle;
  292. ofnode display_node;
  293. ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
  294. if (ret) {
  295. dev_err(dev, "required display property isn't provided\n");
  296. return -EINVAL;
  297. }
  298. display_node = ofnode_get_by_phandle(display_phandle);
  299. if (!ofnode_valid(display_node)) {
  300. dev_err(dev, "failed to find display subnode\n");
  301. return -EINVAL;
  302. }
  303. ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
  304. if (ret) {
  305. dev_err(dev,
  306. "required bits-per-pixel property isn't provided\n");
  307. return -EINVAL;
  308. }
  309. ret = ofnode_decode_display_timing(display_node, 0, timings);
  310. if (ret) {
  311. dev_err(dev, "failed to get any display timings\n");
  312. return -EINVAL;
  313. }
  314. return ret;
  315. }
  316. static int mxs_video_probe(struct udevice *dev)
  317. {
  318. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  319. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  320. struct display_timing timings;
  321. u32 bpp = 0;
  322. u32 fb_start, fb_end;
  323. int ret;
  324. debug("%s() plat: base 0x%lx, size 0x%x\n",
  325. __func__, plat->base, plat->size);
  326. ret = mxs_of_get_timings(dev, &timings, &bpp);
  327. if (ret)
  328. return ret;
  329. ret = mxs_probe_common(dev, &timings, bpp, plat->base);
  330. if (ret)
  331. return ret;
  332. switch (bpp) {
  333. case 32:
  334. case 24:
  335. case 18:
  336. uc_priv->bpix = VIDEO_BPP32;
  337. break;
  338. case 16:
  339. uc_priv->bpix = VIDEO_BPP16;
  340. break;
  341. case 8:
  342. uc_priv->bpix = VIDEO_BPP8;
  343. break;
  344. default:
  345. dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
  346. return -EINVAL;
  347. }
  348. uc_priv->xsize = timings.hactive.typ;
  349. uc_priv->ysize = timings.vactive.typ;
  350. /* Enable dcache for the frame buffer */
  351. fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
  352. fb_end = plat->base + plat->size;
  353. fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
  354. mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
  355. DCACHE_WRITEBACK);
  356. video_set_flush_dcache(dev, true);
  357. gd->fb_base = plat->base;
  358. return ret;
  359. }
  360. static int mxs_video_bind(struct udevice *dev)
  361. {
  362. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  363. struct display_timing timings;
  364. u32 bpp = 0;
  365. u32 bytes_pp = 0;
  366. int ret;
  367. ret = mxs_of_get_timings(dev, &timings, &bpp);
  368. if (ret)
  369. return ret;
  370. switch (bpp) {
  371. case 32:
  372. case 24:
  373. case 18:
  374. bytes_pp = 4;
  375. break;
  376. case 16:
  377. bytes_pp = 2;
  378. break;
  379. case 8:
  380. bytes_pp = 1;
  381. break;
  382. default:
  383. dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
  384. return -EINVAL;
  385. }
  386. plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
  387. return 0;
  388. }
  389. static int mxs_video_remove(struct udevice *dev)
  390. {
  391. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  392. mxs_remove_common(plat->base);
  393. return 0;
  394. }
  395. static const struct udevice_id mxs_video_ids[] = {
  396. { .compatible = "fsl,imx23-lcdif" },
  397. { .compatible = "fsl,imx28-lcdif" },
  398. { .compatible = "fsl,imx7ulp-lcdif" },
  399. { .compatible = "fsl,imxrt-lcdif" },
  400. { /* sentinel */ }
  401. };
  402. U_BOOT_DRIVER(mxs_video) = {
  403. .name = "mxs_video",
  404. .id = UCLASS_VIDEO,
  405. .of_match = mxs_video_ids,
  406. .bind = mxs_video_bind,
  407. .probe = mxs_video_probe,
  408. .remove = mxs_video_remove,
  409. .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
  410. };
  411. #endif /* ifndef CONFIG_DM_VIDEO */