meson_registers.h 61 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
  4. */
  5. #ifndef __MESON_REGISTERS_H
  6. #define __MESON_REGISTERS_H
  7. /* Shift all registers by 2 */
  8. #include <linux/bitops.h>
  9. #define _REG(reg) ((reg) << 2)
  10. #define writel_bits(mask, val, addr) \
  11. writel((readl(addr) & ~(mask)) | (val), addr)
  12. /* vpp2 */
  13. #define VPP2_DUMMY_DATA 0x1900
  14. #define VPP2_LINE_IN_LENGTH 0x1901
  15. #define VPP2_PIC_IN_HEIGHT 0x1902
  16. #define VPP2_SCALE_COEF_IDX 0x1903
  17. #define VPP2_SCALE_COEF 0x1904
  18. #define VPP2_VSC_REGION12_STARTP 0x1905
  19. #define VPP2_VSC_REGION34_STARTP 0x1906
  20. #define VPP2_VSC_REGION4_ENDP 0x1907
  21. #define VPP2_VSC_START_PHASE_STEP 0x1908
  22. #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
  23. #define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a
  24. #define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b
  25. #define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c
  26. #define VPP2_VSC_PHASE_CTRL 0x190d
  27. #define VPP2_VSC_INI_PHASE 0x190e
  28. #define VPP2_HSC_REGION12_STARTP 0x1910
  29. #define VPP2_HSC_REGION34_STARTP 0x1911
  30. #define VPP2_HSC_REGION4_ENDP 0x1912
  31. #define VPP2_HSC_START_PHASE_STEP 0x1913
  32. #define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914
  33. #define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915
  34. #define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916
  35. #define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917
  36. #define VPP2_HSC_PHASE_CTRL 0x1918
  37. #define VPP2_SC_MISC 0x1919
  38. #define VPP2_PREBLEND_VD1_H_START_END 0x191a
  39. #define VPP2_PREBLEND_VD1_V_START_END 0x191b
  40. #define VPP2_POSTBLEND_VD1_H_START_END 0x191c
  41. #define VPP2_POSTBLEND_VD1_V_START_END 0x191d
  42. #define VPP2_PREBLEND_H_SIZE 0x1920
  43. #define VPP2_POSTBLEND_H_SIZE 0x1921
  44. #define VPP2_HOLD_LINES 0x1922
  45. #define VPP2_BLEND_ONECOLOR_CTRL 0x1923
  46. #define VPP2_PREBLEND_CURRENT_XY 0x1924
  47. #define VPP2_POSTBLEND_CURRENT_XY 0x1925
  48. #define VPP2_MISC 0x1926
  49. #define VPP2_OFIFO_SIZE 0x1927
  50. #define VPP2_FIFO_STATUS 0x1928
  51. #define VPP2_SMOKE_CTRL 0x1929
  52. #define VPP2_SMOKE1_VAL 0x192a
  53. #define VPP2_SMOKE2_VAL 0x192b
  54. #define VPP2_SMOKE1_H_START_END 0x192d
  55. #define VPP2_SMOKE1_V_START_END 0x192e
  56. #define VPP2_SMOKE2_H_START_END 0x192f
  57. #define VPP2_SMOKE2_V_START_END 0x1930
  58. #define VPP2_SCO_FIFO_CTRL 0x1933
  59. #define VPP2_HSC_PHASE_CTRL1 0x1934
  60. #define VPP2_HSC_INI_PAT_CTRL 0x1935
  61. #define VPP2_VADJ_CTRL 0x1940
  62. #define VPP2_VADJ1_Y 0x1941
  63. #define VPP2_VADJ1_MA_MB 0x1942
  64. #define VPP2_VADJ1_MC_MD 0x1943
  65. #define VPP2_VADJ2_Y 0x1944
  66. #define VPP2_VADJ2_MA_MB 0x1945
  67. #define VPP2_VADJ2_MC_MD 0x1946
  68. #define VPP2_MATRIX_PROBE_COLOR 0x195c
  69. #define VPP2_MATRIX_HL_COLOR 0x195d
  70. #define VPP2_MATRIX_PROBE_POS 0x195e
  71. #define VPP2_MATRIX_CTRL 0x195f
  72. #define VPP2_MATRIX_COEF00_01 0x1960
  73. #define VPP2_MATRIX_COEF02_10 0x1961
  74. #define VPP2_MATRIX_COEF11_12 0x1962
  75. #define VPP2_MATRIX_COEF20_21 0x1963
  76. #define VPP2_MATRIX_COEF22 0x1964
  77. #define VPP2_MATRIX_OFFSET0_1 0x1965
  78. #define VPP2_MATRIX_OFFSET2 0x1966
  79. #define VPP2_MATRIX_PRE_OFFSET0_1 0x1967
  80. #define VPP2_MATRIX_PRE_OFFSET2 0x1968
  81. #define VPP2_DUMMY_DATA1 0x1969
  82. #define VPP2_GAINOFF_CTRL0 0x196a
  83. #define VPP2_GAINOFF_CTRL1 0x196b
  84. #define VPP2_GAINOFF_CTRL2 0x196c
  85. #define VPP2_GAINOFF_CTRL3 0x196d
  86. #define VPP2_GAINOFF_CTRL4 0x196e
  87. #define VPP2_CHROMA_ADDR_PORT 0x1970
  88. #define VPP2_CHROMA_DATA_PORT 0x1971
  89. #define VPP2_GCLK_CTRL0 0x1972
  90. #define VPP2_GCLK_CTRL1 0x1973
  91. #define VPP2_SC_GCLK_CTRL 0x1974
  92. #define VPP2_MISC1 0x1976
  93. #define VPP2_DNLP_CTRL_00 0x1981
  94. #define VPP2_DNLP_CTRL_01 0x1982
  95. #define VPP2_DNLP_CTRL_02 0x1983
  96. #define VPP2_DNLP_CTRL_03 0x1984
  97. #define VPP2_DNLP_CTRL_04 0x1985
  98. #define VPP2_DNLP_CTRL_05 0x1986
  99. #define VPP2_DNLP_CTRL_06 0x1987
  100. #define VPP2_DNLP_CTRL_07 0x1988
  101. #define VPP2_DNLP_CTRL_08 0x1989
  102. #define VPP2_DNLP_CTRL_09 0x198a
  103. #define VPP2_DNLP_CTRL_10 0x198b
  104. #define VPP2_DNLP_CTRL_11 0x198c
  105. #define VPP2_DNLP_CTRL_12 0x198d
  106. #define VPP2_DNLP_CTRL_13 0x198e
  107. #define VPP2_DNLP_CTRL_14 0x198f
  108. #define VPP2_DNLP_CTRL_15 0x1990
  109. #define VPP2_VE_ENABLE_CTRL 0x19a1
  110. #define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2
  111. #define VPP2_VE_DEMO_CENTER_BAR 0x19a3
  112. #define VPP2_VE_H_V_SIZE 0x19a4
  113. #define VPP2_VDO_MEAS_CTRL 0x19a8
  114. #define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9
  115. #define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa
  116. #define VPP2_OSD_VSC_PHASE_STEP 0x19c0
  117. #define VPP2_OSD_VSC_INI_PHASE 0x19c1
  118. #define VPP2_OSD_VSC_CTRL0 0x19c2
  119. #define VPP2_OSD_HSC_PHASE_STEP 0x19c3
  120. #define VPP2_OSD_HSC_INI_PHASE 0x19c4
  121. #define VPP2_OSD_HSC_CTRL0 0x19c5
  122. #define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6
  123. #define VPP2_OSD_SC_DUMMY_DATA 0x19c7
  124. #define VPP2_OSD_SC_CTRL0 0x19c8
  125. #define VPP2_OSD_SCI_WH_M1 0x19c9
  126. #define VPP2_OSD_SCO_H_START_END 0x19ca
  127. #define VPP2_OSD_SCO_V_START_END 0x19cb
  128. #define VPP2_OSD_SCALE_COEF_IDX 0x19cc
  129. #define VPP2_OSD_SCALE_COEF 0x19cd
  130. #define VPP2_INT_LINE_NUM 0x19ce
  131. /* viu */
  132. #define VIU_ADDR_START 0x1a00
  133. #define VIU_ADDR_END 0x1aff
  134. #define VIU_SW_RESET 0x1a01
  135. #define VIU_SW_RESET_OSD1 BIT(0)
  136. #define VIU_MISC_CTRL0 0x1a06
  137. #define VIU_CTRL0_VD1_AFBC_MASK 0x170000
  138. #define VIU_MISC_CTRL1 0x1a07
  139. #define D2D3_INTF_LENGTH 0x1a08
  140. #define D2D3_INTF_CTRL0 0x1a09
  141. #define VIU_OSD1_CTRL_STAT 0x1a10
  142. #define VIU_OSD1_OSD_BLK_ENABLE BIT(0)
  143. #define VIU_OSD1_POSTBLD_SRC_VD1 (1 << 8)
  144. #define VIU_OSD1_POSTBLD_SRC_VD2 (2 << 8)
  145. #define VIU_OSD1_POSTBLD_SRC_OSD1 (3 << 8)
  146. #define VIU_OSD1_POSTBLD_SRC_OSD2 (4 << 8)
  147. #define VIU_OSD1_OSD_ENABLE BIT(21)
  148. #define VIU_OSD1_CTRL_STAT2 0x1a2d
  149. #define VIU_OSD1_COLOR_ADDR 0x1a11
  150. #define VIU_OSD1_COLOR 0x1a12
  151. #define VIU_OSD1_TCOLOR_AG0 0x1a17
  152. #define VIU_OSD1_TCOLOR_AG1 0x1a18
  153. #define VIU_OSD1_TCOLOR_AG2 0x1a19
  154. #define VIU_OSD1_TCOLOR_AG3 0x1a1a
  155. #define VIU_OSD1_BLK0_CFG_W0 0x1a1b
  156. #define VIU_OSD1_BLK1_CFG_W0 0x1a1f
  157. #define VIU_OSD1_BLK2_CFG_W0 0x1a23
  158. #define VIU_OSD1_BLK3_CFG_W0 0x1a27
  159. #define VIU_OSD1_BLK0_CFG_W1 0x1a1c
  160. #define VIU_OSD1_BLK1_CFG_W1 0x1a20
  161. #define VIU_OSD1_BLK2_CFG_W1 0x1a24
  162. #define VIU_OSD1_BLK3_CFG_W1 0x1a28
  163. #define VIU_OSD1_BLK0_CFG_W2 0x1a1d
  164. #define VIU_OSD1_BLK1_CFG_W2 0x1a21
  165. #define VIU_OSD1_BLK2_CFG_W2 0x1a25
  166. #define VIU_OSD1_BLK3_CFG_W2 0x1a29
  167. #define VIU_OSD1_BLK0_CFG_W3 0x1a1e
  168. #define VIU_OSD1_BLK1_CFG_W3 0x1a22
  169. #define VIU_OSD1_BLK2_CFG_W3 0x1a26
  170. #define VIU_OSD1_BLK3_CFG_W3 0x1a2a
  171. #define VIU_OSD1_BLK0_CFG_W4 0x1a13
  172. #define VIU_OSD1_BLK1_CFG_W4 0x1a14
  173. #define VIU_OSD1_BLK2_CFG_W4 0x1a15
  174. #define VIU_OSD1_BLK3_CFG_W4 0x1a16
  175. #define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b
  176. #define VIU_OSD1_TEST_RDDATA 0x1a2c
  177. #define VIU_OSD1_PROT_CTRL 0x1a2e
  178. #define VIU_OSD2_CTRL_STAT 0x1a30
  179. #define VIU_OSD2_CTRL_STAT2 0x1a4d
  180. #define VIU_OSD2_COLOR_ADDR 0x1a31
  181. #define VIU_OSD2_COLOR 0x1a32
  182. #define VIU_OSD2_HL1_H_START_END 0x1a33
  183. #define VIU_OSD2_HL1_V_START_END 0x1a34
  184. #define VIU_OSD2_HL2_H_START_END 0x1a35
  185. #define VIU_OSD2_HL2_V_START_END 0x1a36
  186. #define VIU_OSD2_TCOLOR_AG0 0x1a37
  187. #define VIU_OSD2_TCOLOR_AG1 0x1a38
  188. #define VIU_OSD2_TCOLOR_AG2 0x1a39
  189. #define VIU_OSD2_TCOLOR_AG3 0x1a3a
  190. #define VIU_OSD2_BLK0_CFG_W0 0x1a3b
  191. #define VIU_OSD2_BLK1_CFG_W0 0x1a3f
  192. #define VIU_OSD2_BLK2_CFG_W0 0x1a43
  193. #define VIU_OSD2_BLK3_CFG_W0 0x1a47
  194. #define VIU_OSD2_BLK0_CFG_W1 0x1a3c
  195. #define VIU_OSD2_BLK1_CFG_W1 0x1a40
  196. #define VIU_OSD2_BLK2_CFG_W1 0x1a44
  197. #define VIU_OSD2_BLK3_CFG_W1 0x1a48
  198. #define VIU_OSD2_BLK0_CFG_W2 0x1a3d
  199. #define VIU_OSD2_BLK1_CFG_W2 0x1a41
  200. #define VIU_OSD2_BLK2_CFG_W2 0x1a45
  201. #define VIU_OSD2_BLK3_CFG_W2 0x1a49
  202. #define VIU_OSD2_BLK0_CFG_W3 0x1a3e
  203. #define VIU_OSD2_BLK1_CFG_W3 0x1a42
  204. #define VIU_OSD2_BLK2_CFG_W3 0x1a46
  205. #define VIU_OSD2_BLK3_CFG_W3 0x1a4a
  206. #define VIU_OSD2_BLK0_CFG_W4 0x1a64
  207. #define VIU_OSD2_BLK1_CFG_W4 0x1a65
  208. #define VIU_OSD2_BLK2_CFG_W4 0x1a66
  209. #define VIU_OSD2_BLK3_CFG_W4 0x1a67
  210. #define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b
  211. #define VIU_OSD2_TEST_RDDATA 0x1a4c
  212. #define VIU_OSD2_PROT_CTRL 0x1a4e
  213. #define VIU_OSD2_MALI_UNPACK_CTRL 0x1abd
  214. #define VIU_OSD2_DIMM_CTRL 0x1acf
  215. #define VIU_OSD3_CTRL_STAT 0x3d80
  216. #define VIU_OSD3_CTRL_STAT2 0x3d81
  217. #define VIU_OSD3_COLOR_ADDR 0x3d82
  218. #define VIU_OSD3_COLOR 0x3d83
  219. #define VIU_OSD3_TCOLOR_AG0 0x3d84
  220. #define VIU_OSD3_TCOLOR_AG1 0x3d85
  221. #define VIU_OSD3_TCOLOR_AG2 0x3d86
  222. #define VIU_OSD3_TCOLOR_AG3 0x3d87
  223. #define VIU_OSD3_BLK0_CFG_W0 0x3d88
  224. #define VIU_OSD3_BLK0_CFG_W1 0x3d8c
  225. #define VIU_OSD3_BLK0_CFG_W2 0x3d90
  226. #define VIU_OSD3_BLK0_CFG_W3 0x3d94
  227. #define VIU_OSD3_BLK0_CFG_W4 0x3d98
  228. #define VIU_OSD3_BLK1_CFG_W4 0x3d99
  229. #define VIU_OSD3_BLK2_CFG_W4 0x3d9a
  230. #define VIU_OSD3_FIFO_CTRL_STAT 0x3d9c
  231. #define VIU_OSD3_TEST_RDDATA 0x3d9d
  232. #define VIU_OSD3_PROT_CTRL 0x3d9e
  233. #define VIU_OSD3_MALI_UNPACK_CTRL 0x3d9f
  234. #define VIU_OSD3_DIMM_CTRL 0x3da0
  235. #define VIU_OSD_DDR_PRIORITY_URGENT BIT(0)
  236. #define VIU_OSD_HOLD_FIFO_LINES(lines) ((lines & 0x1f) << 5)
  237. #define VIU_OSD_FIFO_DEPTH_VAL(val) ((val & 0x7f) << 12)
  238. #define VIU_OSD_WORDS_PER_BURST(words) (((words & 0x4) >> 1) << 22)
  239. #define VIU_OSD_FIFO_LIMITS(size) ((size & 0xf) << 24)
  240. #define VD1_IF0_GEN_REG 0x1a50
  241. #define VD1_IF0_CANVAS0 0x1a51
  242. #define VD1_IF0_CANVAS1 0x1a52
  243. #define VD1_IF0_LUMA_X0 0x1a53
  244. #define VD1_IF0_LUMA_Y0 0x1a54
  245. #define VD1_IF0_CHROMA_X0 0x1a55
  246. #define VD1_IF0_CHROMA_Y0 0x1a56
  247. #define VD1_IF0_LUMA_X1 0x1a57
  248. #define VD1_IF0_LUMA_Y1 0x1a58
  249. #define VD1_IF0_CHROMA_X1 0x1a59
  250. #define VD1_IF0_CHROMA_Y1 0x1a5a
  251. #define VD1_IF0_RPT_LOOP 0x1a5b
  252. #define VD1_IF0_LUMA0_RPT_PAT 0x1a5c
  253. #define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d
  254. #define VD1_IF0_LUMA1_RPT_PAT 0x1a5e
  255. #define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f
  256. #define VD1_IF0_LUMA_PSEL 0x1a60
  257. #define VD1_IF0_CHROMA_PSEL 0x1a61
  258. #define VD1_IF0_DUMMY_PIXEL 0x1a62
  259. #define VD1_IF0_LUMA_FIFO_SIZE 0x1a63
  260. #define VD1_IF0_RANGE_MAP_Y 0x1a6a
  261. #define VD1_IF0_RANGE_MAP_CB 0x1a6b
  262. #define VD1_IF0_RANGE_MAP_CR 0x1a6c
  263. #define VD1_IF0_GEN_REG2 0x1a6d
  264. #define VD1_IF0_PROT_CNTL 0x1a6e
  265. #define VIU_VD1_FMT_CTRL 0x1a68
  266. #define VIU_VD1_FMT_W 0x1a69
  267. #define VD2_IF0_GEN_REG 0x1a70
  268. #define VD2_IF0_CANVAS0 0x1a71
  269. #define VD2_IF0_CANVAS1 0x1a72
  270. #define VD2_IF0_LUMA_X0 0x1a73
  271. #define VD2_IF0_LUMA_Y0 0x1a74
  272. #define VD2_IF0_CHROMA_X0 0x1a75
  273. #define VD2_IF0_CHROMA_Y0 0x1a76
  274. #define VD2_IF0_LUMA_X1 0x1a77
  275. #define VD2_IF0_LUMA_Y1 0x1a78
  276. #define VD2_IF0_CHROMA_X1 0x1a79
  277. #define VD2_IF0_CHROMA_Y1 0x1a7a
  278. #define VD2_IF0_RPT_LOOP 0x1a7b
  279. #define VD2_IF0_LUMA0_RPT_PAT 0x1a7c
  280. #define VD2_IF0_CHROMA0_RPT_PAT 0x1a7d
  281. #define VD2_IF0_LUMA1_RPT_PAT 0x1a7e
  282. #define VD2_IF0_CHROMA1_RPT_PAT 0x1a7f
  283. #define VD2_IF0_LUMA_PSEL 0x1a80
  284. #define VD2_IF0_CHROMA_PSEL 0x1a81
  285. #define VD2_IF0_DUMMY_PIXEL 0x1a82
  286. #define VD2_IF0_LUMA_FIFO_SIZE 0x1a83
  287. #define VD2_IF0_RANGE_MAP_Y 0x1a8a
  288. #define VD2_IF0_RANGE_MAP_CB 0x1a8b
  289. #define VD2_IF0_RANGE_MAP_CR 0x1a8c
  290. #define VD2_IF0_GEN_REG2 0x1a8d
  291. #define VD2_IF0_PROT_CNTL 0x1a8e
  292. #define VIU_VD2_FMT_CTRL 0x1a88
  293. #define VIU_VD2_FMT_W 0x1a89
  294. /* VIU Matrix Registers */
  295. #define VIU_OSD1_MATRIX_CTRL 0x1a90
  296. #define VIU_OSD1_MATRIX_COEF00_01 0x1a91
  297. #define VIU_OSD1_MATRIX_COEF02_10 0x1a92
  298. #define VIU_OSD1_MATRIX_COEF11_12 0x1a93
  299. #define VIU_OSD1_MATRIX_COEF20_21 0x1a94
  300. #define VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95
  301. #define VIU_OSD1_MATRIX_OFFSET0_1 0x1a96
  302. #define VIU_OSD1_MATRIX_OFFSET2 0x1a97
  303. #define VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98
  304. #define VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99
  305. #define VIU_OSD1_MATRIX_COEF22_30 0x1a9d
  306. #define VIU_OSD1_MATRIX_COEF31_32 0x1a9e
  307. #define VIU_OSD1_MATRIX_COEF40_41 0x1a9f
  308. #define VD1_IF0_GEN_REG3 0x1aa7
  309. #define VIU_OSD_BLENDO_H_START_END 0x1aa9
  310. #define VIU_OSD_BLENDO_V_START_END 0x1aaa
  311. #define VIU_OSD_BLEND_GEN_CTRL0 0x1aab
  312. #define VIU_OSD_BLEND_GEN_CTRL1 0x1aac
  313. #define VIU_OSD_BLEND_DUMMY_DATA 0x1aad
  314. #define VIU_OSD_BLEND_CURRENT_XY 0x1aae
  315. #define VIU_OSD2_MATRIX_CTRL 0x1ab0
  316. #define VIU_OSD2_MATRIX_COEF00_01 0x1ab1
  317. #define VIU_OSD2_MATRIX_COEF02_10 0x1ab2
  318. #define VIU_OSD2_MATRIX_COEF11_12 0x1ab3
  319. #define VIU_OSD2_MATRIX_COEF20_21 0x1ab4
  320. #define VIU_OSD2_MATRIX_COEF22 0x1ab5
  321. #define VIU_OSD2_MATRIX_OFFSET0_1 0x1ab6
  322. #define VIU_OSD2_MATRIX_OFFSET2 0x1ab7
  323. #define VIU_OSD2_MATRIX_PRE_OFFSET0_1 0x1ab8
  324. #define VIU_OSD2_MATRIX_PRE_OFFSET2 0x1ab9
  325. #define VIU_OSD2_MATRIX_PROBE_COLOR 0x1aba
  326. #define VIU_OSD2_MATRIX_HL_COLOR 0x1abb
  327. #define VIU_OSD2_MATRIX_PROBE_POS 0x1abc
  328. #define VIU_OSD1_EOTF_CTL 0x1ad4
  329. #define VIU_OSD1_EOTF_COEF00_01 0x1ad5
  330. #define VIU_OSD1_EOTF_COEF02_10 0x1ad6
  331. #define VIU_OSD1_EOTF_COEF11_12 0x1ad7
  332. #define VIU_OSD1_EOTF_COEF20_21 0x1ad8
  333. #define VIU_OSD1_EOTF_COEF22_RS 0x1ad9
  334. #define VIU_OSD1_EOTF_LUT_ADDR_PORT 0x1ada
  335. #define VIU_OSD1_EOTF_LUT_DATA_PORT 0x1adb
  336. #define VIU_OSD1_OETF_CTL 0x1adc
  337. #define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add
  338. #define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade
  339. #define AFBC_ENABLE 0x1ae0
  340. /* vpp */
  341. #define VPP_DUMMY_DATA 0x1d00
  342. #define VPP_LINE_IN_LENGTH 0x1d01
  343. #define VPP_PIC_IN_HEIGHT 0x1d02
  344. #define VPP_SCALE_COEF_IDX 0x1d03
  345. #define VPP_SCALE_HORIZONTAL_COEF BIT(8)
  346. #define VPP_SCALE_COEF 0x1d04
  347. #define VPP_VSC_REGION12_STARTP 0x1d05
  348. #define VPP_VSC_REGION34_STARTP 0x1d06
  349. #define VPP_VSC_REGION4_ENDP 0x1d07
  350. #define VPP_VSC_START_PHASE_STEP 0x1d08
  351. #define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09
  352. #define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a
  353. #define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b
  354. #define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c
  355. #define VPP_VSC_PHASE_CTRL 0x1d0d
  356. #define VPP_VSC_INI_PHASE 0x1d0e
  357. #define VPP_HSC_REGION12_STARTP 0x1d10
  358. #define VPP_HSC_REGION34_STARTP 0x1d11
  359. #define VPP_HSC_REGION4_ENDP 0x1d12
  360. #define VPP_HSC_START_PHASE_STEP 0x1d13
  361. #define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14
  362. #define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15
  363. #define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16
  364. #define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17
  365. #define VPP_HSC_PHASE_CTRL 0x1d18
  366. #define VPP_SC_MISC 0x1d19
  367. #define VPP_SC_VD_EN_ENABLE BIT(15)
  368. #define VPP_SC_TOP_EN_ENABLE BIT(16)
  369. #define VPP_SC_HSC_EN_ENABLE BIT(17)
  370. #define VPP_SC_VSC_EN_ENABLE BIT(18)
  371. #define VPP_VSC_BANK_LENGTH(length) (length & 0x7)
  372. #define VPP_HSC_BANK_LENGTH(length) ((length & 0x7) << 8)
  373. #define VPP_PREBLEND_VD1_H_START_END 0x1d1a
  374. #define VPP_PREBLEND_VD1_V_START_END 0x1d1b
  375. #define VPP_POSTBLEND_VD1_H_START_END 0x1d1c
  376. #define VPP_POSTBLEND_VD1_V_START_END 0x1d1d
  377. #define VPP_BLEND_VD2_H_START_END 0x1d1e
  378. #define VPP_BLEND_VD2_V_START_END 0x1d1f
  379. #define VPP_PREBLEND_H_SIZE 0x1d20
  380. #define VPP_POSTBLEND_H_SIZE 0x1d21
  381. #define VPP_HOLD_LINES 0x1d22
  382. #define VPP_POSTBLEND_HOLD_LINES(lines) (lines & 0xf)
  383. #define VPP_PREBLEND_HOLD_LINES(lines) ((lines & 0xf) << 8)
  384. #define VPP_BLEND_ONECOLOR_CTRL 0x1d23
  385. #define VPP_PREBLEND_CURRENT_XY 0x1d24
  386. #define VPP_POSTBLEND_CURRENT_XY 0x1d25
  387. #define VPP_MISC 0x1d26
  388. #define VPP_PREBLEND_ENABLE BIT(6)
  389. #define VPP_POSTBLEND_ENABLE BIT(7)
  390. #define VPP_OSD2_ALPHA_PREMULT BIT(8)
  391. #define VPP_OSD1_ALPHA_PREMULT BIT(9)
  392. #define VPP_VD1_POSTBLEND BIT(10)
  393. #define VPP_VD2_POSTBLEND BIT(11)
  394. #define VPP_OSD1_POSTBLEND BIT(12)
  395. #define VPP_OSD2_POSTBLEND BIT(13)
  396. #define VPP_VD1_PREBLEND BIT(14)
  397. #define VPP_VD2_PREBLEND BIT(15)
  398. #define VPP_OSD1_PREBLEND BIT(16)
  399. #define VPP_OSD2_PREBLEND BIT(17)
  400. #define VPP_COLOR_MNG_ENABLE BIT(28)
  401. #define VPP_OFIFO_SIZE 0x1d27
  402. #define VPP_OFIFO_SIZE_MASK GENMASK(13, 0)
  403. #define VPP_OFIFO_SIZE_DEFAULT (0xfff << 20 | 0x1000)
  404. #define VPP_FIFO_STATUS 0x1d28
  405. #define VPP_SMOKE_CTRL 0x1d29
  406. #define VPP_SMOKE1_VAL 0x1d2a
  407. #define VPP_SMOKE2_VAL 0x1d2b
  408. #define VPP_SMOKE3_VAL 0x1d2c
  409. #define VPP_SMOKE1_H_START_END 0x1d2d
  410. #define VPP_SMOKE1_V_START_END 0x1d2e
  411. #define VPP_SMOKE2_H_START_END 0x1d2f
  412. #define VPP_SMOKE2_V_START_END 0x1d30
  413. #define VPP_SMOKE3_H_START_END 0x1d31
  414. #define VPP_SMOKE3_V_START_END 0x1d32
  415. #define VPP_SCO_FIFO_CTRL 0x1d33
  416. #define VPP_HSC_PHASE_CTRL1 0x1d34
  417. #define VPP_HSC_INI_PAT_CTRL 0x1d35
  418. #define VPP_VADJ_CTRL 0x1d40
  419. #define VPP_MINUS_BLACK_LVL_VADJ1_ENABLE BIT(1)
  420. #define VPP_VADJ1_Y 0x1d41
  421. #define VPP_VADJ1_MA_MB 0x1d42
  422. #define VPP_VADJ1_MC_MD 0x1d43
  423. #define VPP_VADJ2_Y 0x1d44
  424. #define VPP_VADJ2_MA_MB 0x1d45
  425. #define VPP_VADJ2_MC_MD 0x1d46
  426. #define VPP_HSHARP_CTRL 0x1d50
  427. #define VPP_HSHARP_LUMA_THRESH01 0x1d51
  428. #define VPP_HSHARP_LUMA_THRESH23 0x1d52
  429. #define VPP_HSHARP_CHROMA_THRESH01 0x1d53
  430. #define VPP_HSHARP_CHROMA_THRESH23 0x1d54
  431. #define VPP_HSHARP_LUMA_GAIN 0x1d55
  432. #define VPP_HSHARP_CHROMA_GAIN 0x1d56
  433. #define VPP_MATRIX_PROBE_COLOR 0x1d5c
  434. #define VPP_MATRIX_HL_COLOR 0x1d5d
  435. #define VPP_MATRIX_PROBE_POS 0x1d5e
  436. #define VPP_MATRIX_CTRL 0x1d5f
  437. #define VPP_MATRIX_COEF00_01 0x1d60
  438. #define VPP_MATRIX_COEF02_10 0x1d61
  439. #define VPP_MATRIX_COEF11_12 0x1d62
  440. #define VPP_MATRIX_COEF20_21 0x1d63
  441. #define VPP_MATRIX_COEF22 0x1d64
  442. #define VPP_MATRIX_OFFSET0_1 0x1d65
  443. #define VPP_MATRIX_OFFSET2 0x1d66
  444. #define VPP_MATRIX_PRE_OFFSET0_1 0x1d67
  445. #define VPP_MATRIX_PRE_OFFSET2 0x1d68
  446. #define VPP_DUMMY_DATA1 0x1d69
  447. #define VPP_GAINOFF_CTRL0 0x1d6a
  448. #define VPP_GAINOFF_CTRL1 0x1d6b
  449. #define VPP_GAINOFF_CTRL2 0x1d6c
  450. #define VPP_GAINOFF_CTRL3 0x1d6d
  451. #define VPP_GAINOFF_CTRL4 0x1d6e
  452. #define VPP_CHROMA_ADDR_PORT 0x1d70
  453. #define VPP_CHROMA_DATA_PORT 0x1d71
  454. #define VPP_GCLK_CTRL0 0x1d72
  455. #define VPP_GCLK_CTRL1 0x1d73
  456. #define VPP_SC_GCLK_CTRL 0x1d74
  457. #define VPP_MISC1 0x1d76
  458. #define VPP_BLACKEXT_CTRL 0x1d80
  459. #define VPP_DNLP_CTRL_00 0x1d81
  460. #define VPP_DNLP_CTRL_01 0x1d82
  461. #define VPP_DNLP_CTRL_02 0x1d83
  462. #define VPP_DNLP_CTRL_03 0x1d84
  463. #define VPP_DNLP_CTRL_04 0x1d85
  464. #define VPP_DNLP_CTRL_05 0x1d86
  465. #define VPP_DNLP_CTRL_06 0x1d87
  466. #define VPP_DNLP_CTRL_07 0x1d88
  467. #define VPP_DNLP_CTRL_08 0x1d89
  468. #define VPP_DNLP_CTRL_09 0x1d8a
  469. #define VPP_DNLP_CTRL_10 0x1d8b
  470. #define VPP_DNLP_CTRL_11 0x1d8c
  471. #define VPP_DNLP_CTRL_12 0x1d8d
  472. #define VPP_DNLP_CTRL_13 0x1d8e
  473. #define VPP_DNLP_CTRL_14 0x1d8f
  474. #define VPP_DNLP_CTRL_15 0x1d90
  475. #define VPP_PEAKING_HGAIN 0x1d91
  476. #define VPP_PEAKING_VGAIN 0x1d92
  477. #define VPP_PEAKING_NLP_1 0x1d93
  478. #define VPP_DOLBY_CTRL 0x1d93
  479. #define VPP_PPS_DUMMY_DATA_MODE (1 << 17)
  480. #define VPP_PEAKING_NLP_2 0x1d94
  481. #define VPP_PEAKING_NLP_3 0x1d95
  482. #define VPP_PEAKING_NLP_4 0x1d96
  483. #define VPP_PEAKING_NLP_5 0x1d97
  484. #define VPP_SHARP_LIMIT 0x1d98
  485. #define VPP_VLTI_CTRL 0x1d99
  486. #define VPP_HLTI_CTRL 0x1d9a
  487. #define VPP_CTI_CTRL 0x1d9b
  488. #define VPP_BLUE_STRETCH_1 0x1d9c
  489. #define VPP_BLUE_STRETCH_2 0x1d9d
  490. #define VPP_BLUE_STRETCH_3 0x1d9e
  491. #define VPP_CCORING_CTRL 0x1da0
  492. #define VPP_VE_ENABLE_CTRL 0x1da1
  493. #define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2
  494. #define VPP_VE_DEMO_CENTER_BAR 0x1da3
  495. #define VPP_VE_H_V_SIZE 0x1da4
  496. #define VPP_VDO_MEAS_CTRL 0x1da8
  497. #define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9
  498. #define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa
  499. #define VPP_INPUT_CTRL 0x1dab
  500. #define VPP_CTI_CTRL2 0x1dac
  501. #define VPP_PEAKING_SAT_THD1 0x1dad
  502. #define VPP_PEAKING_SAT_THD2 0x1dae
  503. #define VPP_PEAKING_SAT_THD3 0x1daf
  504. #define VPP_PEAKING_SAT_THD4 0x1db0
  505. #define VPP_PEAKING_SAT_THD5 0x1db1
  506. #define VPP_PEAKING_SAT_THD6 0x1db2
  507. #define VPP_PEAKING_SAT_THD7 0x1db3
  508. #define VPP_PEAKING_SAT_THD8 0x1db4
  509. #define VPP_PEAKING_SAT_THD9 0x1db5
  510. #define VPP_PEAKING_GAIN_ADD1 0x1db6
  511. #define VPP_PEAKING_GAIN_ADD2 0x1db7
  512. #define VPP_PEAKING_DNLP 0x1db8
  513. #define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9
  514. #define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba
  515. #define VPP_FRONT_HLTI_CTRL 0x1dbb
  516. #define VPP_FRONT_CTI_CTRL 0x1dbc
  517. #define VPP_FRONT_CTI_CTRL2 0x1dbd
  518. #define VPP_OSD_VSC_PHASE_STEP 0x1dc0
  519. #define VPP_OSD_VSC_INI_PHASE 0x1dc1
  520. #define VPP_OSD_VSC_CTRL0 0x1dc2
  521. #define VPP_OSD_HSC_PHASE_STEP 0x1dc3
  522. #define VPP_OSD_HSC_INI_PHASE 0x1dc4
  523. #define VPP_OSD_HSC_CTRL0 0x1dc5
  524. #define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6
  525. #define VPP_OSD_SC_DUMMY_DATA 0x1dc7
  526. #define VPP_OSD_SC_CTRL0 0x1dc8
  527. #define VPP_OSD_SCI_WH_M1 0x1dc9
  528. #define VPP_OSD_SCO_H_START_END 0x1dca
  529. #define VPP_OSD_SCO_V_START_END 0x1dcb
  530. #define VPP_OSD_SCALE_COEF_IDX 0x1dcc
  531. #define VPP_OSD_SCALE_COEF 0x1dcd
  532. #define VPP_INT_LINE_NUM 0x1dce
  533. #define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60
  534. #define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61
  535. #define VPP_WRAP_OSD1_MATRIX_COEF11_12 0x3d62
  536. #define VPP_WRAP_OSD1_MATRIX_COEF20_21 0x3d63
  537. #define VPP_WRAP_OSD1_MATRIX_COEF22 0x3d64
  538. #define VPP_WRAP_OSD1_MATRIX_COEF13_14 0x3d65
  539. #define VPP_WRAP_OSD1_MATRIX_COEF23_24 0x3d66
  540. #define VPP_WRAP_OSD1_MATRIX_COEF15_25 0x3d67
  541. #define VPP_WRAP_OSD1_MATRIX_CLIP 0x3d68
  542. #define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 0x3d69
  543. #define VPP_WRAP_OSD1_MATRIX_OFFSET2 0x3d6a
  544. #define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 0x3d6b
  545. #define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 0x3d6c
  546. #define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d
  547. #define VPP_WRAP_OSD2_MATRIX_COEF00_01 0x3d70
  548. #define VPP_WRAP_OSD2_MATRIX_COEF02_10 0x3d71
  549. #define VPP_WRAP_OSD2_MATRIX_COEF11_12 0x3d72
  550. #define VPP_WRAP_OSD2_MATRIX_COEF20_21 0x3d73
  551. #define VPP_WRAP_OSD2_MATRIX_COEF22 0x3d74
  552. #define VPP_WRAP_OSD2_MATRIX_COEF13_14 0x3d75
  553. #define VPP_WRAP_OSD2_MATRIX_COEF23_24 0x3d76
  554. #define VPP_WRAP_OSD2_MATRIX_COEF15_25 0x3d77
  555. #define VPP_WRAP_OSD2_MATRIX_CLIP 0x3d78
  556. #define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 0x3d79
  557. #define VPP_WRAP_OSD2_MATRIX_OFFSET2 0x3d7a
  558. #define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 0x3d7b
  559. #define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 0x3d7c
  560. #define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d
  561. #define VPP_WRAP_OSD3_MATRIX_COEF00_01 0x3db0
  562. #define VPP_WRAP_OSD3_MATRIX_COEF02_10 0x3db1
  563. #define VPP_WRAP_OSD3_MATRIX_COEF11_12 0x3db2
  564. #define VPP_WRAP_OSD3_MATRIX_COEF20_21 0x3db3
  565. #define VPP_WRAP_OSD3_MATRIX_COEF22 0x3db4
  566. #define VPP_WRAP_OSD3_MATRIX_COEF13_14 0x3db5
  567. #define VPP_WRAP_OSD3_MATRIX_COEF23_24 0x3db6
  568. #define VPP_WRAP_OSD3_MATRIX_COEF15_25 0x3db7
  569. #define VPP_WRAP_OSD3_MATRIX_CLIP 0x3db8
  570. #define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 0x3db9
  571. #define VPP_WRAP_OSD3_MATRIX_OFFSET2 0x3dba
  572. #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 0x3dbb
  573. #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc
  574. #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
  575. /* osd2 scaler */
  576. #define OSD2_VSC_PHASE_STEP 0x3d00
  577. #define OSD2_VSC_INI_PHASE 0x3d01
  578. #define OSD2_VSC_CTRL0 0x3d02
  579. #define OSD2_HSC_PHASE_STEP 0x3d03
  580. #define OSD2_HSC_INI_PHASE 0x3d04
  581. #define OSD2_HSC_CTRL0 0x3d05
  582. #define OSD2_HSC_INI_PAT_CTRL 0x3d06
  583. #define OSD2_SC_DUMMY_DATA 0x3d07
  584. #define OSD2_SC_CTRL0 0x3d08
  585. #define OSD2_SCI_WH_M1 0x3d09
  586. #define OSD2_SCO_H_START_END 0x3d0a
  587. #define OSD2_SCO_V_START_END 0x3d0b
  588. #define OSD2_SCALE_COEF_IDX 0x3d18
  589. #define OSD2_SCALE_COEF 0x3d19
  590. /* osd34 scaler */
  591. #define OSD34_SCALE_COEF_IDX 0x3d1e
  592. #define OSD34_SCALE_COEF 0x3d1f
  593. #define OSD34_VSC_PHASE_STEP 0x3d20
  594. #define OSD34_VSC_INI_PHASE 0x3d21
  595. #define OSD34_VSC_CTRL0 0x3d22
  596. #define OSD34_HSC_PHASE_STEP 0x3d23
  597. #define OSD34_HSC_INI_PHASE 0x3d24
  598. #define OSD34_HSC_CTRL0 0x3d25
  599. #define OSD34_HSC_INI_PAT_CTRL 0x3d26
  600. #define OSD34_SC_DUMMY_DATA 0x3d27
  601. #define OSD34_SC_CTRL0 0x3d28
  602. #define OSD34_SCI_WH_M1 0x3d29
  603. #define OSD34_SCO_H_START_END 0x3d2a
  604. #define OSD34_SCO_V_START_END 0x3d2b
  605. /* viu2 */
  606. #define VIU2_ADDR_START 0x1e00
  607. #define VIU2_ADDR_END 0x1eff
  608. #define VIU2_SW_RESET 0x1e01
  609. #define VIU2_OSD1_CTRL_STAT 0x1e10
  610. #define VIU2_OSD1_CTRL_STAT2 0x1e2d
  611. #define VIU2_OSD1_COLOR_ADDR 0x1e11
  612. #define VIU2_OSD1_COLOR 0x1e12
  613. #define VIU2_OSD1_TCOLOR_AG0 0x1e17
  614. #define VIU2_OSD1_TCOLOR_AG1 0x1e18
  615. #define VIU2_OSD1_TCOLOR_AG2 0x1e19
  616. #define VIU2_OSD1_TCOLOR_AG3 0x1e1a
  617. #define VIU2_OSD1_BLK0_CFG_W0 0x1e1b
  618. #define VIU2_OSD1_BLK1_CFG_W0 0x1e1f
  619. #define VIU2_OSD1_BLK2_CFG_W0 0x1e23
  620. #define VIU2_OSD1_BLK3_CFG_W0 0x1e27
  621. #define VIU2_OSD1_BLK0_CFG_W1 0x1e1c
  622. #define VIU2_OSD1_BLK1_CFG_W1 0x1e20
  623. #define VIU2_OSD1_BLK2_CFG_W1 0x1e24
  624. #define VIU2_OSD1_BLK3_CFG_W1 0x1e28
  625. #define VIU2_OSD1_BLK0_CFG_W2 0x1e1d
  626. #define VIU2_OSD1_BLK1_CFG_W2 0x1e21
  627. #define VIU2_OSD1_BLK2_CFG_W2 0x1e25
  628. #define VIU2_OSD1_BLK3_CFG_W2 0x1e29
  629. #define VIU2_OSD1_BLK0_CFG_W3 0x1e1e
  630. #define VIU2_OSD1_BLK1_CFG_W3 0x1e22
  631. #define VIU2_OSD1_BLK2_CFG_W3 0x1e26
  632. #define VIU2_OSD1_BLK3_CFG_W3 0x1e2a
  633. #define VIU2_OSD1_BLK0_CFG_W4 0x1e13
  634. #define VIU2_OSD1_BLK1_CFG_W4 0x1e14
  635. #define VIU2_OSD1_BLK2_CFG_W4 0x1e15
  636. #define VIU2_OSD1_BLK3_CFG_W4 0x1e16
  637. #define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b
  638. #define VIU2_OSD1_TEST_RDDATA 0x1e2c
  639. #define VIU2_OSD1_PROT_CTRL 0x1e2e
  640. #define VIU2_OSD2_CTRL_STAT 0x1e30
  641. #define VIU2_OSD2_CTRL_STAT2 0x1e4d
  642. #define VIU2_OSD2_COLOR_ADDR 0x1e31
  643. #define VIU2_OSD2_COLOR 0x1e32
  644. #define VIU2_OSD2_HL1_H_START_END 0x1e33
  645. #define VIU2_OSD2_HL1_V_START_END 0x1e34
  646. #define VIU2_OSD2_HL2_H_START_END 0x1e35
  647. #define VIU2_OSD2_HL2_V_START_END 0x1e36
  648. #define VIU2_OSD2_TCOLOR_AG0 0x1e37
  649. #define VIU2_OSD2_TCOLOR_AG1 0x1e38
  650. #define VIU2_OSD2_TCOLOR_AG2 0x1e39
  651. #define VIU2_OSD2_TCOLOR_AG3 0x1e3a
  652. #define VIU2_OSD2_BLK0_CFG_W0 0x1e3b
  653. #define VIU2_OSD2_BLK1_CFG_W0 0x1e3f
  654. #define VIU2_OSD2_BLK2_CFG_W0 0x1e43
  655. #define VIU2_OSD2_BLK3_CFG_W0 0x1e47
  656. #define VIU2_OSD2_BLK0_CFG_W1 0x1e3c
  657. #define VIU2_OSD2_BLK1_CFG_W1 0x1e40
  658. #define VIU2_OSD2_BLK2_CFG_W1 0x1e44
  659. #define VIU2_OSD2_BLK3_CFG_W1 0x1e48
  660. #define VIU2_OSD2_BLK0_CFG_W2 0x1e3d
  661. #define VIU2_OSD2_BLK1_CFG_W2 0x1e41
  662. #define VIU2_OSD2_BLK2_CFG_W2 0x1e45
  663. #define VIU2_OSD2_BLK3_CFG_W2 0x1e49
  664. #define VIU2_OSD2_BLK0_CFG_W3 0x1e3e
  665. #define VIU2_OSD2_BLK1_CFG_W3 0x1e42
  666. #define VIU2_OSD2_BLK2_CFG_W3 0x1e46
  667. #define VIU2_OSD2_BLK3_CFG_W3 0x1e4a
  668. #define VIU2_OSD2_BLK0_CFG_W4 0x1e64
  669. #define VIU2_OSD2_BLK1_CFG_W4 0x1e65
  670. #define VIU2_OSD2_BLK2_CFG_W4 0x1e66
  671. #define VIU2_OSD2_BLK3_CFG_W4 0x1e67
  672. #define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b
  673. #define VIU2_OSD2_TEST_RDDATA 0x1e4c
  674. #define VIU2_OSD2_PROT_CTRL 0x1e4e
  675. #define VIU2_VD1_IF0_GEN_REG 0x1e50
  676. #define VIU2_VD1_IF0_CANVAS0 0x1e51
  677. #define VIU2_VD1_IF0_CANVAS1 0x1e52
  678. #define VIU2_VD1_IF0_LUMA_X0 0x1e53
  679. #define VIU2_VD1_IF0_LUMA_Y0 0x1e54
  680. #define VIU2_VD1_IF0_CHROMA_X0 0x1e55
  681. #define VIU2_VD1_IF0_CHROMA_Y0 0x1e56
  682. #define VIU2_VD1_IF0_LUMA_X1 0x1e57
  683. #define VIU2_VD1_IF0_LUMA_Y1 0x1e58
  684. #define VIU2_VD1_IF0_CHROMA_X1 0x1e59
  685. #define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a
  686. #define VIU2_VD1_IF0_RPT_LOOP 0x1e5b
  687. #define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c
  688. #define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d
  689. #define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e
  690. #define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f
  691. #define VIU2_VD1_IF0_LUMA_PSEL 0x1e60
  692. #define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61
  693. #define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62
  694. #define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63
  695. #define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a
  696. #define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b
  697. #define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c
  698. #define VIU2_VD1_IF0_GEN_REG2 0x1e6d
  699. #define VIU2_VD1_IF0_PROT_CNTL 0x1e6e
  700. #define VIU2_VD1_FMT_CTRL 0x1e68
  701. #define VIU2_VD1_FMT_W 0x1e69
  702. /* encode */
  703. #define ENCP_VFIFO2VD_CTL 0x1b58
  704. #define ENCP_VFIFO2VD_PIXEL_START 0x1b59
  705. #define ENCP_VFIFO2VD_PIXEL_END 0x1b5a
  706. #define ENCP_VFIFO2VD_LINE_TOP_START 0x1b5b
  707. #define ENCP_VFIFO2VD_LINE_TOP_END 0x1b5c
  708. #define ENCP_VFIFO2VD_LINE_BOT_START 0x1b5d
  709. #define ENCP_VFIFO2VD_LINE_BOT_END 0x1b5e
  710. #define VENC_SYNC_ROUTE 0x1b60
  711. #define VENC_VIDEO_EXSRC 0x1b61
  712. #define VENC_DVI_SETTING 0x1b62
  713. #define VENC_C656_CTRL 0x1b63
  714. #define VENC_UPSAMPLE_CTRL0 0x1b64
  715. #define VENC_UPSAMPLE_CTRL1 0x1b65
  716. #define VENC_UPSAMPLE_CTRL2 0x1b66
  717. #define VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO BIT(0)
  718. #define VENC_UPSAMPLE_CTRL_F1_EN BIT(5)
  719. #define VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN BIT(6)
  720. #define VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA (0x0 << 12)
  721. #define VENC_UPSAMPLE_CTRL_CVBS (0x1 << 12)
  722. #define VENC_UPSAMPLE_CTRL_S_VIDEO_LUMA (0x2 << 12)
  723. #define VENC_UPSAMPLE_CTRL_S_VIDEO_CHROMA (0x3 << 12)
  724. #define VENC_UPSAMPLE_CTRL_INTERLACE_PB (0x4 << 12)
  725. #define VENC_UPSAMPLE_CTRL_INTERLACE_PR (0x5 << 12)
  726. #define VENC_UPSAMPLE_CTRL_INTERLACE_R (0x6 << 12)
  727. #define VENC_UPSAMPLE_CTRL_INTERLACE_G (0x7 << 12)
  728. #define VENC_UPSAMPLE_CTRL_INTERLACE_B (0x8 << 12)
  729. #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_Y (0x9 << 12)
  730. #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PB (0xa << 12)
  731. #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PR (0xb << 12)
  732. #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_R (0xc << 12)
  733. #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_G (0xd << 12)
  734. #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_B (0xe << 12)
  735. #define VENC_UPSAMPLE_CTRL_VDAC_TEST_VALUE (0xf << 12)
  736. #define TCON_INVERT_CTL 0x1b67
  737. #define VENC_VIDEO_PROG_MODE 0x1b68
  738. #define VENC_ENCI_LINE 0x1b69
  739. #define VENC_ENCI_PIXEL 0x1b6a
  740. #define VENC_ENCP_LINE 0x1b6b
  741. #define VENC_ENCP_PIXEL 0x1b6c
  742. #define VENC_STATA 0x1b6d
  743. #define VENC_INTCTRL 0x1b6e
  744. #define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1)
  745. #define VENC_INTFLAG 0x1b6f
  746. #define VENC_VIDEO_TST_EN 0x1b70
  747. #define VENC_VIDEO_TST_MDSEL 0x1b71
  748. #define VENC_VIDEO_TST_Y 0x1b72
  749. #define VENC_VIDEO_TST_CB 0x1b73
  750. #define VENC_VIDEO_TST_CR 0x1b74
  751. #define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75
  752. #define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76
  753. #define VENC_VIDEO_TST_VDCNT_STSET 0x1b77
  754. #define VENC_VDAC_DACSEL0 0x1b78
  755. #define VENC_VDAC_SEL_ATV_DMD BIT(5)
  756. #define VENC_VDAC_DACSEL1 0x1b79
  757. #define VENC_VDAC_DACSEL2 0x1b7a
  758. #define VENC_VDAC_DACSEL3 0x1b7b
  759. #define VENC_VDAC_DACSEL4 0x1b7c
  760. #define VENC_VDAC_DACSEL5 0x1b7d
  761. #define VENC_VDAC_SETTING 0x1b7e
  762. #define VENC_VDAC_TST_VAL 0x1b7f
  763. #define VENC_VDAC_DAC0_GAINCTRL 0x1bf0
  764. #define VENC_VDAC_DAC0_OFFSET 0x1bf1
  765. #define VENC_VDAC_DAC1_GAINCTRL 0x1bf2
  766. #define VENC_VDAC_DAC1_OFFSET 0x1bf3
  767. #define VENC_VDAC_DAC2_GAINCTRL 0x1bf4
  768. #define VENC_VDAC_DAC2_OFFSET 0x1bf5
  769. #define VENC_VDAC_DAC3_GAINCTRL 0x1bf6
  770. #define VENC_VDAC_DAC3_OFFSET 0x1bf7
  771. #define VENC_VDAC_DAC4_GAINCTRL 0x1bf8
  772. #define VENC_VDAC_DAC4_OFFSET 0x1bf9
  773. #define VENC_VDAC_DAC5_GAINCTRL 0x1bfa
  774. #define VENC_VDAC_DAC5_OFFSET 0x1bfb
  775. #define VENC_VDAC_FIFO_CTRL 0x1bfc
  776. #define VENC_VDAC_FIFO_EN_ENCI_ENABLE BIT(13)
  777. #define ENCL_TCON_INVERT_CTL 0x1bfd
  778. #define ENCP_VIDEO_EN 0x1b80
  779. #define ENCP_VIDEO_SYNC_MODE 0x1b81
  780. #define ENCP_MACV_EN 0x1b82
  781. #define ENCP_VIDEO_Y_SCL 0x1b83
  782. #define ENCP_VIDEO_PB_SCL 0x1b84
  783. #define ENCP_VIDEO_PR_SCL 0x1b85
  784. #define ENCP_VIDEO_SYNC_SCL 0x1b86
  785. #define ENCP_VIDEO_MACV_SCL 0x1b87
  786. #define ENCP_VIDEO_Y_OFFST 0x1b88
  787. #define ENCP_VIDEO_PB_OFFST 0x1b89
  788. #define ENCP_VIDEO_PR_OFFST 0x1b8a
  789. #define ENCP_VIDEO_SYNC_OFFST 0x1b8b
  790. #define ENCP_VIDEO_MACV_OFFST 0x1b8c
  791. #define ENCP_VIDEO_MODE 0x1b8d
  792. #define ENCP_VIDEO_MODE_DE_V_HIGH BIT(14)
  793. #define ENCP_VIDEO_MODE_ADV 0x1b8e
  794. #define ENCP_DBG_PX_RST 0x1b90
  795. #define ENCP_DBG_LN_RST 0x1b91
  796. #define ENCP_DBG_PX_INT 0x1b92
  797. #define ENCP_DBG_LN_INT 0x1b93
  798. #define ENCP_VIDEO_YFP1_HTIME 0x1b94
  799. #define ENCP_VIDEO_YFP2_HTIME 0x1b95
  800. #define ENCP_VIDEO_YC_DLY 0x1b96
  801. #define ENCP_VIDEO_MAX_PXCNT 0x1b97
  802. #define ENCP_VIDEO_HSPULS_BEGIN 0x1b98
  803. #define ENCP_VIDEO_HSPULS_END 0x1b99
  804. #define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a
  805. #define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b
  806. #define ENCP_VIDEO_VSPULS_END 0x1b9c
  807. #define ENCP_VIDEO_VSPULS_BLINE 0x1b9d
  808. #define ENCP_VIDEO_VSPULS_ELINE 0x1b9e
  809. #define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f
  810. #define ENCP_VIDEO_EQPULS_END 0x1ba0
  811. #define ENCP_VIDEO_EQPULS_BLINE 0x1ba1
  812. #define ENCP_VIDEO_EQPULS_ELINE 0x1ba2
  813. #define ENCP_VIDEO_HAVON_END 0x1ba3
  814. #define ENCP_VIDEO_HAVON_BEGIN 0x1ba4
  815. #define ENCP_VIDEO_VAVON_ELINE 0x1baf
  816. #define ENCP_VIDEO_VAVON_BLINE 0x1ba6
  817. #define ENCP_VIDEO_HSO_BEGIN 0x1ba7
  818. #define ENCP_VIDEO_HSO_END 0x1ba8
  819. #define ENCP_VIDEO_VSO_BEGIN 0x1ba9
  820. #define ENCP_VIDEO_VSO_END 0x1baa
  821. #define ENCP_VIDEO_VSO_BLINE 0x1bab
  822. #define ENCP_VIDEO_VSO_ELINE 0x1bac
  823. #define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad
  824. #define ENCP_VIDEO_MAX_LNCNT 0x1bae
  825. #define ENCP_VIDEO_SY_VAL 0x1bb0
  826. #define ENCP_VIDEO_SY2_VAL 0x1bb1
  827. #define ENCP_VIDEO_BLANKY_VAL 0x1bb2
  828. #define ENCP_VIDEO_BLANKPB_VAL 0x1bb3
  829. #define ENCP_VIDEO_BLANKPR_VAL 0x1bb4
  830. #define ENCP_VIDEO_HOFFST 0x1bb5
  831. #define ENCP_VIDEO_VOFFST 0x1bb6
  832. #define ENCP_VIDEO_RGB_CTRL 0x1bb7
  833. #define ENCP_VIDEO_FILT_CTRL 0x1bb8
  834. #define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9
  835. #define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba
  836. #define ENCP_VIDEO_MATRIX_CB 0x1bbb
  837. #define ENCP_VIDEO_MATRIX_CR 0x1bbc
  838. #define ENCP_VIDEO_RGBIN_CTRL 0x1bbd
  839. #define ENCP_MACV_BLANKY_VAL 0x1bc0
  840. #define ENCP_MACV_MAXY_VAL 0x1bc1
  841. #define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2
  842. #define ENCP_MACV_PSSYNC_STRT 0x1bc3
  843. #define ENCP_MACV_AGC_STRT 0x1bc4
  844. #define ENCP_MACV_AGC_END 0x1bc5
  845. #define ENCP_MACV_WAVE_END 0x1bc6
  846. #define ENCP_MACV_STRTLINE 0x1bc7
  847. #define ENCP_MACV_ENDLINE 0x1bc8
  848. #define ENCP_MACV_TS_CNT_MAX_L 0x1bc9
  849. #define ENCP_MACV_TS_CNT_MAX_H 0x1bca
  850. #define ENCP_MACV_TIME_DOWN 0x1bcb
  851. #define ENCP_MACV_TIME_LO 0x1bcc
  852. #define ENCP_MACV_TIME_UP 0x1bcd
  853. #define ENCP_MACV_TIME_RST 0x1bce
  854. #define ENCP_VBI_CTRL 0x1bd0
  855. #define ENCP_VBI_SETTING 0x1bd1
  856. #define ENCP_VBI_BEGIN 0x1bd2
  857. #define ENCP_VBI_WIDTH 0x1bd3
  858. #define ENCP_VBI_HVAL 0x1bd4
  859. #define ENCP_VBI_DATA0 0x1bd5
  860. #define ENCP_VBI_DATA1 0x1bd6
  861. #define C656_HS_ST 0x1be0
  862. #define C656_HS_ED 0x1be1
  863. #define C656_VS_LNST_E 0x1be2
  864. #define C656_VS_LNST_O 0x1be3
  865. #define C656_VS_LNED_E 0x1be4
  866. #define C656_VS_LNED_O 0x1be5
  867. #define C656_FS_LNST 0x1be6
  868. #define C656_FS_LNED 0x1be7
  869. #define ENCI_VIDEO_MODE 0x1b00
  870. #define ENCI_VIDEO_MODE_ADV 0x1b01
  871. #define ENCI_VIDEO_MODE_ADV_DMXMD(val) (val & 0x3)
  872. #define ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 BIT(2)
  873. #define ENCI_VIDEO_MODE_ADV_YBW_MEDIUM (0 << 4)
  874. #define ENCI_VIDEO_MODE_ADV_YBW_LOW (0x1 << 4)
  875. #define ENCI_VIDEO_MODE_ADV_YBW_HIGH (0x2 << 4)
  876. #define ENCI_VIDEO_FSC_ADJ 0x1b02
  877. #define ENCI_VIDEO_BRIGHT 0x1b03
  878. #define ENCI_VIDEO_CONT 0x1b04
  879. #define ENCI_VIDEO_SAT 0x1b05
  880. #define ENCI_VIDEO_HUE 0x1b06
  881. #define ENCI_VIDEO_SCH 0x1b07
  882. #define ENCI_SYNC_MODE 0x1b08
  883. #define ENCI_SYNC_CTRL 0x1b09
  884. #define ENCI_SYNC_HSO_BEGIN 0x1b0a
  885. #define ENCI_SYNC_HSO_END 0x1b0b
  886. #define ENCI_SYNC_VSO_EVN 0x1b0c
  887. #define ENCI_SYNC_VSO_ODD 0x1b0d
  888. #define ENCI_SYNC_VSO_EVNLN 0x1b0e
  889. #define ENCI_SYNC_VSO_ODDLN 0x1b0f
  890. #define ENCI_SYNC_HOFFST 0x1b10
  891. #define ENCI_SYNC_VOFFST 0x1b11
  892. #define ENCI_SYNC_ADJ 0x1b12
  893. #define ENCI_RGB_SETTING 0x1b13
  894. #define ENCI_DE_H_BEGIN 0x1b16
  895. #define ENCI_DE_H_END 0x1b17
  896. #define ENCI_DE_V_BEGIN_EVEN 0x1b18
  897. #define ENCI_DE_V_END_EVEN 0x1b19
  898. #define ENCI_DE_V_BEGIN_ODD 0x1b1a
  899. #define ENCI_DE_V_END_ODD 0x1b1b
  900. #define ENCI_VBI_SETTING 0x1b20
  901. #define ENCI_VBI_CCDT_EVN 0x1b21
  902. #define ENCI_VBI_CCDT_ODD 0x1b22
  903. #define ENCI_VBI_CC525_LN 0x1b23
  904. #define ENCI_VBI_CC625_LN 0x1b24
  905. #define ENCI_VBI_WSSDT 0x1b25
  906. #define ENCI_VBI_WSS_LN 0x1b26
  907. #define ENCI_VBI_CGMSDT_L 0x1b27
  908. #define ENCI_VBI_CGMSDT_H 0x1b28
  909. #define ENCI_VBI_CGMS_LN 0x1b29
  910. #define ENCI_VBI_TTX_HTIME 0x1b2a
  911. #define ENCI_VBI_TTX_LN 0x1b2b
  912. #define ENCI_VBI_TTXDT0 0x1b2c
  913. #define ENCI_VBI_TTXDT1 0x1b2d
  914. #define ENCI_VBI_TTXDT2 0x1b2e
  915. #define ENCI_VBI_TTXDT3 0x1b2f
  916. #define ENCI_MACV_N0 0x1b30
  917. #define ENCI_MACV_N1 0x1b31
  918. #define ENCI_MACV_N2 0x1b32
  919. #define ENCI_MACV_N3 0x1b33
  920. #define ENCI_MACV_N4 0x1b34
  921. #define ENCI_MACV_N5 0x1b35
  922. #define ENCI_MACV_N6 0x1b36
  923. #define ENCI_MACV_N7 0x1b37
  924. #define ENCI_MACV_N8 0x1b38
  925. #define ENCI_MACV_N9 0x1b39
  926. #define ENCI_MACV_N10 0x1b3a
  927. #define ENCI_MACV_N11 0x1b3b
  928. #define ENCI_MACV_N12 0x1b3c
  929. #define ENCI_MACV_N13 0x1b3d
  930. #define ENCI_MACV_N14 0x1b3e
  931. #define ENCI_MACV_N15 0x1b3f
  932. #define ENCI_MACV_N16 0x1b40
  933. #define ENCI_MACV_N17 0x1b41
  934. #define ENCI_MACV_N18 0x1b42
  935. #define ENCI_MACV_N19 0x1b43
  936. #define ENCI_MACV_N20 0x1b44
  937. #define ENCI_MACV_N21 0x1b45
  938. #define ENCI_MACV_N22 0x1b46
  939. #define ENCI_DBG_PX_RST 0x1b48
  940. #define ENCI_DBG_FLDLN_RST 0x1b49
  941. #define ENCI_DBG_PX_INT 0x1b4a
  942. #define ENCI_DBG_FLDLN_INT 0x1b4b
  943. #define ENCI_DBG_MAXPX 0x1b4c
  944. #define ENCI_DBG_MAXLN 0x1b4d
  945. #define ENCI_MACV_MAX_AMP 0x1b50
  946. #define ENCI_MACV_MAX_AMP_ENABLE_CHANGE BIT(15)
  947. #define ENCI_MACV_MAX_AMP_VAL(val) (val & 0x83ff)
  948. #define ENCI_MACV_PULSE_LO 0x1b51
  949. #define ENCI_MACV_PULSE_HI 0x1b52
  950. #define ENCI_MACV_BKP_MAX 0x1b53
  951. #define ENCI_CFILT_CTRL 0x1b54
  952. #define ENCI_CFILT_CMPT_SEL_HIGH BIT(1)
  953. #define ENCI_CFILT7 0x1b55
  954. #define ENCI_YC_DELAY 0x1b56
  955. #define ENCI_VIDEO_EN 0x1b57
  956. #define ENCI_VIDEO_EN_ENABLE BIT(0)
  957. #define ENCI_DVI_HSO_BEGIN 0x1c00
  958. #define ENCI_DVI_HSO_END 0x1c01
  959. #define ENCI_DVI_VSO_BLINE_EVN 0x1c02
  960. #define ENCI_DVI_VSO_BLINE_ODD 0x1c03
  961. #define ENCI_DVI_VSO_ELINE_EVN 0x1c04
  962. #define ENCI_DVI_VSO_ELINE_ODD 0x1c05
  963. #define ENCI_DVI_VSO_BEGIN_EVN 0x1c06
  964. #define ENCI_DVI_VSO_BEGIN_ODD 0x1c07
  965. #define ENCI_DVI_VSO_END_EVN 0x1c08
  966. #define ENCI_DVI_VSO_END_ODD 0x1c09
  967. #define ENCI_CFILT_CTRL2 0x1c0a
  968. #define ENCI_CFILT_CMPT_CR_DLY(delay) (delay & 0xf)
  969. #define ENCI_CFILT_CMPT_CB_DLY(delay) ((delay & 0xf) << 4)
  970. #define ENCI_CFILT_CVBS_CR_DLY(delay) ((delay & 0xf) << 8)
  971. #define ENCI_CFILT_CVBS_CB_DLY(delay) ((delay & 0xf) << 12)
  972. #define ENCI_DACSEL_0 0x1c0b
  973. #define ENCI_DACSEL_1 0x1c0c
  974. #define ENCP_DACSEL_0 0x1c0d
  975. #define ENCP_DACSEL_1 0x1c0e
  976. #define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f
  977. #define ENCI_TST_EN 0x1c10
  978. #define ENCI_TST_MDSEL 0x1c11
  979. #define ENCI_TST_Y 0x1c12
  980. #define ENCI_TST_CB 0x1c13
  981. #define ENCI_TST_CR 0x1c14
  982. #define ENCI_TST_CLRBAR_STRT 0x1c15
  983. #define ENCI_TST_CLRBAR_WIDTH 0x1c16
  984. #define ENCI_TST_VDCNT_STSET 0x1c17
  985. #define ENCI_VFIFO2VD_CTL 0x1c18
  986. #define ENCI_VFIFO2VD_CTL_ENABLE BIT(0)
  987. #define ENCI_VFIFO2VD_CTL_VD_SEL(val) ((val & 0xff) << 8)
  988. #define ENCI_VFIFO2VD_PIXEL_START 0x1c19
  989. #define ENCI_VFIFO2VD_PIXEL_END 0x1c1a
  990. #define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b
  991. #define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c
  992. #define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d
  993. #define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e
  994. #define ENCI_VFIFO2VD_CTL2 0x1c1f
  995. #define ENCT_VFIFO2VD_CTL 0x1c20
  996. #define ENCT_VFIFO2VD_PIXEL_START 0x1c21
  997. #define ENCT_VFIFO2VD_PIXEL_END 0x1c22
  998. #define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23
  999. #define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24
  1000. #define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25
  1001. #define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26
  1002. #define ENCT_VFIFO2VD_CTL2 0x1c27
  1003. #define ENCT_TST_EN 0x1c28
  1004. #define ENCT_TST_MDSEL 0x1c29
  1005. #define ENCT_TST_Y 0x1c2a
  1006. #define ENCT_TST_CB 0x1c2b
  1007. #define ENCT_TST_CR 0x1c2c
  1008. #define ENCT_TST_CLRBAR_STRT 0x1c2d
  1009. #define ENCT_TST_CLRBAR_WIDTH 0x1c2e
  1010. #define ENCT_TST_VDCNT_STSET 0x1c2f
  1011. #define ENCP_DVI_HSO_BEGIN 0x1c30
  1012. #define ENCP_DVI_HSO_END 0x1c31
  1013. #define ENCP_DVI_VSO_BLINE_EVN 0x1c32
  1014. #define ENCP_DVI_VSO_BLINE_ODD 0x1c33
  1015. #define ENCP_DVI_VSO_ELINE_EVN 0x1c34
  1016. #define ENCP_DVI_VSO_ELINE_ODD 0x1c35
  1017. #define ENCP_DVI_VSO_BEGIN_EVN 0x1c36
  1018. #define ENCP_DVI_VSO_BEGIN_ODD 0x1c37
  1019. #define ENCP_DVI_VSO_END_EVN 0x1c38
  1020. #define ENCP_DVI_VSO_END_ODD 0x1c39
  1021. #define ENCP_DE_H_BEGIN 0x1c3a
  1022. #define ENCP_DE_H_END 0x1c3b
  1023. #define ENCP_DE_V_BEGIN_EVEN 0x1c3c
  1024. #define ENCP_DE_V_END_EVEN 0x1c3d
  1025. #define ENCP_DE_V_BEGIN_ODD 0x1c3e
  1026. #define ENCP_DE_V_END_ODD 0x1c3f
  1027. #define ENCI_SYNC_LINE_LENGTH 0x1c40
  1028. #define ENCI_SYNC_PIXEL_EN 0x1c41
  1029. #define ENCI_SYNC_TO_LINE_EN 0x1c42
  1030. #define ENCI_SYNC_TO_PIXEL 0x1c43
  1031. #define ENCP_SYNC_LINE_LENGTH 0x1c44
  1032. #define ENCP_SYNC_PIXEL_EN 0x1c45
  1033. #define ENCP_SYNC_TO_LINE_EN 0x1c46
  1034. #define ENCP_SYNC_TO_PIXEL 0x1c47
  1035. #define ENCT_SYNC_LINE_LENGTH 0x1c48
  1036. #define ENCT_SYNC_PIXEL_EN 0x1c49
  1037. #define ENCT_SYNC_TO_LINE_EN 0x1c4a
  1038. #define ENCT_SYNC_TO_PIXEL 0x1c4b
  1039. #define ENCL_SYNC_LINE_LENGTH 0x1c4c
  1040. #define ENCL_SYNC_PIXEL_EN 0x1c4d
  1041. #define ENCL_SYNC_TO_LINE_EN 0x1c4e
  1042. #define ENCL_SYNC_TO_PIXEL 0x1c4f
  1043. #define ENCP_VFIFO2VD_CTL2 0x1c50
  1044. #define VENC_DVI_SETTING_MORE 0x1c51
  1045. #define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54
  1046. #define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55
  1047. #define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56
  1048. #define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57
  1049. #define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58
  1050. #define VENC_VDAC_DAC0_FILT_CTRL0_EN BIT(0)
  1051. #define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59
  1052. #define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a
  1053. #define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b
  1054. #define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c
  1055. #define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d
  1056. #define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e
  1057. #define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f
  1058. #define ENCT_VIDEO_EN 0x1c60
  1059. #define ENCT_VIDEO_Y_SCL 0x1c61
  1060. #define ENCT_VIDEO_PB_SCL 0x1c62
  1061. #define ENCT_VIDEO_PR_SCL 0x1c63
  1062. #define ENCT_VIDEO_Y_OFFST 0x1c64
  1063. #define ENCT_VIDEO_PB_OFFST 0x1c65
  1064. #define ENCT_VIDEO_PR_OFFST 0x1c66
  1065. #define ENCT_VIDEO_MODE 0x1c67
  1066. #define ENCT_VIDEO_MODE_ADV 0x1c68
  1067. #define ENCT_DBG_PX_RST 0x1c69
  1068. #define ENCT_DBG_LN_RST 0x1c6a
  1069. #define ENCT_DBG_PX_INT 0x1c6b
  1070. #define ENCT_DBG_LN_INT 0x1c6c
  1071. #define ENCT_VIDEO_YFP1_HTIME 0x1c6d
  1072. #define ENCT_VIDEO_YFP2_HTIME 0x1c6e
  1073. #define ENCT_VIDEO_YC_DLY 0x1c6f
  1074. #define ENCT_VIDEO_MAX_PXCNT 0x1c70
  1075. #define ENCT_VIDEO_HAVON_END 0x1c71
  1076. #define ENCT_VIDEO_HAVON_BEGIN 0x1c72
  1077. #define ENCT_VIDEO_VAVON_ELINE 0x1c73
  1078. #define ENCT_VIDEO_VAVON_BLINE 0x1c74
  1079. #define ENCT_VIDEO_HSO_BEGIN 0x1c75
  1080. #define ENCT_VIDEO_HSO_END 0x1c76
  1081. #define ENCT_VIDEO_VSO_BEGIN 0x1c77
  1082. #define ENCT_VIDEO_VSO_END 0x1c78
  1083. #define ENCT_VIDEO_VSO_BLINE 0x1c79
  1084. #define ENCT_VIDEO_VSO_ELINE 0x1c7a
  1085. #define ENCT_VIDEO_MAX_LNCNT 0x1c7b
  1086. #define ENCT_VIDEO_BLANKY_VAL 0x1c7c
  1087. #define ENCT_VIDEO_BLANKPB_VAL 0x1c7d
  1088. #define ENCT_VIDEO_BLANKPR_VAL 0x1c7e
  1089. #define ENCT_VIDEO_HOFFST 0x1c7f
  1090. #define ENCT_VIDEO_VOFFST 0x1c80
  1091. #define ENCT_VIDEO_RGB_CTRL 0x1c81
  1092. #define ENCT_VIDEO_FILT_CTRL 0x1c82
  1093. #define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83
  1094. #define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84
  1095. #define ENCT_VIDEO_MATRIX_CB 0x1c85
  1096. #define ENCT_VIDEO_MATRIX_CR 0x1c86
  1097. #define ENCT_VIDEO_RGBIN_CTRL 0x1c87
  1098. #define ENCT_MAX_LINE_SWITCH_POINT 0x1c88
  1099. #define ENCT_DACSEL_0 0x1c89
  1100. #define ENCT_DACSEL_1 0x1c8a
  1101. #define ENCL_VFIFO2VD_CTL 0x1c90
  1102. #define ENCL_VFIFO2VD_PIXEL_START 0x1c91
  1103. #define ENCL_VFIFO2VD_PIXEL_END 0x1c92
  1104. #define ENCL_VFIFO2VD_LINE_TOP_START 0x1c93
  1105. #define ENCL_VFIFO2VD_LINE_TOP_END 0x1c94
  1106. #define ENCL_VFIFO2VD_LINE_BOT_START 0x1c95
  1107. #define ENCL_VFIFO2VD_LINE_BOT_END 0x1c96
  1108. #define ENCL_VFIFO2VD_CTL2 0x1c97
  1109. #define ENCL_TST_EN 0x1c98
  1110. #define ENCL_TST_MDSEL 0x1c99
  1111. #define ENCL_TST_Y 0x1c9a
  1112. #define ENCL_TST_CB 0x1c9b
  1113. #define ENCL_TST_CR 0x1c9c
  1114. #define ENCL_TST_CLRBAR_STRT 0x1c9d
  1115. #define ENCL_TST_CLRBAR_WIDTH 0x1c9e
  1116. #define ENCL_TST_VDCNT_STSET 0x1c9f
  1117. #define ENCL_VIDEO_EN 0x1ca0
  1118. #define ENCL_VIDEO_Y_SCL 0x1ca1
  1119. #define ENCL_VIDEO_PB_SCL 0x1ca2
  1120. #define ENCL_VIDEO_PR_SCL 0x1ca3
  1121. #define ENCL_VIDEO_Y_OFFST 0x1ca4
  1122. #define ENCL_VIDEO_PB_OFFST 0x1ca5
  1123. #define ENCL_VIDEO_PR_OFFST 0x1ca6
  1124. #define ENCL_VIDEO_MODE 0x1ca7
  1125. #define ENCL_VIDEO_MODE_ADV 0x1ca8
  1126. #define ENCL_DBG_PX_RST 0x1ca9
  1127. #define ENCL_DBG_LN_RST 0x1caa
  1128. #define ENCL_DBG_PX_INT 0x1cab
  1129. #define ENCL_DBG_LN_INT 0x1cac
  1130. #define ENCL_VIDEO_YFP1_HTIME 0x1cad
  1131. #define ENCL_VIDEO_YFP2_HTIME 0x1cae
  1132. #define ENCL_VIDEO_YC_DLY 0x1caf
  1133. #define ENCL_VIDEO_MAX_PXCNT 0x1cb0
  1134. #define ENCL_VIDEO_HAVON_END 0x1cb1
  1135. #define ENCL_VIDEO_HAVON_BEGIN 0x1cb2
  1136. #define ENCL_VIDEO_VAVON_ELINE 0x1cb3
  1137. #define ENCL_VIDEO_VAVON_BLINE 0x1cb4
  1138. #define ENCL_VIDEO_HSO_BEGIN 0x1cb5
  1139. #define ENCL_VIDEO_HSO_END 0x1cb6
  1140. #define ENCL_VIDEO_VSO_BEGIN 0x1cb7
  1141. #define ENCL_VIDEO_VSO_END 0x1cb8
  1142. #define ENCL_VIDEO_VSO_BLINE 0x1cb9
  1143. #define ENCL_VIDEO_VSO_ELINE 0x1cba
  1144. #define ENCL_VIDEO_MAX_LNCNT 0x1cbb
  1145. #define ENCL_VIDEO_BLANKY_VAL 0x1cbc
  1146. #define ENCL_VIDEO_BLANKPB_VAL 0x1cbd
  1147. #define ENCL_VIDEO_BLANKPR_VAL 0x1cbe
  1148. #define ENCL_VIDEO_HOFFST 0x1cbf
  1149. #define ENCL_VIDEO_VOFFST 0x1cc0
  1150. #define ENCL_VIDEO_RGB_CTRL 0x1cc1
  1151. #define ENCL_VIDEO_FILT_CTRL 0x1cc2
  1152. #define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3
  1153. #define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4
  1154. #define ENCL_VIDEO_MATRIX_CB 0x1cc5
  1155. #define ENCL_VIDEO_MATRIX_CR 0x1cc6
  1156. #define ENCL_VIDEO_RGBIN_CTRL 0x1cc7
  1157. #define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8
  1158. #define ENCL_DACSEL_0 0x1cc9
  1159. #define ENCL_DACSEL_1 0x1cca
  1160. #define RDMA_AHB_START_ADDR_MAN 0x1100
  1161. #define RDMA_AHB_END_ADDR_MAN 0x1101
  1162. #define RDMA_AHB_START_ADDR_1 0x1102
  1163. #define RDMA_AHB_END_ADDR_1 0x1103
  1164. #define RDMA_AHB_START_ADDR_2 0x1104
  1165. #define RDMA_AHB_END_ADDR_2 0x1105
  1166. #define RDMA_AHB_START_ADDR_3 0x1106
  1167. #define RDMA_AHB_END_ADDR_3 0x1107
  1168. #define RDMA_AHB_START_ADDR_4 0x1108
  1169. #define RDMA_AHB_END_ADDR_4 0x1109
  1170. #define RDMA_AHB_START_ADDR_5 0x110a
  1171. #define RDMA_AHB_END_ADDR_5 0x110b
  1172. #define RDMA_AHB_START_ADDR_6 0x110c
  1173. #define RDMA_AHB_END_ADDR_6 0x110d
  1174. #define RDMA_AHB_START_ADDR_7 0x110e
  1175. #define RDMA_AHB_END_ADDR_7 0x110f
  1176. #define RDMA_ACCESS_AUTO 0x1110
  1177. #define RDMA_ACCESS_AUTO2 0x1111
  1178. #define RDMA_ACCESS_AUTO3 0x1112
  1179. #define RDMA_ACCESS_MAN 0x1113
  1180. #define RDMA_CTRL 0x1114
  1181. #define RDMA_STATUS 0x1115
  1182. #define RDMA_STATUS2 0x1116
  1183. #define RDMA_STATUS3 0x1117
  1184. #define L_GAMMA_CNTL_PORT 0x1400
  1185. #define L_GAMMA_DATA_PORT 0x1401
  1186. #define L_GAMMA_ADDR_PORT 0x1402
  1187. #define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403
  1188. #define L_RGB_BASE_ADDR 0x1405
  1189. #define L_RGB_COEFF_ADDR 0x1406
  1190. #define L_POL_CNTL_ADDR 0x1407
  1191. #define L_DITH_CNTL_ADDR 0x1408
  1192. #define L_GAMMA_PROBE_CTRL 0x1409
  1193. #define L_GAMMA_PROBE_COLOR_L 0x140a
  1194. #define L_GAMMA_PROBE_COLOR_H 0x140b
  1195. #define L_GAMMA_PROBE_HL_COLOR 0x140c
  1196. #define L_GAMMA_PROBE_POS_X 0x140d
  1197. #define L_GAMMA_PROBE_POS_Y 0x140e
  1198. #define L_STH1_HS_ADDR 0x1410
  1199. #define L_STH1_HE_ADDR 0x1411
  1200. #define L_STH1_VS_ADDR 0x1412
  1201. #define L_STH1_VE_ADDR 0x1413
  1202. #define L_STH2_HS_ADDR 0x1414
  1203. #define L_STH2_HE_ADDR 0x1415
  1204. #define L_STH2_VS_ADDR 0x1416
  1205. #define L_STH2_VE_ADDR 0x1417
  1206. #define L_OEH_HS_ADDR 0x1418
  1207. #define L_OEH_HE_ADDR 0x1419
  1208. #define L_OEH_VS_ADDR 0x141a
  1209. #define L_OEH_VE_ADDR 0x141b
  1210. #define L_VCOM_HSWITCH_ADDR 0x141c
  1211. #define L_VCOM_VS_ADDR 0x141d
  1212. #define L_VCOM_VE_ADDR 0x141e
  1213. #define L_CPV1_HS_ADDR 0x141f
  1214. #define L_CPV1_HE_ADDR 0x1420
  1215. #define L_CPV1_VS_ADDR 0x1421
  1216. #define L_CPV1_VE_ADDR 0x1422
  1217. #define L_CPV2_HS_ADDR 0x1423
  1218. #define L_CPV2_HE_ADDR 0x1424
  1219. #define L_CPV2_VS_ADDR 0x1425
  1220. #define L_CPV2_VE_ADDR 0x1426
  1221. #define L_STV1_HS_ADDR 0x1427
  1222. #define L_STV1_HE_ADDR 0x1428
  1223. #define L_STV1_VS_ADDR 0x1429
  1224. #define L_STV1_VE_ADDR 0x142a
  1225. #define L_STV2_HS_ADDR 0x142b
  1226. #define L_STV2_HE_ADDR 0x142c
  1227. #define L_STV2_VS_ADDR 0x142d
  1228. #define L_STV2_VE_ADDR 0x142e
  1229. #define L_OEV1_HS_ADDR 0x142f
  1230. #define L_OEV1_HE_ADDR 0x1430
  1231. #define L_OEV1_VS_ADDR 0x1431
  1232. #define L_OEV1_VE_ADDR 0x1432
  1233. #define L_OEV2_HS_ADDR 0x1433
  1234. #define L_OEV2_HE_ADDR 0x1434
  1235. #define L_OEV2_VS_ADDR 0x1435
  1236. #define L_OEV2_VE_ADDR 0x1436
  1237. #define L_OEV3_HS_ADDR 0x1437
  1238. #define L_OEV3_HE_ADDR 0x1438
  1239. #define L_OEV3_VS_ADDR 0x1439
  1240. #define L_OEV3_VE_ADDR 0x143a
  1241. #define L_LCD_PWR_ADDR 0x143b
  1242. #define L_LCD_PWM0_LO_ADDR 0x143c
  1243. #define L_LCD_PWM0_HI_ADDR 0x143d
  1244. #define L_LCD_PWM1_LO_ADDR 0x143e
  1245. #define L_LCD_PWM1_HI_ADDR 0x143f
  1246. #define L_INV_CNT_ADDR 0x1440
  1247. #define L_TCON_MISC_SEL_ADDR 0x1441
  1248. #define L_DUAL_PORT_CNTL_ADDR 0x1442
  1249. #define MLVDS_CLK_CTL1_HI 0x1443
  1250. #define MLVDS_CLK_CTL1_LO 0x1444
  1251. #define L_TCON_DOUBLE_CTL 0x1449
  1252. #define L_TCON_PATTERN_HI 0x144a
  1253. #define L_TCON_PATTERN_LO 0x144b
  1254. #define LDIM_BL_ADDR_PORT 0x144e
  1255. #define LDIM_BL_DATA_PORT 0x144f
  1256. #define L_DE_HS_ADDR 0x1451
  1257. #define L_DE_HE_ADDR 0x1452
  1258. #define L_DE_VS_ADDR 0x1453
  1259. #define L_DE_VE_ADDR 0x1454
  1260. #define L_HSYNC_HS_ADDR 0x1455
  1261. #define L_HSYNC_HE_ADDR 0x1456
  1262. #define L_HSYNC_VS_ADDR 0x1457
  1263. #define L_HSYNC_VE_ADDR 0x1458
  1264. #define L_VSYNC_HS_ADDR 0x1459
  1265. #define L_VSYNC_HE_ADDR 0x145a
  1266. #define L_VSYNC_VS_ADDR 0x145b
  1267. #define L_VSYNC_VE_ADDR 0x145c
  1268. #define L_LCD_MCU_CTL 0x145d
  1269. #define DUAL_MLVDS_CTL 0x1460
  1270. #define DUAL_MLVDS_LINE_START 0x1461
  1271. #define DUAL_MLVDS_LINE_END 0x1462
  1272. #define DUAL_MLVDS_PIXEL_W_START_L 0x1463
  1273. #define DUAL_MLVDS_PIXEL_W_END_L 0x1464
  1274. #define DUAL_MLVDS_PIXEL_W_START_R 0x1465
  1275. #define DUAL_MLVDS_PIXEL_W_END_R 0x1466
  1276. #define DUAL_MLVDS_PIXEL_R_START_L 0x1467
  1277. #define DUAL_MLVDS_PIXEL_R_CNT_L 0x1468
  1278. #define DUAL_MLVDS_PIXEL_R_START_R 0x1469
  1279. #define DUAL_MLVDS_PIXEL_R_CNT_R 0x146a
  1280. #define V_INVERSION_PIXEL 0x1470
  1281. #define V_INVERSION_LINE 0x1471
  1282. #define V_INVERSION_CONTROL 0x1472
  1283. #define MLVDS2_CONTROL 0x1474
  1284. #define MLVDS2_CONFIG_HI 0x1475
  1285. #define MLVDS2_CONFIG_LO 0x1476
  1286. #define MLVDS2_DUAL_GATE_WR_START 0x1477
  1287. #define MLVDS2_DUAL_GATE_WR_END 0x1478
  1288. #define MLVDS2_DUAL_GATE_RD_START 0x1479
  1289. #define MLVDS2_DUAL_GATE_RD_END 0x147a
  1290. #define MLVDS2_SECOND_RESET_CTL 0x147b
  1291. #define MLVDS2_DUAL_GATE_CTL_HI 0x147c
  1292. #define MLVDS2_DUAL_GATE_CTL_LO 0x147d
  1293. #define MLVDS2_RESET_CONFIG_HI 0x147e
  1294. #define MLVDS2_RESET_CONFIG_LO 0x147f
  1295. #define GAMMA_CNTL_PORT 0x1480
  1296. #define GAMMA_DATA_PORT 0x1481
  1297. #define GAMMA_ADDR_PORT 0x1482
  1298. #define GAMMA_VCOM_HSWITCH_ADDR 0x1483
  1299. #define RGB_BASE_ADDR 0x1485
  1300. #define RGB_COEFF_ADDR 0x1486
  1301. #define POL_CNTL_ADDR 0x1487
  1302. #define DITH_CNTL_ADDR 0x1488
  1303. #define GAMMA_PROBE_CTRL 0x1489
  1304. #define GAMMA_PROBE_COLOR_L 0x148a
  1305. #define GAMMA_PROBE_COLOR_H 0x148b
  1306. #define GAMMA_PROBE_HL_COLOR 0x148c
  1307. #define GAMMA_PROBE_POS_X 0x148d
  1308. #define GAMMA_PROBE_POS_Y 0x148e
  1309. #define STH1_HS_ADDR 0x1490
  1310. #define STH1_HE_ADDR 0x1491
  1311. #define STH1_VS_ADDR 0x1492
  1312. #define STH1_VE_ADDR 0x1493
  1313. #define STH2_HS_ADDR 0x1494
  1314. #define STH2_HE_ADDR 0x1495
  1315. #define STH2_VS_ADDR 0x1496
  1316. #define STH2_VE_ADDR 0x1497
  1317. #define OEH_HS_ADDR 0x1498
  1318. #define OEH_HE_ADDR 0x1499
  1319. #define OEH_VS_ADDR 0x149a
  1320. #define OEH_VE_ADDR 0x149b
  1321. #define VCOM_HSWITCH_ADDR 0x149c
  1322. #define VCOM_VS_ADDR 0x149d
  1323. #define VCOM_VE_ADDR 0x149e
  1324. #define CPV1_HS_ADDR 0x149f
  1325. #define CPV1_HE_ADDR 0x14a0
  1326. #define CPV1_VS_ADDR 0x14a1
  1327. #define CPV1_VE_ADDR 0x14a2
  1328. #define CPV2_HS_ADDR 0x14a3
  1329. #define CPV2_HE_ADDR 0x14a4
  1330. #define CPV2_VS_ADDR 0x14a5
  1331. #define CPV2_VE_ADDR 0x14a6
  1332. #define STV1_HS_ADDR 0x14a7
  1333. #define STV1_HE_ADDR 0x14a8
  1334. #define STV1_VS_ADDR 0x14a9
  1335. #define STV1_VE_ADDR 0x14aa
  1336. #define STV2_HS_ADDR 0x14ab
  1337. #define STV2_HE_ADDR 0x14ac
  1338. #define STV2_VS_ADDR 0x14ad
  1339. #define STV2_VE_ADDR 0x14ae
  1340. #define OEV1_HS_ADDR 0x14af
  1341. #define OEV1_HE_ADDR 0x14b0
  1342. #define OEV1_VS_ADDR 0x14b1
  1343. #define OEV1_VE_ADDR 0x14b2
  1344. #define OEV2_HS_ADDR 0x14b3
  1345. #define OEV2_HE_ADDR 0x14b4
  1346. #define OEV2_VS_ADDR 0x14b5
  1347. #define OEV2_VE_ADDR 0x14b6
  1348. #define OEV3_HS_ADDR 0x14b7
  1349. #define OEV3_HE_ADDR 0x14b8
  1350. #define OEV3_VS_ADDR 0x14b9
  1351. #define OEV3_VE_ADDR 0x14ba
  1352. #define LCD_PWR_ADDR 0x14bb
  1353. #define LCD_PWM0_LO_ADDR 0x14bc
  1354. #define LCD_PWM0_HI_ADDR 0x14bd
  1355. #define LCD_PWM1_LO_ADDR 0x14be
  1356. #define LCD_PWM1_HI_ADDR 0x14bf
  1357. #define INV_CNT_ADDR 0x14c0
  1358. #define TCON_MISC_SEL_ADDR 0x14c1
  1359. #define DUAL_PORT_CNTL_ADDR 0x14c2
  1360. #define MLVDS_CONTROL 0x14c3
  1361. #define MLVDS_RESET_PATTERN_HI 0x14c4
  1362. #define MLVDS_RESET_PATTERN_LO 0x14c5
  1363. #define MLVDS_RESET_PATTERN_EXT 0x14c6
  1364. #define MLVDS_CONFIG_HI 0x14c7
  1365. #define MLVDS_CONFIG_LO 0x14c8
  1366. #define TCON_DOUBLE_CTL 0x14c9
  1367. #define TCON_PATTERN_HI 0x14ca
  1368. #define TCON_PATTERN_LO 0x14cb
  1369. #define TCON_CONTROL_HI 0x14cc
  1370. #define TCON_CONTROL_LO 0x14cd
  1371. #define LVDS_BLANK_DATA_HI 0x14ce
  1372. #define LVDS_BLANK_DATA_LO 0x14cf
  1373. #define LVDS_PACK_CNTL_ADDR 0x14d0
  1374. #define DE_HS_ADDR 0x14d1
  1375. #define DE_HE_ADDR 0x14d2
  1376. #define DE_VS_ADDR 0x14d3
  1377. #define DE_VE_ADDR 0x14d4
  1378. #define HSYNC_HS_ADDR 0x14d5
  1379. #define HSYNC_HE_ADDR 0x14d6
  1380. #define HSYNC_VS_ADDR 0x14d7
  1381. #define HSYNC_VE_ADDR 0x14d8
  1382. #define VSYNC_HS_ADDR 0x14d9
  1383. #define VSYNC_HE_ADDR 0x14da
  1384. #define VSYNC_VS_ADDR 0x14db
  1385. #define VSYNC_VE_ADDR 0x14dc
  1386. #define LCD_MCU_CTL 0x14dd
  1387. #define LCD_MCU_DATA_0 0x14de
  1388. #define LCD_MCU_DATA_1 0x14df
  1389. #define LVDS_GEN_CNTL 0x14e0
  1390. #define LVDS_PHY_CNTL0 0x14e1
  1391. #define LVDS_PHY_CNTL1 0x14e2
  1392. #define LVDS_PHY_CNTL2 0x14e3
  1393. #define LVDS_PHY_CNTL3 0x14e4
  1394. #define LVDS_PHY_CNTL4 0x14e5
  1395. #define LVDS_PHY_CNTL5 0x14e6
  1396. #define LVDS_SRG_TEST 0x14e8
  1397. #define LVDS_BIST_MUX0 0x14e9
  1398. #define LVDS_BIST_MUX1 0x14ea
  1399. #define LVDS_BIST_FIXED0 0x14eb
  1400. #define LVDS_BIST_FIXED1 0x14ec
  1401. #define LVDS_BIST_CNTL0 0x14ed
  1402. #define LVDS_CLKB_CLKA 0x14ee
  1403. #define LVDS_PHY_CLK_CNTL 0x14ef
  1404. #define LVDS_SER_EN 0x14f0
  1405. #define LVDS_PHY_CNTL6 0x14f1
  1406. #define LVDS_PHY_CNTL7 0x14f2
  1407. #define LVDS_PHY_CNTL8 0x14f3
  1408. #define MLVDS_CLK_CTL0_HI 0x14f4
  1409. #define MLVDS_CLK_CTL0_LO 0x14f5
  1410. #define MLVDS_DUAL_GATE_WR_START 0x14f6
  1411. #define MLVDS_DUAL_GATE_WR_END 0x14f7
  1412. #define MLVDS_DUAL_GATE_RD_START 0x14f8
  1413. #define MLVDS_DUAL_GATE_RD_END 0x14f9
  1414. #define MLVDS_SECOND_RESET_CTL 0x14fa
  1415. #define MLVDS_DUAL_GATE_CTL_HI 0x14fb
  1416. #define MLVDS_DUAL_GATE_CTL_LO 0x14fc
  1417. #define MLVDS_RESET_CONFIG_HI 0x14fd
  1418. #define MLVDS_RESET_CONFIG_LO 0x14fe
  1419. #define VPU_OSD1_MMC_CTRL 0x2701
  1420. #define VPU_OSD2_MMC_CTRL 0x2702
  1421. #define VPU_VD1_MMC_CTRL 0x2703
  1422. #define VPU_VD2_MMC_CTRL 0x2704
  1423. #define VPU_DI_IF1_MMC_CTRL 0x2705
  1424. #define VPU_DI_MEM_MMC_CTRL 0x2706
  1425. #define VPU_DI_INP_MMC_CTRL 0x2707
  1426. #define VPU_DI_MTNRD_MMC_CTRL 0x2708
  1427. #define VPU_DI_CHAN2_MMC_CTRL 0x2709
  1428. #define VPU_DI_MTNWR_MMC_CTRL 0x270a
  1429. #define VPU_DI_NRWR_MMC_CTRL 0x270b
  1430. #define VPU_DI_DIWR_MMC_CTRL 0x270c
  1431. #define VPU_VDIN0_MMC_CTRL 0x270d
  1432. #define VPU_VDIN1_MMC_CTRL 0x270e
  1433. #define VPU_BT656_MMC_CTRL 0x270f
  1434. #define VPU_TVD3D_MMC_CTRL 0x2710
  1435. #define VPU_TVDVBI_MMC_CTRL 0x2711
  1436. #define VPU_TVDVBI_VSLATCH_ADDR 0x2712
  1437. #define VPU_TVDVBI_WRRSP_ADDR 0x2713
  1438. #define VPU_VDIN_PRE_ARB_CTRL 0x2714
  1439. #define VPU_VDISP_PRE_ARB_CTRL 0x2715
  1440. #define VPU_VPUARB2_PRE_ARB_CTRL 0x2716
  1441. #define VPU_OSD3_MMC_CTRL 0x2717
  1442. #define VPU_OSD4_MMC_CTRL 0x2718
  1443. #define VPU_VD3_MMC_CTRL 0x2719
  1444. #define VPU_VIU_VENC_MUX_CTRL 0x271a
  1445. #define VIU1_SEL_VENC_MASK 0x3
  1446. #define VIU1_SEL_VENC_ENCL 0
  1447. #define VIU1_SEL_VENC_ENCI 1
  1448. #define VIU1_SEL_VENC_ENCP 2
  1449. #define VIU1_SEL_VENC_ENCT 3
  1450. #define VIU2_SEL_VENC_MASK 0xc
  1451. #define VIU2_SEL_VENC_ENCL 0
  1452. #define VIU2_SEL_VENC_ENCI (1 << 2)
  1453. #define VIU2_SEL_VENC_ENCP (2 << 2)
  1454. #define VIU2_SEL_VENC_ENCT (3 << 2)
  1455. #define VPU_HDMI_SETTING 0x271b
  1456. #define VPU_HDMI_ENCI_DATA_TO_HDMI BIT(0)
  1457. #define VPU_HDMI_ENCP_DATA_TO_HDMI BIT(1)
  1458. #define VPU_HDMI_INV_HSYNC BIT(2)
  1459. #define VPU_HDMI_INV_VSYNC BIT(3)
  1460. #define VPU_HDMI_OUTPUT_CRYCB (0 << 5)
  1461. #define VPU_HDMI_OUTPUT_YCBCR (1 << 5)
  1462. #define VPU_HDMI_OUTPUT_YCRCB (2 << 5)
  1463. #define VPU_HDMI_OUTPUT_CBCRY (3 << 5)
  1464. #define VPU_HDMI_OUTPUT_CBYCR (4 << 5)
  1465. #define VPU_HDMI_OUTPUT_CRCBY (5 << 5)
  1466. #define VPU_HDMI_WR_RATE(rate) (((rate & 0x1f) - 1) << 8)
  1467. #define VPU_HDMI_RD_RATE(rate) (((rate & 0x1f) - 1) << 12)
  1468. #define ENCI_INFO_READ 0x271c
  1469. #define ENCP_INFO_READ 0x271d
  1470. #define ENCT_INFO_READ 0x271e
  1471. #define ENCL_INFO_READ 0x271f
  1472. #define VPU_SW_RESET 0x2720
  1473. #define VPU_D2D3_MMC_CTRL 0x2721
  1474. #define VPU_CONT_MMC_CTRL 0x2722
  1475. #define VPU_CLK_GATE 0x2723
  1476. #define VPU_RDMA_MMC_CTRL 0x2724
  1477. #define VPU_MEM_PD_REG0 0x2725
  1478. #define VPU_MEM_PD_REG1 0x2726
  1479. #define VPU_HDMI_DATA_OVR 0x2727
  1480. #define VPU_PROT1_MMC_CTRL 0x2728
  1481. #define VPU_PROT2_MMC_CTRL 0x2729
  1482. #define VPU_PROT3_MMC_CTRL 0x272a
  1483. #define VPU_ARB4_V1_MMC_CTRL 0x272b
  1484. #define VPU_ARB4_V2_MMC_CTRL 0x272c
  1485. #define VPU_VPU_PWM_V0 0x2730
  1486. #define VPU_VPU_PWM_V1 0x2731
  1487. #define VPU_VPU_PWM_V2 0x2732
  1488. #define VPU_VPU_PWM_V3 0x2733
  1489. #define VPU_VPU_PWM_H0 0x2734
  1490. #define VPU_VPU_PWM_H1 0x2735
  1491. #define VPU_VPU_PWM_H2 0x2736
  1492. #define VPU_VPU_PWM_H3 0x2737
  1493. #define VPU_MISC_CTRL 0x2740
  1494. #define VPU_ISP_GCLK_CTRL0 0x2741
  1495. #define VPU_ISP_GCLK_CTRL1 0x2742
  1496. #define VPU_HDMI_FMT_CTRL 0x2743
  1497. #define VPU_VDIN_ASYNC_HOLD_CTRL 0x2743
  1498. #define VPU_VDISP_ASYNC_HOLD_CTRL 0x2744
  1499. #define VPU_VPUARB2_ASYNC_HOLD_CTRL 0x2745
  1500. #define VPU_PROT1_CLK_GATE 0x2750
  1501. #define VPU_PROT1_GEN_CNTL 0x2751
  1502. #define VPU_PROT1_X_START_END 0x2752
  1503. #define VPU_PROT1_Y_START_END 0x2753
  1504. #define VPU_PROT1_Y_LEN_STEP 0x2754
  1505. #define VPU_PROT1_RPT_LOOP 0x2755
  1506. #define VPU_PROT1_RPT_PAT 0x2756
  1507. #define VPU_PROT1_DDR 0x2757
  1508. #define VPU_PROT1_RBUF_ROOM 0x2758
  1509. #define VPU_PROT1_STAT_0 0x2759
  1510. #define VPU_PROT1_STAT_1 0x275a
  1511. #define VPU_PROT1_STAT_2 0x275b
  1512. #define VPU_PROT1_REQ_ONOFF 0x275c
  1513. #define VPU_PROT2_CLK_GATE 0x2760
  1514. #define VPU_PROT2_GEN_CNTL 0x2761
  1515. #define VPU_PROT2_X_START_END 0x2762
  1516. #define VPU_PROT2_Y_START_END 0x2763
  1517. #define VPU_PROT2_Y_LEN_STEP 0x2764
  1518. #define VPU_PROT2_RPT_LOOP 0x2765
  1519. #define VPU_PROT2_RPT_PAT 0x2766
  1520. #define VPU_PROT2_DDR 0x2767
  1521. #define VPU_PROT2_RBUF_ROOM 0x2768
  1522. #define VPU_PROT2_STAT_0 0x2769
  1523. #define VPU_PROT2_STAT_1 0x276a
  1524. #define VPU_PROT2_STAT_2 0x276b
  1525. #define VPU_PROT2_REQ_ONOFF 0x276c
  1526. #define VPU_PROT3_CLK_GATE 0x2770
  1527. #define VPU_PROT3_GEN_CNTL 0x2771
  1528. #define VPU_PROT3_X_START_END 0x2772
  1529. #define VPU_PROT3_Y_START_END 0x2773
  1530. #define VPU_PROT3_Y_LEN_STEP 0x2774
  1531. #define VPU_PROT3_RPT_LOOP 0x2775
  1532. #define VPU_PROT3_RPT_PAT 0x2776
  1533. #define VPU_PROT3_DDR 0x2777
  1534. #define VPU_PROT3_RBUF_ROOM 0x2778
  1535. #define VPU_PROT3_STAT_0 0x2779
  1536. #define VPU_PROT3_STAT_1 0x277a
  1537. #define VPU_PROT3_STAT_2 0x277b
  1538. #define VPU_PROT3_REQ_ONOFF 0x277c
  1539. #define VPU_RDARB_MODE_L1C1 0x2790
  1540. #define VPU_RDARB_MODE_L1C2 0x2799
  1541. #define VPU_RDARB_MODE_L2C1 0x279d
  1542. #define VPU_WRARB_MODE_L2C1 0x27a2
  1543. #define VPU_RDARB_SLAVE_TO_MASTER_PORT(dc, port) (port << (16 + dc))
  1544. /* osd super scale */
  1545. #define OSDSR_HV_SIZEIN 0x3130
  1546. #define OSDSR_CTRL_MODE 0x3131
  1547. #define OSDSR_ABIC_HCOEF 0x3132
  1548. #define OSDSR_YBIC_HCOEF 0x3133
  1549. #define OSDSR_CBIC_HCOEF 0x3134
  1550. #define OSDSR_ABIC_VCOEF 0x3135
  1551. #define OSDSR_YBIC_VCOEF 0x3136
  1552. #define OSDSR_CBIC_VCOEF 0x3137
  1553. #define OSDSR_VAR_PARA 0x3138
  1554. #define OSDSR_CONST_PARA 0x3139
  1555. #define OSDSR_RKE_EXTWIN 0x313a
  1556. #define OSDSR_UK_GRAD2DDIAG_TH_RATE 0x313b
  1557. #define OSDSR_UK_GRAD2DDIAG_LIMIT 0x313c
  1558. #define OSDSR_UK_GRAD2DADJA_TH_RATE 0x313d
  1559. #define OSDSR_UK_GRAD2DADJA_LIMIT 0x313e
  1560. #define OSDSR_UK_BST_GAIN 0x313f
  1561. #define OSDSR_HVBLEND_TH 0x3140
  1562. #define OSDSR_DEMO_WIND_TB 0x3141
  1563. #define OSDSR_DEMO_WIND_LR 0x3142
  1564. #define OSDSR_INT_BLANK_NUM 0x3143
  1565. #define OSDSR_FRM_END_STAT 0x3144
  1566. #define OSDSR_ABIC_HCOEF0 0x3145
  1567. #define OSDSR_YBIC_HCOEF0 0x3146
  1568. #define OSDSR_CBIC_HCOEF0 0x3147
  1569. #define OSDSR_ABIC_VCOEF0 0x3148
  1570. #define OSDSR_YBIC_VCOEF0 0x3149
  1571. #define OSDSR_CBIC_VCOEF0 0x314a
  1572. /* osd afbcd on gxtvbb */
  1573. #define OSD1_AFBCD_ENABLE 0x31a0
  1574. #define OSD1_AFBCD_MODE 0x31a1
  1575. #define OSD1_AFBCD_SIZE_IN 0x31a2
  1576. #define OSD1_AFBCD_HDR_PTR 0x31a3
  1577. #define OSD1_AFBCD_FRAME_PTR 0x31a4
  1578. #define OSD1_AFBCD_CHROMA_PTR 0x31a5
  1579. #define OSD1_AFBCD_CONV_CTRL 0x31a6
  1580. #define OSD1_AFBCD_STATUS 0x31a8
  1581. #define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9
  1582. #define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa
  1583. /* add for gxm and 962e dv core2 */
  1584. #define DOLBY_CORE2A_SWAP_CTRL1 0x3434
  1585. #define DOLBY_CORE2A_SWAP_CTRL2 0x3435
  1586. /* osd afbc on g12a */
  1587. #define VPU_MAFBC_BLOCK_ID 0x3a00
  1588. #define VPU_MAFBC_IRQ_RAW_STATUS 0x3a01
  1589. #define VPU_MAFBC_IRQ_CLEAR 0x3a02
  1590. #define VPU_MAFBC_IRQ_MASK 0x3a03
  1591. #define VPU_MAFBC_IRQ_STATUS 0x3a04
  1592. #define VPU_MAFBC_COMMAND 0x3a05
  1593. #define VPU_MAFBC_STATUS 0x3a06
  1594. #define VPU_MAFBC_SURFACE_CFG 0x3a07
  1595. #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10
  1596. #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11
  1597. #define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12
  1598. #define VPU_MAFBC_BUFFER_WIDTH_S0 0x3a13
  1599. #define VPU_MAFBC_BUFFER_HEIGHT_S0 0x3a14
  1600. #define VPU_MAFBC_BOUNDING_BOX_X_START_S0 0x3a15
  1601. #define VPU_MAFBC_BOUNDING_BOX_X_END_S0 0x3a16
  1602. #define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 0x3a17
  1603. #define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 0x3a18
  1604. #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 0x3a19
  1605. #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 0x3a1a
  1606. #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 0x3a1b
  1607. #define VPU_MAFBC_PREFETCH_CFG_S0 0x3a1c
  1608. #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 0x3a30
  1609. #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 0x3a31
  1610. #define VPU_MAFBC_FORMAT_SPECIFIER_S1 0x3a32
  1611. #define VPU_MAFBC_BUFFER_WIDTH_S1 0x3a33
  1612. #define VPU_MAFBC_BUFFER_HEIGHT_S1 0x3a34
  1613. #define VPU_MAFBC_BOUNDING_BOX_X_START_S1 0x3a35
  1614. #define VPU_MAFBC_BOUNDING_BOX_X_END_S1 0x3a36
  1615. #define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 0x3a37
  1616. #define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 0x3a38
  1617. #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 0x3a39
  1618. #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 0x3a3a
  1619. #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 0x3a3b
  1620. #define VPU_MAFBC_PREFETCH_CFG_S1 0x3a3c
  1621. #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 0x3a50
  1622. #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 0x3a51
  1623. #define VPU_MAFBC_FORMAT_SPECIFIER_S2 0x3a52
  1624. #define VPU_MAFBC_BUFFER_WIDTH_S2 0x3a53
  1625. #define VPU_MAFBC_BUFFER_HEIGHT_S2 0x3a54
  1626. #define VPU_MAFBC_BOUNDING_BOX_X_START_S2 0x3a55
  1627. #define VPU_MAFBC_BOUNDING_BOX_X_END_S2 0x3a56
  1628. #define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 0x3a57
  1629. #define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 0x3a58
  1630. #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 0x3a59
  1631. #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 0x3a5a
  1632. #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 0x3a5b
  1633. #define VPU_MAFBC_PREFETCH_CFG_S2 0x3a5c
  1634. #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 0x3a70
  1635. #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 0x3a71
  1636. #define VPU_MAFBC_FORMAT_SPECIFIER_S3 0x3a72
  1637. #define VPU_MAFBC_BUFFER_WIDTH_S3 0x3a73
  1638. #define VPU_MAFBC_BUFFER_HEIGHT_S3 0x3a74
  1639. #define VPU_MAFBC_BOUNDING_BOX_X_START_S3 0x3a75
  1640. #define VPU_MAFBC_BOUNDING_BOX_X_END_S3 0x3a76
  1641. #define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 0x3a77
  1642. #define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 0x3a78
  1643. #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 0x3a79
  1644. #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 0x3a7a
  1645. #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 0x3a7b
  1646. #define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c
  1647. #define DOLBY_PATH_CTRL 0x1a0c
  1648. #define DOLBY_BYPASS_EN(val) (val & 0xf)
  1649. #define OSD_PATH_MISC_CTRL 0x1a0e
  1650. #define MALI_AFBCD_TOP_CTRL 0x1a0f
  1651. #define VIU_OSD_BLEND_CTRL 0x39b0
  1652. #define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4))
  1653. #define VIU_OSD_BLEND_DIN_EN(bits) ((bits & 0xf) << 20)
  1654. #define VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 BIT(24)
  1655. #define VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 BIT(25)
  1656. #define VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 BIT(26)
  1657. #define VIU_OSD_BLEND_BLEN2_PREMULT_EN(input) ((input & 0x3) << 27)
  1658. #define VIU_OSD_BLEND_HOLD_LINES(lines) ((u32)(lines & 0x7) << 29)
  1659. #define VIU_OSD_BLEND_CTRL1 0x39c0
  1660. #define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1
  1661. #define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2
  1662. #define VIU_OSD_BLEND_DIN1_SCOPE_H 0x39b3
  1663. #define VIU_OSD_BLEND_DIN1_SCOPE_V 0x39b4
  1664. #define VIU_OSD_BLEND_DIN2_SCOPE_H 0x39b5
  1665. #define VIU_OSD_BLEND_DIN2_SCOPE_V 0x39b6
  1666. #define VIU_OSD_BLEND_DIN3_SCOPE_H 0x39b7
  1667. #define VIU_OSD_BLEND_DIN3_SCOPE_V 0x39b8
  1668. #define VIU_OSD_BLEND_DUMMY_DATA0 0x39b9
  1669. #define VIU_OSD_BLEND_DUMMY_ALPHA 0x39ba
  1670. #define VIU_OSD_BLEND_BLEND0_SIZE 0x39bb
  1671. #define VIU_OSD_BLEND_BLEND1_SIZE 0x39bc
  1672. #define VIU_OSD_BLEND_RO_CURRENT_XY 0x39bf
  1673. #define VPP_OUT_H_V_SIZE 0x1da5
  1674. #define VPP_VD2_HDR_IN_SIZE 0x1df0
  1675. #define VPP_OSD1_IN_SIZE 0x1df1
  1676. #define VPP_GCLK_CTRL2 0x1df2
  1677. #define VD2_PPS_DUMMY_DATA 0x1df4
  1678. #define VPP_OSD1_BLD_H_SCOPE 0x1df5
  1679. #define VPP_OSD1_BLD_V_SCOPE 0x1df6
  1680. #define VPP_OSD2_BLD_H_SCOPE 0x1df7
  1681. #define VPP_OSD2_BLD_V_SCOPE 0x1df8
  1682. #define VPP_WRBAK_CTRL 0x1df9
  1683. #define VPP_SLEEP_CTRL 0x1dfa
  1684. #define VD1_BLEND_SRC_CTRL 0x1dfb
  1685. #define VD2_BLEND_SRC_CTRL 0x1dfc
  1686. #define VD_BLEND_PREBLD_SRC_VD1 (1 << 0)
  1687. #define VD_BLEND_PREBLD_SRC_VD2 (2 << 0)
  1688. #define VD_BLEND_PREBLD_SRC_OSD1 (3 << 0)
  1689. #define VD_BLEND_PREBLD_SRC_OSD2 (4 << 0)
  1690. #define VD_BLEND_PREBLD_PREMULT_EN BIT(4)
  1691. #define VD_BLEND_POSTBLD_SRC_VD1 (1 << 8)
  1692. #define VD_BLEND_POSTBLD_SRC_VD2 (2 << 8)
  1693. #define VD_BLEND_POSTBLD_SRC_OSD1 (3 << 8)
  1694. #define VD_BLEND_POSTBLD_SRC_OSD2 (4 << 8)
  1695. #define VD_BLEND_POSTBLD_PREMULT_EN BIT(16)
  1696. #define OSD1_BLEND_SRC_CTRL 0x1dfd
  1697. #define OSD2_BLEND_SRC_CTRL 0x1dfe
  1698. #define OSD_BLEND_POSTBLD_SRC_VD1 (1 << 8)
  1699. #define OSD_BLEND_POSTBLD_SRC_VD2 (2 << 8)
  1700. #define OSD_BLEND_POSTBLD_SRC_OSD1 (3 << 8)
  1701. #define OSD_BLEND_POSTBLD_SRC_OSD2 (4 << 8)
  1702. #define OSD_BLEND_PATH_SEL_ENABLE BIT(20)
  1703. #define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x3968
  1704. #define VPP_POST_BLEND_DUMMY_ALPHA 0x3969
  1705. #define VPP_RDARB_MODE 0x3978
  1706. #define VPP_RDARB_REQEN_SLV 0x3979
  1707. #endif /* __MESON_REGISTERS_H */