meson_dw_hdmi.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 BayLibre, SAS
  4. * Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <display.h>
  8. #include <dm.h>
  9. #include <edid.h>
  10. #include <log.h>
  11. #include <asm/io.h>
  12. #include <dw_hdmi.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/uclass-internal.h>
  15. #include <linux/bitops.h>
  16. #include <power/regulator.h>
  17. #include <clk.h>
  18. #include <linux/delay.h>
  19. #include <reset.h>
  20. #include <media_bus_format.h>
  21. #include "meson_dw_hdmi.h"
  22. #include "meson_vpu.h"
  23. /* TOP Block Communication Channel */
  24. #define HDMITX_TOP_ADDR_REG 0x0
  25. #define HDMITX_TOP_DATA_REG 0x4
  26. #define HDMITX_TOP_CTRL_REG 0x8
  27. #define HDMITX_TOP_G12A_OFFSET 0x8000
  28. /* Controller Communication Channel */
  29. #define HDMITX_DWC_ADDR_REG 0x10
  30. #define HDMITX_DWC_DATA_REG 0x14
  31. #define HDMITX_DWC_CTRL_REG 0x18
  32. /* HHI Registers */
  33. #define HHI_MEM_PD_REG0 0x100 /* 0x40 */
  34. #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
  35. #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
  36. #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
  37. #define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
  38. #define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
  39. #define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
  40. #define HHI_HDMI_PHY_CNTL5 0x3b4 /* 0xed */
  41. struct meson_dw_hdmi {
  42. struct udevice *dev;
  43. struct dw_hdmi hdmi;
  44. void __iomem *hhi_base;
  45. };
  46. enum hdmi_compatible {
  47. HDMI_COMPATIBLE_GXBB = 0,
  48. HDMI_COMPATIBLE_GXL = 1,
  49. HDMI_COMPATIBLE_GXM = 2,
  50. HDMI_COMPATIBLE_G12A = 3,
  51. };
  52. static inline bool meson_hdmi_is_compatible(struct meson_dw_hdmi *priv,
  53. enum hdmi_compatible family)
  54. {
  55. enum hdmi_compatible compat = dev_get_driver_data(priv->dev);
  56. return compat == family;
  57. }
  58. static unsigned int dw_hdmi_top_read(struct dw_hdmi *hdmi, unsigned int addr)
  59. {
  60. struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
  61. hdmi);
  62. unsigned int data;
  63. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
  64. return readl(hdmi->ioaddr +
  65. HDMITX_TOP_G12A_OFFSET + (addr << 2));
  66. /* ADDR must be written twice */
  67. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  68. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  69. /* Read needs a second DATA read */
  70. data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  71. data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  72. return data;
  73. }
  74. static inline void dw_hdmi_top_write(struct dw_hdmi *hdmi,
  75. unsigned int addr, unsigned int data)
  76. {
  77. struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
  78. hdmi);
  79. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
  80. writel(data, hdmi->ioaddr +
  81. HDMITX_TOP_G12A_OFFSET + (addr << 2));
  82. return;
  83. }
  84. /* ADDR must be written twice */
  85. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  86. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  87. /* Write needs single DATA write */
  88. writel(data, hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  89. }
  90. static inline void dw_hdmi_top_write_bits(struct dw_hdmi *hdmi,
  91. unsigned int addr,
  92. unsigned int mask,
  93. unsigned int val)
  94. {
  95. unsigned int data = dw_hdmi_top_read(hdmi, addr);
  96. data &= ~mask;
  97. data |= val;
  98. dw_hdmi_top_write(hdmi, addr, data);
  99. }
  100. static u8 dw_hdmi_dwc_read(struct dw_hdmi *hdmi, int addr)
  101. {
  102. unsigned int data;
  103. /* ADDR must be written twice */
  104. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  105. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  106. /* Read needs a second DATA read */
  107. data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);
  108. data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);
  109. return data;
  110. }
  111. static inline void dw_hdmi_dwc_write(struct dw_hdmi *hdmi, u8 data, int addr)
  112. {
  113. /* ADDR must be written twice */
  114. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  115. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  116. /* Write needs single DATA write */
  117. writel(data, hdmi->ioaddr + HDMITX_DWC_DATA_REG);
  118. }
  119. static inline void dw_hdmi_dwc_write_bits(struct dw_hdmi *hdmi,
  120. unsigned int addr,
  121. unsigned int mask,
  122. unsigned int val)
  123. {
  124. u8 data = dw_hdmi_dwc_read(hdmi, addr);
  125. data &= ~mask;
  126. data |= val;
  127. dw_hdmi_dwc_write(hdmi, data, addr);
  128. }
  129. static inline void dw_hdmi_hhi_write(struct meson_dw_hdmi *priv,
  130. unsigned int addr, unsigned int data)
  131. {
  132. hhi_write(addr, data);
  133. }
  134. __attribute__((unused))
  135. static unsigned int dw_hdmi_hhi_read(struct meson_dw_hdmi *priv,
  136. unsigned int addr)
  137. {
  138. return hhi_read(addr);
  139. }
  140. static inline void dw_hdmi_hhi_update_bits(struct meson_dw_hdmi *priv,
  141. unsigned int addr,
  142. unsigned int mask,
  143. unsigned int val)
  144. {
  145. hhi_update_bits(addr, mask, val);
  146. }
  147. static int meson_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  148. {
  149. #if defined DEBUG
  150. struct display_timing timing;
  151. int panel_bits_per_colour;
  152. #endif
  153. struct meson_dw_hdmi *priv = dev_get_priv(dev);
  154. int ret;
  155. ret = dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
  156. #if defined DEBUG
  157. if (!ret)
  158. return ret;
  159. edid_print_info((struct edid1_info *)buf);
  160. edid_get_timing(buf, ret, &timing, &panel_bits_per_colour);
  161. debug("Display timing:\n");
  162. debug(" hactive %04d, hfrontp %04d, hbackp %04d hsync %04d\n"
  163. " vactive %04d, vfrontp %04d, vbackp %04d vsync %04d\n",
  164. timing.hactive.typ, timing.hfront_porch.typ,
  165. timing.hback_porch.typ, timing.hsync_len.typ,
  166. timing.vactive.typ, timing.vfront_porch.typ,
  167. timing.vback_porch.typ, timing.vsync_len.typ);
  168. debug(" flags: ");
  169. if (timing.flags & DISPLAY_FLAGS_INTERLACED)
  170. debug("interlaced ");
  171. if (timing.flags & DISPLAY_FLAGS_DOUBLESCAN)
  172. debug("doublescan ");
  173. if (timing.flags & DISPLAY_FLAGS_DOUBLECLK)
  174. debug("doubleclk ");
  175. if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
  176. debug("hsync_low ");
  177. if (timing.flags & DISPLAY_FLAGS_HSYNC_HIGH)
  178. debug("hsync_high ");
  179. if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
  180. debug("vsync_low ");
  181. if (timing.flags & DISPLAY_FLAGS_VSYNC_HIGH)
  182. debug("vsync_high ");
  183. debug("\n");
  184. #endif
  185. return ret;
  186. }
  187. static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *priv)
  188. {
  189. /* Enable and software reset */
  190. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xf);
  191. mdelay(2);
  192. /* Enable and unreset */
  193. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xe);
  194. mdelay(2);
  195. }
  196. static void meson_dw_hdmi_phy_setup_mode(struct meson_dw_hdmi *priv,
  197. uint pixel_clock)
  198. {
  199. pixel_clock = pixel_clock / 1000;
  200. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXL) ||
  201. meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXM)) {
  202. if (pixel_clock >= 371250) {
  203. /* 5.94Gbps, 3.7125Gbps */
  204. hhi_write(HHI_HDMI_PHY_CNTL0, 0x333d3282);
  205. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2136315b);
  206. } else if (pixel_clock >= 297000) {
  207. /* 2.97Gbps */
  208. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33303382);
  209. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2036315b);
  210. } else if (pixel_clock >= 148500) {
  211. /* 1.485Gbps */
  212. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33303362);
  213. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2016315b);
  214. } else {
  215. /* 742.5Mbps, and below */
  216. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33604142);
  217. hhi_write(HHI_HDMI_PHY_CNTL3, 0x0016315b);
  218. }
  219. } else if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXBB)) {
  220. if (pixel_clock >= 371250) {
  221. /* 5.94Gbps, 3.7125Gbps */
  222. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33353245);
  223. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2100115b);
  224. } else if (pixel_clock >= 297000) {
  225. /* 2.97Gbps */
  226. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33634283);
  227. hhi_write(HHI_HDMI_PHY_CNTL3, 0xb000115b);
  228. } else {
  229. /* 1.485Gbps, and below */
  230. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33632122);
  231. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2000115b);
  232. }
  233. } else if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
  234. if (pixel_clock >= 371250) {
  235. /* 5.94Gbps, 3.7125Gbps */
  236. hhi_write(HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
  237. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
  238. hhi_write(HHI_HDMI_PHY_CNTL5, 0x0000080b);
  239. } else if (pixel_clock >= 297000) {
  240. /* 2.97Gbps */
  241. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33eb6262);
  242. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
  243. hhi_write(HHI_HDMI_PHY_CNTL5, 0x00000003);
  244. } else {
  245. /* 1.485Gbps, and below */
  246. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33eb4242);
  247. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
  248. hhi_write(HHI_HDMI_PHY_CNTL5, 0x00000003);
  249. }
  250. }
  251. }
  252. static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock)
  253. {
  254. struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
  255. hdmi);
  256. /* Enable clocks */
  257. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
  258. /* Bring HDMITX MEM output of power down */
  259. dw_hdmi_hhi_update_bits(priv, HHI_MEM_PD_REG0, 0xff << 8, 0);
  260. /* Bring out of reset */
  261. dw_hdmi_top_write(hdmi, HDMITX_TOP_SW_RESET, 0);
  262. /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
  263. dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3, 0x3);
  264. dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3 << 4, 0x3 << 4);
  265. /* Enable normal output to PHY */
  266. dw_hdmi_top_write(hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
  267. /* TMDS pattern setup (TOFIX pattern for 4k2k scrambling) */
  268. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);
  269. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);
  270. /* Load TMDS pattern */
  271. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
  272. mdelay(20);
  273. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
  274. /* Setup PHY parameters */
  275. meson_dw_hdmi_phy_setup_mode(priv, pixel_clock);
  276. /* Setup PHY */
  277. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
  278. 0xffff << 16, 0x0390 << 16);
  279. /* BIT_INVERT */
  280. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXL) ||
  281. meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXM) ||
  282. meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
  283. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, BIT(17), 0);
  284. else
  285. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
  286. BIT(17), BIT(17));
  287. /* Disable clock, fifo, fifo_wr */
  288. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0);
  289. mdelay(100);
  290. /* Reset PHY 3 times in a row */
  291. meson_dw_hdmi_phy_reset(priv);
  292. meson_dw_hdmi_phy_reset(priv);
  293. meson_dw_hdmi_phy_reset(priv);
  294. return 0;
  295. }
  296. static int meson_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
  297. const struct display_timing *edid)
  298. {
  299. struct meson_dw_hdmi *priv = dev_get_priv(dev);
  300. /* will back into meson_dw_hdmi_phy_init */
  301. return dw_hdmi_enable(&priv->hdmi, edid);
  302. }
  303. static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
  304. {
  305. int i;
  306. /* Poll 1 second for HPD signal */
  307. for (i = 0; i < 10; ++i) {
  308. if (dw_hdmi_top_read(hdmi, HDMITX_TOP_STAT0))
  309. return 0;
  310. mdelay(100);
  311. }
  312. return -ETIMEDOUT;
  313. }
  314. static int meson_dw_hdmi_probe(struct udevice *dev)
  315. {
  316. struct meson_dw_hdmi *priv = dev_get_priv(dev);
  317. struct reset_ctl_bulk resets;
  318. struct clk_bulk clocks;
  319. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  320. struct udevice *supply;
  321. #endif
  322. int ret;
  323. priv->dev = dev;
  324. priv->hdmi.ioaddr = (ulong)dev_remap_addr_index(dev, 0);
  325. if (!priv->hdmi.ioaddr)
  326. return -EINVAL;
  327. priv->hhi_base = dev_remap_addr_index(dev, 1);
  328. if (!priv->hhi_base)
  329. return -EINVAL;
  330. priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
  331. priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
  332. priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
  333. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
  334. priv->hdmi.reg_io_width = 1;
  335. else {
  336. priv->hdmi.write_reg = dw_hdmi_dwc_write;
  337. priv->hdmi.read_reg = dw_hdmi_dwc_read;
  338. }
  339. priv->hdmi.i2c_clk_high = 0x67;
  340. priv->hdmi.i2c_clk_low = 0x78;
  341. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  342. ret = device_get_supply_regulator(dev, "hdmi-supply", &supply);
  343. if (ret && ret != -ENOENT) {
  344. pr_err("Failed to get HDMI regulator\n");
  345. return ret;
  346. }
  347. if (!ret) {
  348. ret = regulator_set_enable(supply, true);
  349. if (ret)
  350. return ret;
  351. }
  352. #endif
  353. uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
  354. &priv->hdmi.ddc_bus);
  355. ret = reset_get_bulk(dev, &resets);
  356. if (ret)
  357. return ret;
  358. ret = clk_get_bulk(dev, &clocks);
  359. if (ret)
  360. return ret;
  361. ret = clk_enable_bulk(&clocks);
  362. if (ret)
  363. return ret;
  364. /* Enable clocks */
  365. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
  366. /* Bring HDMITX MEM output of power down */
  367. dw_hdmi_hhi_update_bits(priv, HHI_MEM_PD_REG0, 0xff << 8, 0);
  368. /* Reset HDMITX APB & TX & PHY: cycle needed for EDID */
  369. ret = reset_deassert_bulk(&resets);
  370. if (ret)
  371. return ret;
  372. ret = reset_assert_bulk(&resets);
  373. if (ret)
  374. return ret;
  375. ret = reset_deassert_bulk(&resets);
  376. if (ret)
  377. return ret;
  378. if (!meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
  379. /* Enable APB3 fail on error */
  380. writel_bits(BIT(15), BIT(15),
  381. priv->hdmi.ioaddr + HDMITX_TOP_CTRL_REG);
  382. writel_bits(BIT(15), BIT(15),
  383. priv->hdmi.ioaddr + HDMITX_DWC_CTRL_REG);
  384. }
  385. /* Bring out of reset */
  386. dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_SW_RESET, 0);
  387. mdelay(20);
  388. dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_CLK_CNTL, 0xff);
  389. dw_hdmi_init(&priv->hdmi);
  390. dw_hdmi_phy_init(&priv->hdmi);
  391. /* wait for connector */
  392. ret = meson_dw_hdmi_wait_hpd(&priv->hdmi);
  393. if (ret)
  394. debug("hdmi can not get hpd signal\n");
  395. return ret;
  396. }
  397. static bool meson_dw_hdmi_mode_valid(struct udevice *dev,
  398. const struct display_timing *timing)
  399. {
  400. return meson_venc_hdmi_supported_mode(timing);
  401. }
  402. static const struct dm_display_ops meson_dw_hdmi_ops = {
  403. .read_edid = meson_dw_hdmi_read_edid,
  404. .enable = meson_dw_hdmi_enable,
  405. .mode_valid = meson_dw_hdmi_mode_valid,
  406. };
  407. static const struct udevice_id meson_dw_hdmi_ids[] = {
  408. { .compatible = "amlogic,meson-gxbb-dw-hdmi",
  409. .data = HDMI_COMPATIBLE_GXBB },
  410. { .compatible = "amlogic,meson-gxl-dw-hdmi",
  411. .data = HDMI_COMPATIBLE_GXL },
  412. { .compatible = "amlogic,meson-gxm-dw-hdmi",
  413. .data = HDMI_COMPATIBLE_GXM },
  414. { .compatible = "amlogic,meson-g12a-dw-hdmi",
  415. .data = HDMI_COMPATIBLE_G12A },
  416. { }
  417. };
  418. U_BOOT_DRIVER(meson_dw_hdmi) = {
  419. .name = "meson_dw_hdmi",
  420. .id = UCLASS_DISPLAY,
  421. .of_match = meson_dw_hdmi_ids,
  422. .ops = &meson_dw_hdmi_ops,
  423. .probe = meson_dw_hdmi_probe,
  424. .priv_auto = sizeof(struct meson_dw_hdmi),
  425. };