logicore_dp_tx_regif.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * logicore_dp_tx_regif.h
  4. *
  5. * Register interface definition for XILINX LogiCore DisplayPort v6.1 TX
  6. * (Source) based on Xilinx dp_v3_1 driver sources
  7. *
  8. * (C) Copyright 2016
  9. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  10. */
  11. #ifndef __GDSYS_LOGICORE_DP_TX_REGIF_H__
  12. #define __GDSYS_LOGICORE_DP_TX_REGIF_H__
  13. enum {
  14. /* link configuration field */
  15. REG_LINK_BW_SET = 0x000,
  16. REG_LANE_COUNT_SET = 0x004,
  17. REG_ENHANCED_FRAME_EN = 0x008,
  18. REG_TRAINING_PATTERN_SET = 0x00C,
  19. REG_LINK_QUAL_PATTERN_SET = 0x010,
  20. REG_SCRAMBLING_DISABLE = 0x014,
  21. REG_DOWNSPREAD_CTRL = 0x018,
  22. REG_SOFT_RESET = 0x01C,
  23. };
  24. enum {
  25. /* core enables */
  26. REG_ENABLE = 0x080,
  27. REG_ENABLE_MAIN_STREAM = 0x084,
  28. REG_ENABLE_SEC_STREAM = 0x088,
  29. REG_FORCE_SCRAMBLER_RESET = 0x0C0,
  30. REG_MST_CONFIG = 0x0D0,
  31. REG_LINE_RESET_DISABLE = 0x0F0,
  32. };
  33. enum {
  34. /* core ID */
  35. REG_VERSION = 0x0F8,
  36. REG_CORE_ID = 0x0FC,
  37. };
  38. enum {
  39. /* AUX channel interface */
  40. REG_AUX_CMD = 0x100,
  41. REG_AUX_WRITE_FIFO = 0x104,
  42. REG_AUX_ADDRESS = 0x108,
  43. REG_AUX_CLK_DIVIDER = 0x10C,
  44. REG_USER_FIFO_OVERFLOW = 0x110,
  45. REG_INTERRUPT_SIG_STATE = 0x130,
  46. REG_AUX_REPLY_DATA = 0x134,
  47. REG_AUX_REPLY_CODE = 0x138,
  48. REG_AUX_REPLY_COUNT = 0x13C,
  49. REG_INTERRUPT_STATUS = 0x140,
  50. REG_INTERRUPT_MASK = 0x144,
  51. REG_REPLY_DATA_COUNT = 0x148,
  52. REG_REPLY_STATUS = 0x14C,
  53. REG_HPD_DURATION = 0x150,
  54. };
  55. enum {
  56. /* main stream attributes for SST / MST STREAM1 */
  57. REG_STREAM1_MSA_START = 0x180,
  58. REG_MAIN_STREAM_HTOTAL = 0x180,
  59. REG_MAIN_STREAM_VTOTAL = 0x184,
  60. REG_MAIN_STREAM_POLARITY = 0x188,
  61. REG_MAIN_STREAM_HSWIDTH = 0x18C,
  62. REG_MAIN_STREAM_VSWIDTH = 0x190,
  63. REG_MAIN_STREAM_HRES = 0x194,
  64. REG_MAIN_STREAM_VRES = 0x198,
  65. REG_MAIN_STREAM_HSTART = 0x19C,
  66. REG_MAIN_STREAM_VSTART = 0x1A0,
  67. REG_MAIN_STREAM_MISC0 = 0x1A4,
  68. REG_MAIN_STREAM_MISC1 = 0x1A8,
  69. REG_M_VID = 0x1AC,
  70. REG_TU_SIZE = 0x1B0,
  71. REG_N_VID = 0x1B4,
  72. REG_USER_PIXEL_WIDTH = 0x1B8,
  73. REG_USER_DATA_COUNT_PER_LANE = 0x1BC,
  74. REG_MAIN_STREAM_INTERLACED = 0x1C0,
  75. REG_MIN_BYTES_PER_TU = 0x1C4,
  76. REG_FRAC_BYTES_PER_TU = 0x1C8,
  77. REG_INIT_WAIT = 0x1CC,
  78. REG_STREAM1 = 0x1D0,
  79. REG_STREAM2 = 0x1D4,
  80. REG_STREAM3 = 0x1D8,
  81. REG_STREAM4 = 0x1DC,
  82. };
  83. enum {
  84. /* PHY configuration status */
  85. REG_PHY_CONFIG = 0x200,
  86. REG_PHY_VOLTAGE_DIFF_LANE_0 = 0x220,
  87. REG_PHY_VOLTAGE_DIFF_LANE_1 = 0x224,
  88. REG_PHY_VOLTAGE_DIFF_LANE_2 = 0x228,
  89. REG_PHY_VOLTAGE_DIFF_LANE_3 = 0x22C,
  90. REG_PHY_TRANSMIT_PRBS7 = 0x230,
  91. REG_PHY_CLOCK_SELECT = 0x234,
  92. REG_PHY_POWER_DOWN = 0x238,
  93. REG_PHY_PRECURSOR_LANE_0 = 0x23C,
  94. REG_PHY_PRECURSOR_LANE_1 = 0x240,
  95. REG_PHY_PRECURSOR_LANE_2 = 0x244,
  96. REG_PHY_PRECURSOR_LANE_3 = 0x248,
  97. REG_PHY_POSTCURSOR_LANE_0 = 0x24C,
  98. REG_PHY_POSTCURSOR_LANE_1 = 0x250,
  99. REG_PHY_POSTCURSOR_LANE_2 = 0x254,
  100. REG_PHY_POSTCURSOR_LANE_3 = 0x258,
  101. REG_PHY_STATUS = 0x280,
  102. REG_GT_DRP_COMMAND = 0x2A0,
  103. REG_GT_DRP_READ_DATA = 0x2A4,
  104. REG_GT_DRP_CHANNEL_STATUS = 0x2A8,
  105. };
  106. enum {
  107. /* DisplayPort audio */
  108. REG_AUDIO_CONTROL = 0x300,
  109. REG_AUDIO_CHANNELS = 0x304,
  110. REG_AUDIO_INFO_DATA = 0x308,
  111. REG_AUDIO_MAUD = 0x328,
  112. REG_AUDIO_NAUD = 0x32C,
  113. REG_AUDIO_EXT_DATA = 0x330,
  114. };
  115. enum {
  116. /* HDCP */
  117. REG_HDCP_ENABLE = 0x400,
  118. };
  119. enum {
  120. /* main stream attributes for MST STREAM2, 3, and 4 */
  121. REG_STREAM2_MSA_START = 0x500,
  122. REG_STREAM3_MSA_START = 0x550,
  123. REG_STREAM4_MSA_START = 0x5A0,
  124. REG_VC_PAYLOAD_BUFFER_ADDR = 0x800,
  125. };
  126. enum {
  127. LINK_BW_SET_162GBPS = 0x06,
  128. LINK_BW_SET_270GBPS = 0x0A,
  129. LINK_BW_SET_540GBPS = 0x14,
  130. };
  131. enum {
  132. LANE_COUNT_SET_1 = 0x1,
  133. LANE_COUNT_SET_2 = 0x2,
  134. LANE_COUNT_SET_4 = 0x4,
  135. };
  136. enum {
  137. TRAINING_PATTERN_SET_OFF = 0x0,
  138. /* training pattern 1 used for clock recovery */
  139. TRAINING_PATTERN_SET_TP1 = 0x1,
  140. /* training pattern 2 used for channel equalization */
  141. TRAINING_PATTERN_SET_TP2 = 0x2,
  142. /*
  143. * training pattern 3 used for channel equalization for cores with DP
  144. * v1.2
  145. */
  146. TRAINING_PATTERN_SET_TP3 = 0x3,
  147. };
  148. enum {
  149. LINK_QUAL_PATTERN_SET_OFF = 0x0,
  150. /* D10.2 unscrambled test pattern transmitted */
  151. LINK_QUAL_PATTERN_SET_D102_TEST = 0x1,
  152. /* symbol error rate measurement pattern transmitted */
  153. LINK_QUAL_PATTERN_SET_SER_MES = 0x2,
  154. /* pseudo random bit sequence 7 transmitted */
  155. LINK_QUAL_PATTERN_SET_PRBS7 = 0x3,
  156. };
  157. enum {
  158. SOFT_RESET_VIDEO_STREAM1_MASK = 0x00000001,
  159. SOFT_RESET_VIDEO_STREAM2_MASK = 0x00000002,
  160. SOFT_RESET_VIDEO_STREAM3_MASK = 0x00000004,
  161. SOFT_RESET_VIDEO_STREAM4_MASK = 0x00000008,
  162. SOFT_RESET_AUX_MASK = 0x00000080,
  163. SOFT_RESET_VIDEO_STREAM_ALL_MASK = 0x0000000F,
  164. };
  165. enum {
  166. MST_CONFIG_MST_EN_MASK = 0x00000001,
  167. };
  168. enum {
  169. LINE_RESET_DISABLE_MASK = 0x1,
  170. };
  171. #define AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F
  172. #define AUX_CMD_SHIFT 8
  173. #define AUX_CMD_MASK 0x00000F00
  174. enum {
  175. AUX_CMD_I2C_WRITE = 0x0,
  176. AUX_CMD_I2C_READ = 0x1,
  177. AUX_CMD_I2C_WRITE_STATUS = 0x2,
  178. AUX_CMD_I2C_WRITE_MOT = 0x4,
  179. AUX_CMD_I2C_READ_MOT = 0x5,
  180. AUX_CMD_I2C_WRITE_STATUS_MOT = 0x6,
  181. AUX_CMD_WRITE = 0x8,
  182. AUX_CMD_READ = 0x9,
  183. };
  184. #define AUX_CLK_DIVIDER_VAL_MASK 0x00FF
  185. #define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8
  186. #define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00
  187. enum {
  188. INTERRUPT_SIG_STATE_HPD_STATE_MASK = 0x00000001,
  189. INTERRUPT_SIG_STATE_REQUEST_STATE_MASK = 0x00000002,
  190. INTERRUPT_SIG_STATE_REPLY_STATE_MASK = 0x00000004,
  191. INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK = 0x00000008,
  192. };
  193. enum {
  194. AUX_REPLY_CODE_ACK = 0x0,
  195. AUX_REPLY_CODE_I2C_ACK = 0x0,
  196. AUX_REPLY_CODE_NACK = 0x1,
  197. AUX_REPLY_CODE_DEFER = 0x2,
  198. AUX_REPLY_CODE_I2C_NACK = 0x4,
  199. AUX_REPLY_CODE_I2C_DEFER = 0x8,
  200. };
  201. enum {
  202. INTERRUPT_STATUS_HPD_IRQ_MASK = 0x00000001,
  203. INTERRUPT_STATUS_HPD_EVENT_MASK = 0x00000002,
  204. INTERRUPT_STATUS_REPLY_RECEIVED_MASK = 0x00000004,
  205. INTERRUPT_STATUS_REPLY_TIMEOUT_MASK = 0x00000008,
  206. INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK = 0x00000010,
  207. INTERRUPT_STATUS_EXT_PKT_TXD_MASK = 0x00000020,
  208. };
  209. enum {
  210. INTERRUPT_MASK_HPD_IRQ_MASK = 0x00000001,
  211. INTERRUPT_MASK_HPD_EVENT_MASK = 0x00000002,
  212. INTERRUPT_MASK_REPLY_RECEIVED_MASK = 0x00000004,
  213. INTERRUPT_MASK_REPLY_TIMEOUT_MASK = 0x00000008,
  214. INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK = 0x00000010,
  215. INTERRUPT_MASK_EXT_PKT_TXD_MASK = 0x00000020,
  216. };
  217. #define REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4
  218. #define REPLY_STATUS_REPLY_STATUS_STATE_MASK 0x00000FF0
  219. enum {
  220. REPLY_STATUS_REPLY_RECEIVED_MASK = 0x00000001,
  221. REPLY_STATUS_REPLY_IN_PROGRESS_MASK = 0x00000002,
  222. REPLY_STATUS_REQUEST_IN_PROGRESS_MASK = 0x00000004,
  223. REPLY_STATUS_REPLY_ERROR_MASK = 0x00000008,
  224. };
  225. #define MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1
  226. enum {
  227. MAIN_STREAMX_POLARITY_HSYNC_POL_MASK = 0x00000001,
  228. MAIN_STREAMX_POLARITY_VSYNC_POL_MASK = 0x00000002,
  229. };
  230. enum {
  231. MAIN_STREAMX_MISC0_SYNC_CLK_MASK = 0x00000001,
  232. };
  233. #define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1
  234. #define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006
  235. enum {
  236. MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB = 0x0,
  237. MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 = 0x1,
  238. MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 = 0x2,
  239. };
  240. #define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3
  241. #define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008
  242. #define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4
  243. #define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010
  244. #define MAIN_STREAMX_MISC0_BDC_SHIFT 5
  245. #define MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0
  246. enum {
  247. MAIN_STREAMX_MISC0_BDC_6BPC = 0x0,
  248. MAIN_STREAMX_MISC0_BDC_8BPC = 0x1,
  249. MAIN_STREAMX_MISC0_BDC_10BPC = 0x2,
  250. MAIN_STREAMX_MISC0_BDC_12BPC = 0x3,
  251. MAIN_STREAMX_MISC0_BDC_16BPC = 0x4,
  252. };
  253. enum {
  254. PHY_CONFIG_PHY_RESET_ENABLE_MASK = 0x0000000,
  255. PHY_CONFIG_PHY_RESET_MASK = 0x0000001,
  256. PHY_CONFIG_GTTX_RESET_MASK = 0x0000002,
  257. PHY_CONFIG_GT_ALL_RESET_MASK = 0x0000003,
  258. PHY_CONFIG_TX_PHY_PMA_RESET_MASK = 0x0000100,
  259. PHY_CONFIG_TX_PHY_PCS_RESET_MASK = 0x0000200,
  260. PHY_CONFIG_TX_PHY_POLARITY_MASK = 0x0000800,
  261. PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK = 0x0001000,
  262. PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK = 0x0010000,
  263. PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK = 0x0020000,
  264. PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK = 0x0040000,
  265. PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK = 0x0080000,
  266. PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK = 0x0100000,
  267. PHY_CONFIG_TX_PHY_8B10BEN_MASK = 0x0200000,
  268. };
  269. #define PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13
  270. #define PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x000E000
  271. enum {
  272. PHY_CLOCK_SELECT_162GBPS = 0x1,
  273. PHY_CLOCK_SELECT_270GBPS = 0x3,
  274. PHY_CLOCK_SELECT_540GBPS = 0x5,
  275. };
  276. enum {
  277. VS_LEVEL_0 = 0x2,
  278. VS_LEVEL_1 = 0x5,
  279. VS_LEVEL_2 = 0x8,
  280. VS_LEVEL_3 = 0xF,
  281. VS_LEVEL_OFFSET = 0x4,
  282. };
  283. enum {
  284. PE_LEVEL_0 = 0x00,
  285. PE_LEVEL_1 = 0x0E,
  286. PE_LEVEL_2 = 0x14,
  287. PE_LEVEL_3 = 0x1B,
  288. };
  289. enum {
  290. PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT = 2,
  291. PHY_STATUS_TX_ERROR_LANE_0_SHIFT = 18,
  292. PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT = 20,
  293. PHY_STATUS_TX_ERROR_LANE_1_SHIFT = 22,
  294. PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT = 16,
  295. PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT = 24,
  296. PHY_STATUS_TX_ERROR_LANE_2_SHIFT = 26,
  297. PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT = 28,
  298. PHY_STATUS_TX_ERROR_LANE_3_SHIFT = 30,
  299. };
  300. enum {
  301. PHY_STATUS_RESET_LANE_0_DONE_MASK = 0x00000001,
  302. PHY_STATUS_RESET_LANE_1_DONE_MASK = 0x00000002,
  303. PHY_STATUS_RESET_LANE_2_3_DONE_MASK = 0x0000000C,
  304. PHY_STATUS_PLL_LANE0_1_LOCK_MASK = 0x00000010,
  305. PHY_STATUS_PLL_LANE2_3_LOCK_MASK = 0x00000020,
  306. PHY_STATUS_PLL_FABRIC_LOCK_MASK = 0x00000040,
  307. PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK = 0x00030000,
  308. PHY_STATUS_TX_ERROR_LANE_0_MASK = 0x000C0000,
  309. PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK = 0x00300000,
  310. PHY_STATUS_TX_ERROR_LANE_1_MASK = 0x00C00000,
  311. PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK = 0x03000000,
  312. PHY_STATUS_TX_ERROR_LANE_2_MASK = 0x0C000000,
  313. PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK = 0x30000000,
  314. PHY_STATUS_TX_ERROR_LANE_3_MASK = 0xC0000000,
  315. };
  316. #define PHY_STATUS_LANE_0_READY_MASK \
  317. (PHY_STATUS_RESET_LANE_0_DONE_MASK | \
  318. PHY_STATUS_PLL_LANE0_1_LOCK_MASK)
  319. #define PHY_STATUS_LANES_0_1_READY_MASK \
  320. (PHY_STATUS_LANE_0_READY_MASK | \
  321. PHY_STATUS_RESET_LANE_1_DONE_MASK)
  322. /*
  323. * PHY_STATUS_ALL_LANES_READY_MASK seems to be missing lanes 0 and 1 in
  324. * Xilinx dp_v3_0 implementation
  325. */
  326. #define PHY_STATUS_ALL_LANES_READY_MASK \
  327. (PHY_STATUS_LANES_0_1_READY_MASK | \
  328. PHY_STATUS_RESET_LANE_2_3_DONE_MASK | \
  329. PHY_STATUS_PLL_LANE2_3_LOCK_MASK)
  330. /**
  331. * phy_status_lanes_ready_mask() - Generate phy status ready mask
  332. * @lane_count: Number of lanes for which to generate a mask
  333. *
  334. * Return: The generated phy status ready mask
  335. */
  336. static inline u32 phy_status_lanes_ready_mask(u8 lane_count)
  337. {
  338. if (lane_count > 2)
  339. return PHY_STATUS_ALL_LANES_READY_MASK;
  340. if (lane_count == 2)
  341. return PHY_STATUS_LANES_0_1_READY_MASK;
  342. return PHY_STATUS_LANE_0_READY_MASK;
  343. }
  344. #define GT_DRP_COMMAND_DRP_ADDR_MASK 0x000F
  345. #define GT_DRP_COMMAND_DRP_RW_CMD_MASK 0x0080
  346. #define GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16
  347. #define GT_DRP_COMMAND_DRP_W_DATA_MASK 0xFF00
  348. #define HDCP_ENABLE_BYPASS_DISABLE_MASK 0x0001
  349. #endif /* __GDSYS_LOGICORE_DP_TX_REGIF_H__ */