logicore_dp_tx.h 1.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * logicore_dp_tx.h
  4. *
  5. * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source)
  6. *
  7. * (C) Copyright 2016
  8. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  9. */
  10. #ifndef __GDSYS_LOGICORE_DP_TX_H__
  11. #define __GDSYS_LOGICORE_DP_TX_H__
  12. /*
  13. * struct logicore_dp_tx_msa - Main Stream Attributes (MSA)
  14. * @pixel_clock_hz: The pixel clock of the stream (in Hz)
  15. * @bits_per_color: Number of bits per color component
  16. * @h_active: Horizontal active resolution (pixels)
  17. * @h_start: Horizontal blank start (in pixels)
  18. * @h_sync_polarity: Horizontal sync polarity
  19. * (0 = negative | 1 = positive)
  20. * @h_sync_width: Horizontal sync width (pixels)
  21. * @h_total: Horizontal total (pixels)
  22. * @v_active: Vertical active resolution (lines)
  23. * @v_start: Vertical blank start (in lines).
  24. * @v_sync_polarity: Vertical sync polarity
  25. * (0 = negative | 1 = positive)
  26. * @v_sync_width: Vertical sync width (lines)
  27. * @v_total: Vertical total (lines)
  28. * @override_user_pixel_width: If true, the value stored for user_pixel_width
  29. * will be used as the pixel width.
  30. * @user_pixel_width: The width of the user data input port.
  31. *
  32. * This is a stripped down version of struct main_stream_attributes that
  33. * contains only the parameters that are not set by cfg_msa_recalculate()
  34. */
  35. struct logicore_dp_tx_msa {
  36. u32 pixel_clock_hz;
  37. u32 bits_per_color;
  38. u16 h_active;
  39. u32 h_start;
  40. bool h_sync_polarity;
  41. u16 h_sync_width;
  42. u16 h_total;
  43. u16 v_active;
  44. u32 v_start;
  45. bool v_sync_polarity;
  46. u16 v_sync_width;
  47. u16 v_total;
  48. bool override_user_pixel_width;
  49. u32 user_pixel_width;
  50. };
  51. #endif /* __GDSYS_LOGICORE_DP_TX_H__ */