ivybridge_igd.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <bios_emul.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <fdtdec.h>
  10. #include <log.h>
  11. #include <pci_rom.h>
  12. #include <vbe.h>
  13. #include <video.h>
  14. #include <asm/global_data.h>
  15. #include <asm/intel_regs.h>
  16. #include <asm/io.h>
  17. #include <asm/mtrr.h>
  18. #include <asm/pci.h>
  19. #include <asm/arch/pch.h>
  20. #include <asm/arch/sandybridge.h>
  21. #include <linux/delay.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. struct gt_powermeter {
  24. u16 reg;
  25. u32 value;
  26. };
  27. /* These are magic values - unfortunately the meaning is unknown */
  28. static const struct gt_powermeter snb_pm_gt1[] = {
  29. { 0xa200, 0xcc000000 },
  30. { 0xa204, 0x07000040 },
  31. { 0xa208, 0x0000fe00 },
  32. { 0xa20c, 0x00000000 },
  33. { 0xa210, 0x17000000 },
  34. { 0xa214, 0x00000021 },
  35. { 0xa218, 0x0817fe19 },
  36. { 0xa21c, 0x00000000 },
  37. { 0xa220, 0x00000000 },
  38. { 0xa224, 0xcc000000 },
  39. { 0xa228, 0x07000040 },
  40. { 0xa22c, 0x0000fe00 },
  41. { 0xa230, 0x00000000 },
  42. { 0xa234, 0x17000000 },
  43. { 0xa238, 0x00000021 },
  44. { 0xa23c, 0x0817fe19 },
  45. { 0xa240, 0x00000000 },
  46. { 0xa244, 0x00000000 },
  47. { 0xa248, 0x8000421e },
  48. { 0 }
  49. };
  50. static const struct gt_powermeter snb_pm_gt2[] = {
  51. { 0xa200, 0x330000a6 },
  52. { 0xa204, 0x402d0031 },
  53. { 0xa208, 0x00165f83 },
  54. { 0xa20c, 0xf1000000 },
  55. { 0xa210, 0x00000000 },
  56. { 0xa214, 0x00160016 },
  57. { 0xa218, 0x002a002b },
  58. { 0xa21c, 0x00000000 },
  59. { 0xa220, 0x00000000 },
  60. { 0xa224, 0x330000a6 },
  61. { 0xa228, 0x402d0031 },
  62. { 0xa22c, 0x00165f83 },
  63. { 0xa230, 0xf1000000 },
  64. { 0xa234, 0x00000000 },
  65. { 0xa238, 0x00160016 },
  66. { 0xa23c, 0x002a002b },
  67. { 0xa240, 0x00000000 },
  68. { 0xa244, 0x00000000 },
  69. { 0xa248, 0x8000421e },
  70. { 0 }
  71. };
  72. static const struct gt_powermeter ivb_pm_gt1[] = {
  73. { 0xa800, 0x00000000 },
  74. { 0xa804, 0x00021c00 },
  75. { 0xa808, 0x00000403 },
  76. { 0xa80c, 0x02001700 },
  77. { 0xa810, 0x05000200 },
  78. { 0xa814, 0x00000000 },
  79. { 0xa818, 0x00690500 },
  80. { 0xa81c, 0x0000007f },
  81. { 0xa820, 0x01002501 },
  82. { 0xa824, 0x00000300 },
  83. { 0xa828, 0x01000331 },
  84. { 0xa82c, 0x0000000c },
  85. { 0xa830, 0x00010016 },
  86. { 0xa834, 0x01100101 },
  87. { 0xa838, 0x00010103 },
  88. { 0xa83c, 0x00041300 },
  89. { 0xa840, 0x00000b30 },
  90. { 0xa844, 0x00000000 },
  91. { 0xa848, 0x7f000000 },
  92. { 0xa84c, 0x05000008 },
  93. { 0xa850, 0x00000001 },
  94. { 0xa854, 0x00000004 },
  95. { 0xa858, 0x00000007 },
  96. { 0xa85c, 0x00000000 },
  97. { 0xa860, 0x00010000 },
  98. { 0xa248, 0x0000221e },
  99. { 0xa900, 0x00000000 },
  100. { 0xa904, 0x00001c00 },
  101. { 0xa908, 0x00000000 },
  102. { 0xa90c, 0x06000000 },
  103. { 0xa910, 0x09000200 },
  104. { 0xa914, 0x00000000 },
  105. { 0xa918, 0x00590000 },
  106. { 0xa91c, 0x00000000 },
  107. { 0xa920, 0x04002501 },
  108. { 0xa924, 0x00000100 },
  109. { 0xa928, 0x03000410 },
  110. { 0xa92c, 0x00000000 },
  111. { 0xa930, 0x00020000 },
  112. { 0xa934, 0x02070106 },
  113. { 0xa938, 0x00010100 },
  114. { 0xa93c, 0x00401c00 },
  115. { 0xa940, 0x00000000 },
  116. { 0xa944, 0x00000000 },
  117. { 0xa948, 0x10000e00 },
  118. { 0xa94c, 0x02000004 },
  119. { 0xa950, 0x00000001 },
  120. { 0xa954, 0x00000004 },
  121. { 0xa960, 0x00060000 },
  122. { 0xaa3c, 0x00001c00 },
  123. { 0xaa54, 0x00000004 },
  124. { 0xaa60, 0x00060000 },
  125. { 0 }
  126. };
  127. static const struct gt_powermeter ivb_pm_gt2_17w[] = {
  128. { 0xa800, 0x20000000 },
  129. { 0xa804, 0x000e3800 },
  130. { 0xa808, 0x00000806 },
  131. { 0xa80c, 0x0c002f00 },
  132. { 0xa810, 0x0c000800 },
  133. { 0xa814, 0x00000000 },
  134. { 0xa818, 0x00d20d00 },
  135. { 0xa81c, 0x000000ff },
  136. { 0xa820, 0x03004b02 },
  137. { 0xa824, 0x00000600 },
  138. { 0xa828, 0x07000773 },
  139. { 0xa82c, 0x00000000 },
  140. { 0xa830, 0x00020032 },
  141. { 0xa834, 0x1520040d },
  142. { 0xa838, 0x00020105 },
  143. { 0xa83c, 0x00083700 },
  144. { 0xa840, 0x000016ff },
  145. { 0xa844, 0x00000000 },
  146. { 0xa848, 0xff000000 },
  147. { 0xa84c, 0x0a000010 },
  148. { 0xa850, 0x00000002 },
  149. { 0xa854, 0x00000008 },
  150. { 0xa858, 0x0000000f },
  151. { 0xa85c, 0x00000000 },
  152. { 0xa860, 0x00020000 },
  153. { 0xa248, 0x0000221e },
  154. { 0xa900, 0x00000000 },
  155. { 0xa904, 0x00003800 },
  156. { 0xa908, 0x00000000 },
  157. { 0xa90c, 0x0c000000 },
  158. { 0xa910, 0x12000800 },
  159. { 0xa914, 0x00000000 },
  160. { 0xa918, 0x00b20000 },
  161. { 0xa91c, 0x00000000 },
  162. { 0xa920, 0x08004b02 },
  163. { 0xa924, 0x00000300 },
  164. { 0xa928, 0x01000820 },
  165. { 0xa92c, 0x00000000 },
  166. { 0xa930, 0x00030000 },
  167. { 0xa934, 0x15150406 },
  168. { 0xa938, 0x00020300 },
  169. { 0xa93c, 0x00903900 },
  170. { 0xa940, 0x00000000 },
  171. { 0xa944, 0x00000000 },
  172. { 0xa948, 0x20001b00 },
  173. { 0xa94c, 0x0a000010 },
  174. { 0xa950, 0x00000000 },
  175. { 0xa954, 0x00000008 },
  176. { 0xa960, 0x00110000 },
  177. { 0xaa3c, 0x00003900 },
  178. { 0xaa54, 0x00000008 },
  179. { 0xaa60, 0x00110000 },
  180. { 0 }
  181. };
  182. static const struct gt_powermeter ivb_pm_gt2_35w[] = {
  183. { 0xa800, 0x00000000 },
  184. { 0xa804, 0x00030400 },
  185. { 0xa808, 0x00000806 },
  186. { 0xa80c, 0x0c002f00 },
  187. { 0xa810, 0x0c000300 },
  188. { 0xa814, 0x00000000 },
  189. { 0xa818, 0x00d20d00 },
  190. { 0xa81c, 0x000000ff },
  191. { 0xa820, 0x03004b02 },
  192. { 0xa824, 0x00000600 },
  193. { 0xa828, 0x07000773 },
  194. { 0xa82c, 0x00000000 },
  195. { 0xa830, 0x00020032 },
  196. { 0xa834, 0x1520040d },
  197. { 0xa838, 0x00020105 },
  198. { 0xa83c, 0x00083700 },
  199. { 0xa840, 0x000016ff },
  200. { 0xa844, 0x00000000 },
  201. { 0xa848, 0xff000000 },
  202. { 0xa84c, 0x0a000010 },
  203. { 0xa850, 0x00000001 },
  204. { 0xa854, 0x00000008 },
  205. { 0xa858, 0x00000008 },
  206. { 0xa85c, 0x00000000 },
  207. { 0xa860, 0x00020000 },
  208. { 0xa248, 0x0000221e },
  209. { 0xa900, 0x00000000 },
  210. { 0xa904, 0x00003800 },
  211. { 0xa908, 0x00000000 },
  212. { 0xa90c, 0x0c000000 },
  213. { 0xa910, 0x12000800 },
  214. { 0xa914, 0x00000000 },
  215. { 0xa918, 0x00b20000 },
  216. { 0xa91c, 0x00000000 },
  217. { 0xa920, 0x08004b02 },
  218. { 0xa924, 0x00000300 },
  219. { 0xa928, 0x01000820 },
  220. { 0xa92c, 0x00000000 },
  221. { 0xa930, 0x00030000 },
  222. { 0xa934, 0x15150406 },
  223. { 0xa938, 0x00020300 },
  224. { 0xa93c, 0x00903900 },
  225. { 0xa940, 0x00000000 },
  226. { 0xa944, 0x00000000 },
  227. { 0xa948, 0x20001b00 },
  228. { 0xa94c, 0x0a000010 },
  229. { 0xa950, 0x00000000 },
  230. { 0xa954, 0x00000008 },
  231. { 0xa960, 0x00110000 },
  232. { 0xaa3c, 0x00003900 },
  233. { 0xaa54, 0x00000008 },
  234. { 0xaa60, 0x00110000 },
  235. { 0 }
  236. };
  237. static inline u32 gtt_read(void *bar, u32 reg)
  238. {
  239. return readl(bar + reg);
  240. }
  241. static inline void gtt_write(void *bar, u32 reg, u32 data)
  242. {
  243. writel(data, bar + reg);
  244. }
  245. static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
  246. {
  247. for (; pm && pm->reg; pm++)
  248. gtt_write(bar, pm->reg, pm->value);
  249. }
  250. #define GTT_RETRY 1000
  251. static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
  252. {
  253. unsigned try = GTT_RETRY;
  254. u32 data;
  255. while (try--) {
  256. data = gtt_read(bar, reg);
  257. if ((data & mask) == value)
  258. return 1;
  259. udelay(10);
  260. }
  261. printf("GT init timeout\n");
  262. return 0;
  263. }
  264. static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
  265. {
  266. u32 reg32;
  267. debug("GT Power Management Init, silicon = %#x\n", rev);
  268. if (rev < IVB_STEP_C0) {
  269. /* 1: Enable force wake */
  270. gtt_write(gtt_bar, 0xa18c, 0x00000001);
  271. gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
  272. } else {
  273. gtt_write(gtt_bar, 0xa180, 1 << 5);
  274. gtt_write(gtt_bar, 0xa188, 0xffff0001);
  275. gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
  276. }
  277. if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
  278. /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
  279. reg32 = gtt_read(gtt_bar, 0x42004);
  280. reg32 |= (1 << 14) | (1 << 15);
  281. gtt_write(gtt_bar, 0x42004, reg32);
  282. }
  283. if (rev >= IVB_STEP_A0) {
  284. /* Display Reset Acknowledge Settings */
  285. reg32 = gtt_read(gtt_bar, 0x45010);
  286. reg32 |= (1 << 1) | (1 << 0);
  287. gtt_write(gtt_bar, 0x45010, reg32);
  288. }
  289. /* 2: Get GT SKU from GTT+0x911c[13] */
  290. reg32 = gtt_read(gtt_bar, 0x911c);
  291. if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
  292. if (reg32 & (1 << 13)) {
  293. debug("SNB GT1 Power Meter Weights\n");
  294. gtt_write_powermeter(gtt_bar, snb_pm_gt1);
  295. } else {
  296. debug("SNB GT2 Power Meter Weights\n");
  297. gtt_write_powermeter(gtt_bar, snb_pm_gt2);
  298. }
  299. } else {
  300. u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
  301. if (reg32 & (1 << 13)) {
  302. /* GT1 SKU */
  303. debug("IVB GT1 Power Meter Weights\n");
  304. gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
  305. } else {
  306. /* GT2 SKU */
  307. u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
  308. tdp /= (1 << unit);
  309. if (tdp <= 17) {
  310. /* <=17W ULV */
  311. debug("IVB GT2 17W Power Meter Weights\n");
  312. gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
  313. } else if ((tdp >= 25) && (tdp <= 35)) {
  314. /* 25W-35W */
  315. debug("IVB GT2 25W-35W Power Meter Weights\n");
  316. gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
  317. } else {
  318. /* All others */
  319. debug("IVB GT2 35W Power Meter Weights\n");
  320. gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
  321. }
  322. }
  323. }
  324. /* 3: Gear ratio map */
  325. gtt_write(gtt_bar, 0xa004, 0x00000010);
  326. /* 4: GFXPAUSE */
  327. gtt_write(gtt_bar, 0xa000, 0x00070020);
  328. /* 5: Dynamic EU trip control */
  329. gtt_write(gtt_bar, 0xa080, 0x00000004);
  330. /* 6: ECO bits */
  331. reg32 = gtt_read(gtt_bar, 0xa180);
  332. reg32 |= (1 << 26) | (1 << 31);
  333. /* (bit 20=1 for SNB step D1+ / IVB A0+) */
  334. if (rev >= SNB_STEP_D1)
  335. reg32 |= (1 << 20);
  336. gtt_write(gtt_bar, 0xa180, reg32);
  337. /* 6a: for SnB step D2+ only */
  338. if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
  339. (rev >= SNB_STEP_D2)) {
  340. reg32 = gtt_read(gtt_bar, 0x9400);
  341. reg32 |= (1 << 7);
  342. gtt_write(gtt_bar, 0x9400, reg32);
  343. reg32 = gtt_read(gtt_bar, 0x941c);
  344. reg32 &= 0xf;
  345. reg32 |= (1 << 1);
  346. gtt_write(gtt_bar, 0x941c, reg32);
  347. gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
  348. }
  349. if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
  350. reg32 = gtt_read(gtt_bar, 0x907c);
  351. reg32 |= (1 << 16);
  352. gtt_write(gtt_bar, 0x907c, reg32);
  353. /* 6b: Clocking reset controls */
  354. gtt_write(gtt_bar, 0x9424, 0x00000001);
  355. } else {
  356. /* 6b: Clocking reset controls */
  357. gtt_write(gtt_bar, 0x9424, 0x00000000);
  358. }
  359. /* 7 */
  360. if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
  361. gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
  362. /* Mailbox Cmd for RC6 VID */
  363. gtt_write(gtt_bar, 0x138124, 0x80000004);
  364. if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
  365. gtt_write(gtt_bar, 0x138124, 0x8000000a);
  366. gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
  367. }
  368. /* 8 */
  369. gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
  370. gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
  371. gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
  372. gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
  373. gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
  374. gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
  375. /* 9 */
  376. gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
  377. gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
  378. gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
  379. /* 10 */
  380. gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
  381. gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
  382. gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
  383. gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
  384. gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
  385. /* 11 */
  386. gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
  387. gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
  388. gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
  389. gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
  390. gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
  391. gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
  392. gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
  393. /* 11a: Enable Render Standby (RC6) */
  394. if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
  395. /*
  396. * IvyBridge should also support DeepRenderStandby.
  397. *
  398. * Unfortunately it does not work reliably on all SKUs so
  399. * disable it here and it can be enabled by the kernel.
  400. */
  401. gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
  402. } else {
  403. gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
  404. }
  405. /* 12: Normal Frequency Request */
  406. /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
  407. reg32 = readl(MCHBAR_REG(0x5998));
  408. reg32 >>= 16;
  409. reg32 &= 0xef;
  410. reg32 <<= 25;
  411. gtt_write(gtt_bar, 0xa008, reg32);
  412. /* 13: RP Control */
  413. gtt_write(gtt_bar, 0xa024, 0x00000592);
  414. /* 14: Enable PM Interrupts */
  415. gtt_write(gtt_bar, 0x4402c, 0x03000076);
  416. /* Clear 0x6c024 [8:6] */
  417. reg32 = gtt_read(gtt_bar, 0x6c024);
  418. reg32 &= ~0x000001c0;
  419. gtt_write(gtt_bar, 0x6c024, reg32);
  420. return 0;
  421. }
  422. static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
  423. {
  424. const void *blob = gd->fdt_blob;
  425. int node = dev_of_offset(dev);
  426. u32 reg32, cycle_delay;
  427. debug("GT Power Management Init (post VBIOS)\n");
  428. /* 15: Deassert Force Wake */
  429. if (rev < IVB_STEP_C0) {
  430. gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
  431. gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
  432. } else {
  433. gtt_write(gtt_bar, 0xa188, 0x1fffe);
  434. if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
  435. gtt_write(gtt_bar, 0xa188,
  436. gtt_read(gtt_bar, 0xa188) | 1);
  437. }
  438. }
  439. /* 16: SW RC Control */
  440. gtt_write(gtt_bar, 0xa094, 0x00060000);
  441. /* Setup Digital Port Hotplug */
  442. reg32 = gtt_read(gtt_bar, 0xc4030);
  443. if (!reg32) {
  444. u32 dp_hotplug[3];
  445. if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
  446. dp_hotplug, ARRAY_SIZE(dp_hotplug)))
  447. return -EINVAL;
  448. reg32 = (dp_hotplug[0] & 0x7) << 2;
  449. reg32 |= (dp_hotplug[0] & 0x7) << 10;
  450. reg32 |= (dp_hotplug[0] & 0x7) << 18;
  451. gtt_write(gtt_bar, 0xc4030, reg32);
  452. }
  453. /* Setup Panel Power On Delays */
  454. reg32 = gtt_read(gtt_bar, 0xc7208);
  455. if (!reg32) {
  456. reg32 = (unsigned)fdtdec_get_int(blob, node,
  457. "panel-port-select", 0) << 30;
  458. reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
  459. << 16;
  460. reg32 |= fdtdec_get_int(blob, node,
  461. "panel-power-backlight-on-delay", 0);
  462. gtt_write(gtt_bar, 0xc7208, reg32);
  463. }
  464. /* Setup Panel Power Off Delays */
  465. reg32 = gtt_read(gtt_bar, 0xc720c);
  466. if (!reg32) {
  467. reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
  468. << 16;
  469. reg32 |= fdtdec_get_int(blob, node,
  470. "panel-power-backlight-off-delay", 0);
  471. gtt_write(gtt_bar, 0xc720c, reg32);
  472. }
  473. /* Setup Panel Power Cycle Delay */
  474. cycle_delay = fdtdec_get_int(blob, node,
  475. "intel,panel-power-cycle-delay", 0);
  476. if (cycle_delay) {
  477. reg32 = gtt_read(gtt_bar, 0xc7210);
  478. reg32 &= ~0xff;
  479. reg32 |= cycle_delay;
  480. gtt_write(gtt_bar, 0xc7210, reg32);
  481. }
  482. /* Enable Backlight if needed */
  483. reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
  484. if (reg32) {
  485. gtt_write(gtt_bar, 0x48250, (1 << 31));
  486. gtt_write(gtt_bar, 0x48254, reg32);
  487. }
  488. reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
  489. if (reg32) {
  490. gtt_write(gtt_bar, 0xc8250, (1 << 31));
  491. gtt_write(gtt_bar, 0xc8254, reg32);
  492. }
  493. return 0;
  494. }
  495. /*
  496. * Some vga option roms are used for several chipsets but they only have one
  497. * PCI ID in their header. If we encounter such an option rom, we need to do
  498. * the mapping ourselves.
  499. */
  500. uint32_t board_map_oprom_vendev(uint32_t vendev)
  501. {
  502. switch (vendev) {
  503. case 0x80860102: /* GT1 Desktop */
  504. case 0x8086010a: /* GT1 Server */
  505. case 0x80860112: /* GT2 Desktop */
  506. case 0x80860116: /* GT2 Mobile */
  507. case 0x80860122: /* GT2 Desktop >=1.3GHz */
  508. case 0x80860126: /* GT2 Mobile >=1.3GHz */
  509. case 0x80860156: /* IVB */
  510. case 0x80860166: /* IVB */
  511. return 0x80860106; /* GT1 Mobile */
  512. }
  513. return vendev;
  514. }
  515. static int int15_handler(void)
  516. {
  517. int res = 0;
  518. debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
  519. switch (M.x86.R_AX) {
  520. case 0x5f34:
  521. /*
  522. * Set Panel Fitting Hook:
  523. * bit 2 = Graphics Stretching
  524. * bit 1 = Text Stretching
  525. * bit 0 = Centering (do not set with bit1 or bit2)
  526. * 0 = video bios default
  527. */
  528. M.x86.R_AX = 0x005f;
  529. M.x86.R_CL = 0x00; /* Use video bios default */
  530. res = 1;
  531. break;
  532. case 0x5f35:
  533. /*
  534. * Boot Display Device Hook:
  535. * bit 0 = CRT
  536. * bit 1 = TV (eDP)
  537. * bit 2 = EFP
  538. * bit 3 = LFP
  539. * bit 4 = CRT2
  540. * bit 5 = TV2 (eDP)
  541. * bit 6 = EFP2
  542. * bit 7 = LFP2
  543. */
  544. M.x86.R_AX = 0x005f;
  545. M.x86.R_CX = 0x0000; /* Use video bios default */
  546. res = 1;
  547. break;
  548. case 0x5f51:
  549. /*
  550. * Hook to select active LFP configuration:
  551. * 00h = No LVDS, VBIOS does not enable LVDS
  552. * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
  553. * 02h = SVDO-LVDS, LFP driven by SVDO decoder
  554. * 03h = eDP, LFP Driven by Int-DisplayPort encoder
  555. */
  556. M.x86.R_AX = 0x005f;
  557. M.x86.R_CX = 0x0003; /* eDP */
  558. res = 1;
  559. break;
  560. case 0x5f70:
  561. switch (M.x86.R_CH) {
  562. case 0:
  563. /* Get Mux */
  564. M.x86.R_AX = 0x005f;
  565. M.x86.R_CX = 0x0000;
  566. res = 1;
  567. break;
  568. case 1:
  569. /* Set Mux */
  570. M.x86.R_AX = 0x005f;
  571. M.x86.R_CX = 0x0000;
  572. res = 1;
  573. break;
  574. case 2:
  575. /* Get SG/Non-SG mode */
  576. M.x86.R_AX = 0x005f;
  577. M.x86.R_CX = 0x0000;
  578. res = 1;
  579. break;
  580. default:
  581. /* Interrupt was not handled */
  582. debug("Unknown INT15 5f70 function: 0x%02x\n",
  583. M.x86.R_CH);
  584. break;
  585. }
  586. break;
  587. case 0x5fac:
  588. res = 1;
  589. break;
  590. default:
  591. debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
  592. break;
  593. }
  594. return res;
  595. }
  596. static void sandybridge_setup_graphics(struct udevice *dev,
  597. struct udevice *video_dev)
  598. {
  599. u32 reg32;
  600. u16 reg16;
  601. u8 reg8;
  602. dm_pci_read_config16(video_dev, PCI_DEVICE_ID, &reg16);
  603. switch (reg16) {
  604. case 0x0102: /* GT1 Desktop */
  605. case 0x0106: /* GT1 Mobile */
  606. case 0x010a: /* GT1 Server */
  607. case 0x0112: /* GT2 Desktop */
  608. case 0x0116: /* GT2 Mobile */
  609. case 0x0122: /* GT2 Desktop >=1.3GHz */
  610. case 0x0126: /* GT2 Mobile >=1.3GHz */
  611. case 0x0156: /* IvyBridge */
  612. case 0x0166: /* IvyBridge */
  613. break;
  614. default:
  615. debug("Graphics not supported by this CPU/chipset\n");
  616. return;
  617. }
  618. debug("Initialising Graphics\n");
  619. /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
  620. dm_pci_read_config16(dev, GGC, &reg16);
  621. reg16 &= ~0x00f8;
  622. reg16 |= 1 << 3;
  623. /* Program GTT memory by setting GGC[9:8] = 2MB */
  624. reg16 &= ~0x0300;
  625. reg16 |= 2 << 8;
  626. /* Enable VGA decode */
  627. reg16 &= ~0x0002;
  628. dm_pci_write_config16(dev, GGC, reg16);
  629. /* Enable 256MB aperture */
  630. dm_pci_read_config8(video_dev, MSAC, &reg8);
  631. reg8 &= ~0x06;
  632. reg8 |= 0x02;
  633. dm_pci_write_config8(video_dev, MSAC, reg8);
  634. /* Erratum workarounds */
  635. reg32 = readl(MCHBAR_REG(0x5f00));
  636. reg32 |= (1 << 9) | (1 << 10);
  637. writel(reg32, MCHBAR_REG(0x5f00));
  638. /* Enable SA Clock Gating */
  639. reg32 = readl(MCHBAR_REG(0x5f00));
  640. writel(reg32 | 1, MCHBAR_REG(0x5f00));
  641. /* GPU RC6 workaround for sighting 366252 */
  642. reg32 = readl(MCHBAR_REG(0x5d14));
  643. reg32 |= (1 << 31);
  644. writel(reg32, MCHBAR_REG(0x5d14));
  645. /* VLW */
  646. reg32 = readl(MCHBAR_REG(0x6120));
  647. reg32 &= ~(1 << 0);
  648. writel(reg32, MCHBAR_REG(0x6120));
  649. reg32 = readl(MCHBAR_REG(0x5418));
  650. reg32 |= (1 << 4) | (1 << 5);
  651. writel(reg32, MCHBAR_REG(0x5418));
  652. }
  653. static int gma_func0_init(struct udevice *dev)
  654. {
  655. struct udevice *nbridge;
  656. void *gtt_bar;
  657. u32 reg32;
  658. int ret;
  659. int rev;
  660. /* Enable PCH Display Port */
  661. writew(0x0010, RCB_REG(DISPBDF));
  662. setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
  663. ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
  664. if (ret)
  665. return ret;
  666. rev = bridge_silicon_revision(nbridge);
  667. sandybridge_setup_graphics(nbridge, dev);
  668. /* IGD needs to be Bus Master */
  669. dm_pci_read_config32(dev, PCI_COMMAND, &reg32);
  670. reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
  671. dm_pci_write_config32(dev, PCI_COMMAND, reg32);
  672. gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
  673. debug("GT bar %p\n", gtt_bar);
  674. ret = gma_pm_init_pre_vbios(gtt_bar, rev);
  675. if (ret)
  676. return ret;
  677. return rev;
  678. }
  679. static int bd82x6x_video_probe(struct udevice *dev)
  680. {
  681. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  682. ulong fbbase;
  683. void *gtt_bar;
  684. int ret, rev;
  685. rev = gma_func0_init(dev);
  686. if (rev < 0)
  687. return rev;
  688. ret = vbe_setup_video(dev, int15_handler);
  689. if (ret)
  690. return ret;
  691. /* Post VBIOS init */
  692. gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
  693. ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
  694. if (ret)
  695. return ret;
  696. /* Use write-combining for the graphics memory, 256MB */
  697. fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
  698. mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
  699. mtrr_commit(true);
  700. return 0;
  701. }
  702. static int bd82x6x_video_bind(struct udevice *dev)
  703. {
  704. struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
  705. /* Set the maximum supported resolution */
  706. uc_plat->size = 2560 * 1600 * 4;
  707. log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  708. return 0;
  709. }
  710. static const struct udevice_id bd82x6x_video_ids[] = {
  711. { .compatible = "intel,gma" },
  712. { }
  713. };
  714. U_BOOT_DRIVER(bd82x6x_video) = {
  715. .name = "bd82x6x_video",
  716. .id = UCLASS_VIDEO,
  717. .of_match = bd82x6x_video_ids,
  718. .bind = bd82x6x_video_bind,
  719. .probe = bd82x6x_video_probe,
  720. };